TLE 4269
Semiconductor Group 1 1998-11-01
Functional Description
This device is a voltage regulator with a fixed 5-V
output, e.g. in a P-DSO-8-1 package. The maximum
operating vol tage is 45 V. The output is ab le to drive a
150 mA load. It is short circuit protected and the
thermal shutdown switches the output off if the junction
temperature is in excess of 150 °C. A reset signal is
generated for an output voltage of VQ<4.6V. The
reset threshold voltage can be decreased by external
connection of a voltage divider. The reset delay time
can be set by an external capacitor. Reset and sense
output have integrated pull up resistors. If the
integrated resistors are not desired TLE 4279 can be
used. It is also possible to su pervise the input vo ltage
by using an integrated comparator to give a low voltage
warning.
5-V Low-Drop Fixed Voltage Regulator TLE 4269
P-DIP-8-4
P-DSO-8-1
P-DSO-20-6
P-DSO-14-4
Features
●Output voltage tolerance ≤ ± 2 %
●Very low current consumption
●Early warning
●Reset output low doown to VQ = 1 V
●Overtemperature protection
●Reverse polarity proof
●Settable reset threshold
●Very low drop voltage
●Wide temperature range
●Integrated pull up resistor at logic outputs
▼ New type
Type Ordering Code Package
TLE 4269 A Q67000-A91 90 P-DIP-8-4
TLE 4269 G Q67006-A9173 P-DSO-8-1 (SMD)
▼TLE 4269 GM Q67006-A9288 P-DSO-14-4 (SMD)
TLE 4269 GL Q67006-A9192 P-DSO-20-6 (SMD)
TLE 4269
Semiconductor Group 2 1998-11-01
Pin Configuration
(top view)
Pin Definitions and Functions (TLE 4269 A and TLE 4269 G)
Pin No. Symbol Function
1IInput; block directly to GND on the IC with a ceramic capacitor.
2SISense Input; if not needed connect to Q.
3REReset Threshold; if not needed connect to ground.
4DReset Delay; to select delay time, connect to GND via external
capacitor.
5GNDGround
6RReset Output; the open-collector output is internally linked to Q
via a 20 kΩ pull- up resis tor.
7SOSense Output; the open-collector output is internally linked to the
output via a 20 kΩ pull-up resistor.
8Q5-V Output; connect to GND with a 10 µF capacitor, ESR < 10 Ω.
GND
R
SO
D5
6
7
RE
8
4
3
2
1
AEP01668
Q
ΙSΙ
P-DIP-8-4 P-DSO-8-1
S
AEP01813
18
SO72
R63
GNDD54
RE
ΙQ
Ι
TLE 4269
Semiconductor Group 3 1998-11-01
Pin Configuration
(top view)
Pin Definitions and Functions (TLE 4269 GM)
Pin No. Symbol Function
1REReset Threshold; if not needed connect to GND.
2DReset Delay; connect to GND via external delay capacitor for
setting delay time.
3, 4, 5, 6 GND Ground
7RReset Output; open-collector output, internally connected to Q
via a pull-up resistor of 20 kΩ.
8SOSense Output; open-collector output, internally connected to Q
via a 20 kΩ pull-up resistor.
9Q5-V Output; connect to GND with a 10 µF capacitor, ESR < 10 Ω.
10, 11, 12 GND Ground
13 IInput; block to GND directly at the IC by a ceramic capacitor.
14 SI Sense Input; if not needed connect to Q.
P-DSO-14-4
AEP02248
Q
GND
SI
GND
R
GND Ι
10
9
GND GND
1
2
3
4
5
GND
6
7SO
14
13
12
11
D
GND
8
RE
TLE 4269
Semiconductor Group 4 1998-11-01
Pin Configuration
(top view)
Pin Definitions and Functions (TLE 4269 GL)
Pin No. Symbol Function
1REReset Threshold; if not needed connect to GND.
2DReset Delay; to select delay time connect to GND via external
capacitor.
4-7, 14-17 GND Ground
10 R Reset Output; the open-collector output is internally linked to
Q via 20 kΩ pull-up resistor.
11 SO Sense Output; the open-collector output is internally linked to
Q via 20 kΩ pull-up resistor.
12 Q Output; connect to GND with a 10 µF capacitor, ESR < 10 Ω.
19 IInput; block directly to GND at the IC by a ceramic capacitor.
20 SI Sense Input; if not needed connect to Q.
P-DSO-20-6
N.C.
12
11
N.C.
N.C.
GND
1
2
3
4
20
5
19
6
18
7N.C.
17
8Q
16
9
15
10
14
13
RE
D
GND
Ι
AEP01802
N.C.
GND
GND
R
S
GND
SO
GND
GND
GND
Ι
TLE 4269
Semiconductor Group 5 1998-11-01
Circuit Description
The control amplifier compares a reference voltage, made highly accurate by resistance
balancing, with a voltage proportional to the output voltage and drives the base of the
series PNP transistor via a buffer. Saturation control as a function of the load current
prevents any over-saturation of the power element.
In the reset generator block a comparator compares a reference voltage independent of
the input voltage with the scaled-down output voltage. If the output voltage reaches 4.6 V
the reset delay capacitor is discharged and the reset output is set to low. This low is
guaranteed down to an output voltage of 1 V. As the output voltage increases again,
from 4.6 V onward the reset delay capacitor is charged with constant current. When the
capacitor voltage reaches the upper switching threshold VdT, the reset returns to high. By
choosing the value of this capacitor, the reset delay time can be selected over a wide
range. With the rese t t hresh old in put RE it is po ss ible to lo we r the reset thres hol d Vrt. If
pin RE is connected to pin Q via a voltage divider, for example, the reset condition is
reached when this voltage is decreased below the switching threshold Vre of 1.35 V.
Another comparator compares the signal of the pin SI, normally fed by a voltage divider
from the input voltage, with the reference and gives an early warning on the pin SO. It is
also possible to superwise an other voltage e.g. of a second regulator, or to build a
watchdog circuit with few external components.
Application Description
The input capacitor CI is necessary for compensating line influences. Using a resistor of
approx. 1 Ω in series with CI, the oscillating circuit consisting of input inductivity and input
ca pacita nce c an be damp ed. Th e out put c apac itor CQ is necessary for the stability of the
regulating circuit. Stability is guaranteed at values ≥10 µF and an ESR ≤10 Ω within the
operating te mperature range. Fo r small toleranc es of the rese t delay the spread of the
capacitance of the delay capacitor and its temperature coefficient should be noted.
TLE 4269
Semiconductor Group 6 1998-11-01
Block Diagram
AEB01669
Control
Saturation
Current and
Reference
Trimming
20 kΩΩk20
Amplifier
Error
Reference
Ι
D
RE
SI
Q
R
SO
TLE 4269
Semiconductor Group 7 1998-11-01
Absolute Maximum Ratings
Tj=–40 to 150 °C
Parameter Symbol Limit Values Unit Notes
min. max.
Input
Input voltage VI–40 45 V –
Input current II– – – internal limited
Sense Input
Input voltage VSI–0.3 45 V –
Input current ISI11mA–
Reset Threshold
Voltage VRE –0.3 7 V –
Current IRE –10 10 mA –
Reset Delay
Voltage VD–0.3 7 V –
Current ID– – – internal limited
Ground
Current IGND 50 – mA –
Reset Output
Voltage VR–0.3 7 V –
Current IR– – – internal limited
TLE 4269
Semiconductor Group 8 1998-11-01
Sense Output
Voltage VSO –0.3 7 V –
Current ISO – – – internal limited
5-V Output
Output voltage VQ–0.3 7 V –
Output current IQ–5 – mA –
Temperature
Junction temperature Tj– 150 °C–
Storage temp eratu re TStg –50 150 °C–
Operating Range
Input volt age VI–45V –
Junction temperature Tj–40 150 °C–
Thermal Data
Junction-ambient Rthja – 100
200
70
70
K/W
K/W
K/W
K/W
P-DIP-8-4
P-DSO-8-1
P-DSO-14-4
P-DSO-20-6
Rthjc –60
60
30
30
K/W
K/W
K/W
K/W
P-DIP-8-4
P-DSO-8-1
P-DSO-14-4
P-DSO-20-6
Absolute Maximum Ratings (cont’d)
Tj=–40 to 150 °C
Parameter Symbol Limit Values Unit Notes
min. max.
TLE 4269
Semiconductor Group 9 1998-11-01
Characteristics
VI=13.5V; Tj=–40 °C<Tj< 125 °C
Parameter Symbol Limit Values Unit Measuring
Condition
min. typ. max.
Output vol tage VQ4.90 5.00 5.10 V 1 mA ≤ IQ≤100 mA
6V≤ VI≤16 V
Current limit IQ150 200 500 mA –
Current consumption;
Iq=II–IQ
Iq– 150 300 µAIQ≤1mA,Tj<85°C
Current consumption;
Iq=II–IQ
Iq– 250 700 µAIQ=10mA
Current consumption;
Iq=II–IQ
Iq–28 mAIQ=50mA
Drop vol tage Vdr –0.250.5VIQ= 100 mA1)
1) Drop voltage = VI–VQ (measured when the output voltage has dropped 100 mV from the
nominal value obtained at 13.5 V input.)
Load regulation ∆VQ–1030mVIQ= 5 mA to 100 mA
Line regulation ∆VQ–1040mVVI= 6 V to 26 V
IQ=1mA
Reset Generator
Switch ing thres hol d Vrt 4.50 4.60 4.80 V –
Reset pull up – 10 20 40 kΩ–
Reset low voltage VR–0.10.4VRintern
Delay switching
threshold Vdt 1.4 1.8 2.2 V –
Switch ing thres hol d Vst 0.3 0.45 0.60 V –
Reset delay low voltag e VD–0.1VVQ<VRT
Charge current Id3.0 6.5 9.5 µAVD=1V
TLE 4269
Semiconductor Group 10 1998-11-01
Characteristics (cont’d)
VI= 13.5 V; Tj=–40 °C<Tj< 125 °C
Parameter Symbol Limit Values Unit Measuring
Condition
min. typ. max.
Delay time L → Htd17 28 –msCD=100nF
Delay time H → Ltt–1– µsCD=100nF
Switching voltage Vre 1.26 1.35 1.44 V VQ>3.5V
Input Voltage Sense
Sense threshold high Vsi, high 1.24 1.31 1.38 V –
Sense threshold low Vsi, low 1.16 1.20 1.28 V –
Sense output
low voltage VSO, l ow –0.10.4VVSI <1.20V;
Vi>3V
Rintern
Sense pull up – 10 20 40 kΩ–
Sense input current ISI –10.11 µA–
TLE 4269
Semiconductor Group 11 1998-11-01
Measuring Circuit (P-DIP-8-4/P-DSO-8-1)
Reset Timing Diagram
AES01670
1000 Fµ
V
ΙQ
V
Ι
Ι
Ι
D
Ι
GND
Ι
Q
C
D
100 nF
Ι
RE
22 Fµ
470 nF
SO
V
TLE 4269
1
23
8
C
Ι
V
SΙ
V
R
V
RE
4567
Ι
D
V
ΙS
Q
C
AED01542
Thermal
t
d
Power-on-Reset Voltage Dip Secondary Overload
at OutputSpike
V
ST
V
Ι
V
D
V
RO
d
Ι
=
V
d
dt
V
Q
RT
V
t
RR
<
RR
t
V
DT
at Input Undervoltage
Shutdown
C
D
TLE 4269
Semiconductor Group 12 1998-11-01
Sence Timing Diagram
AED02559
t
Sense
t
SI, High
V
SI, Low
V
Input
Voltage
High
Low
Output
Sense
Semiconductor Group 13 1998-11-01
TLE 4269
Charg e Current Id versus
Temperature Tj
Drop Voltage Vdr versus
Output Current IQ
Switching Voltage Vdt and Vst versus
Temperature Tj
Reset Switching Threshold Vre
versus Temperature Tj
AED01803
-40
Ι
d
04080120 C160
0
Ι
V
= 13.5 V
2
4
6
8
10
12
14
16
Aµ
1.0 V=
V
C
j
T
AED01805
0
V
dr
mV
0
=25C
Ι
Q
30 60 90 120 180mA
C125=
100
200
300
400
500
j
T
j
T
AED01804
-40
V
04080120 C 160
0
Ι
V
= 13.5 V
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
V
V
st
dt
V
D
j
T
AED01806
-40
V
re
04080120 C160
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
V
j
T
Semiconductor Group 14 1998-11-01
TLE 4269
Current Consumption IQ versus
Input Voltage VI
Sense Threshold Vsi
versus Temperature Tj
Output Voltage VQ versus
Input Voltage VI
Output Voltage VQ versus
Temperature Tj
AED01807
0
Ι
q
mA
10 20 30 40 V50
0
5
10
15
20
25
30
Ι
V
R
L
=50
Ω
Ω
33=
L
R
Ω
100=
L
R
R
L
= 200
Ω
AED01809
-40 04080120 C160
1.0
Ι
V
= 13.5 V
V
si
1.1
1.2
1.3
1.4
1.5
1.6
V
Sense Output High
Sense Output Low
j
T
AED01808
0
V
Q
V
2468V10
0
2
4
6
8
10
12
Ι
V
R
L
=50
Ω
AED01671
-40
V
Q
V
04080
120 C 160
4.6
4.7
4.8
4.9
5.0
5.1
Ι
V
= 13.5 V
5.2
j
T
Semiconductor Group 15 1998-11-01
TLE 4269
Output Current IQ versus
Input Voltage VI
Current Consumption Iq versus
Output Current IQ
Current Consumption Iq versus
Output Current IQ
AED01810
0
Ι
Q
mA
10 20 30 40 V50
0
=25C
Ι
V
50
100
150
200
250
300
350
C125=
j
T
j
T
AED01812
0
Ι
q
mA
0
=25C
Ι
Q
13.5 V=
V
Ι
mA
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
10 20 30 40 50
j
T
AED01811
0
Ι
q
mA
0
=25C
Ι
Q
13.5 V=
V
Ι
20 40 60 80 120mA
2
4
6
8
10
12
j
T
TLE 4269
Semiconductor Group 16 1998-11-01
Package Outlines
P-DIP-8-4
(Plastic Dual In-li ne)
GPD05583
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Infor mation” Dimensions in mm
TLE 4269
Semiconductor Group 17 1998-11-01
1.27
1.45
-0.2
17
8.75
-0.2
14 8
1.75 max
0.2
6
±0.2
0.35 x 45˚
-0.2
4
0.1
-0.1
0.4
+0.8
Index Marking
1)
+0.15
0.35
2)
2) Does not include dambar protrusion of 0.05 max. per side
1) Does not include plastic or metal protrusion of 0.15 max. per side
0.2 14x
1)
0.19
+0.06
8˚ max.
GPS05093
P-DSO-14-4 (SMD)
(Plastic Dual Small Outline)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Infor mation” Dimensions in mm
SMD = Surface Mounted Device
TLE 4269
Semiconductor Group 18 1998-11-01
P-DSO-8-1 (SMD)
(Plastic Dual Small Outline)
GPS05121
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Infor mation” Dimensions in mm
SMD = Surface Mounted Device
TLE 4269
Semiconductor Group 19 1998-11-01
110
1120
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
GPS05094
2.65 max
0.1
0.2
-0.1
2.45
-0.2
+0.15
0.35
1.27
2)
0.2 24x
-0.2
7.6
1)
0.35 x 45˚
0.23
8˚ max
+0.09
+0.8
±0.3
10.3
0.4
12.8
-0.21)
P-DSO-20-6 (SMD)
(Plastic Dual Small Outline)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Infor mation” Dimensions in mm
SMD = Surface Mounted Device