Addendum Rev. 1, 2004-02-02 QuadFALC(R) Quad E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications PEB 22554 HT, Version 1.3 Abstract This document is an Addendum to the PEB 22554 HT, QuadFALC(R), Version 1.3 Data Sheet DS1, release date 2000-07. It describes data that has to be changed or added. The major part of the listed items have been documented already in the Errata Sheet as "Data Sheet Errata". Revision History: Previous Version: Major Changes: Addendum -/- Changes compared to the Errata Sheet (revision DS6) are marked by change bars. 1 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Text Corrections 1 Table 1 Text Corrections Text Corrections Page 7 The following references are added to the list of international standards: ITU-T G.705 ITU.T G.733 ITU-JT G.733 Page 27, Figure 4 "BHE/BLE" should read "BHE/BLE" Page 36, Table 3 CMR1.RS1...0 = 10: Dejittered clock generated by the internal DCO-R circuit. The clock frequency is 2.048 MHz (E1 or T1/J1 and SIC2.SSC2 = 10) or 1.544 MHz (T1/J1 and SIC2.SSC2 = 01). CMR1.RS1...0 = 11: Dejittered clock generated by the internal DCO-R circuit. The clock frequency is 8.192 MHz (E1 or T1/J1 and SIC2.SSC2 = 10) or 6.176 MHz (T1/J1 and SIC2.SSC2 = 01). Page 38, Table 4 After reset, SYPR of channel 1 port A is used, the other lines are ignored. Page 39, Table 4 CMR2.IRSP = 1: "Frame synchronization pulse generated by the DCO-R circuitry internally. Together with... is defined. This pulse is active low for a 2.048-MHz (E1) or 1.544-MHz (T1/J1) period." Page 40, Table 4 Receive Signaling Marker (RSIGM) PC(1...4).RPC(2...0) = 011 E1: Marks the time slots which are defined by register RTR1...4 of every received frame at port RDO. T1/J1: Marks the time slots which are defined by register RTR1...4 of every received frame on port RDO, if CAS-BR is not used. When using the CAS-BR signaling scheme, the robbed bit of each channel every six frames is marked, if it is enabled by XC0.BRM = 1. Page 50, Table 6 "BHE" should read "BHE" Page 50/51, Table 7 "BLE" should read "BLE" Addendum 2 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Text Corrections Table 1 Text Corrections (cont'd) Page 58, Figure 11 "FSC" should read "SEC/FSC" Page 60, Chapter 4.1.6 The following sentence is added: All code violations that do not correspond to zero substitution rules are detected resulting in an incrementation of the 16-bit code violation counter. If a bit error causes a code violation that leads to a valid substitution pattern, this code violation is not detected and the substitution pattern is replaced by the corresponding zero pattern. Page 69 In Table 15, the description "recommended: SYPR = output" should read "recommended: RFM" Page 104, 109 SD = system basic data rate (2.048 Mbit/s, 4.096, 8.192, or 16384 Mbit/s) Page 110, Figure 33/34 SIC3.RESX = 0 should read SIC3.RESX = 01 (rising edge) and SIC3.RESX = 1 should read SIC3.RESX = 10 (falling edge) Page 117, Figure 39 "FSC" should read "SEC/FSC" Page 119, Chapter 5.1.6 The following sentence is added: If a bit error causes a code violation that leads to a valid substitution pattern, this code violation is not detected and the substitution pattern is replaced by the corresponding zero pattern. Further more the corresponding error counter is not incremented Page 130 In Table 31, the description "recommended: SYPR = output" should read "recommended: RFM" Page 166, 176 SD = system basic data rate (1.544, 3.088, 6.176, or 12.352 Mbit/s) Page 185, 191 In chapter 6.3 (7.3), "Device Initialization in E1(T1/J1) Mode", the following sentences are added: The activity level of port XMFS can be selected to be active high or active low by programming PC5.CXMFS. This bit must not be set, if XMFS is not enabled as an input. XMFS input selection is done by programming one of the Transmit Multifunction Ports, using registers PC4(4:1).XPC(3:0). Note: XMFS must not be used together with SYPX on different Multifunction Ports. Addendum 3 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Text Corrections Table 1 Text Corrections (cont'd) Page 200, Figure 74 "CCR3.RCRC" and "CCR3.RADD" should read "CCR2.RCRC" and "CCR2.RADD". Page 214 CMDR.RMC: Confirmation from CPU to QuadFALC that the current frame or data block has been fetched following an RPF or RME interrupt, thus the occupied space in the RFIFO can be released. While the FIFO is empty, RMC must not be set. If RMC is given while RFIFO is already cleared, the next incoming data block is cleared instantly, although interrupts are generated. This might lead to incorrect software behavior. Page 234 with SC = system clock defined by SIC1.SSC1/0 + SIC2.SSC2 with SD = system data rate 2.048 Mbit/s See page 109 for further description. Page 238 XPM04...00:1BH or 27 decimal XPM14...10:1BH or 27 decimal XPM24...20:00H XPM34...30:00H Programming values for XPM0...2: 9C7BH, 03H, 00H Page 241 "LCR1.LLBF" should read "LCR1.FLLB" Page 244 The following sentence is added: JATT is only used to define the jitter attenuation during remote loop operation. Jitter attenuation during normal operation is not affected. Page 248 The line loopback code is transmitted in unframed mode. LLB code does not overwrite the framing FS/DL-bits. Page 252 Addition to description of RESX: CMR2.IXSC = 1: value of RESX bit has no impact on the selected edge of the PCM highway clock but value of RESR bit is used as RESX. Example: If RESR = 0, the rising edge of PCM highway clock is the selected one for sampling data on XDI and vice versa. Page 253 Addition to description of RESR: If bit CMR2.IRSP is set, the behavior of signal RFM (if used) is inverse (1 = falling edge, 0 = rising edge). Addendum 4 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Text Corrections Table 1 Text Corrections (cont'd) Page 254 "CMR2.DXSS" should read "CMR1.DXSS" Page 255 DCF = 0: The DCO-R circuitry is frequency centered - in master mode if no 2.048-MHz reference clock on pin SYNC is provided or - in slave mode if a loss of signal occurs in combination with no 2.048-MHz clock on pin SYNC or - a gapped clock is provided at pin RCLKI and this clock is inactive or stopped. Page 255 IRSP = 0: The frame sync pulse for the receive system interface is sourced by SYPR (if SYPR is applied). If SYPR is not applied, the frame sync pulse is derived from the RDO output signal internally (free running). The use of IRSP = 0 is recommended. IRSP = 1: The frame sync pulse for the receive system interface is internally sourced by the DCO-R circuitry. This internally generated frame sync signal can be output (active low) on multi function ports RP(A to D) (RPC(2:0) = 001). Note: This is the only exception where the use of RFM and SYPR is allowed at the same time. Because only one set of offset registers (RC1/0) is available, programming is done by using the SYPR calculation formula in the same way as for the external SYPR pulse. Bit IRSC must be set for correct operation. Page 260 001...RFM: Receive Frame Marker (Output) CMR2.IRSP = 0: The Receive Frame Marker is active high for one 2.048MHz period during any bit position of the current frame. Programming of the bit position is done by using registers RC1/0. The internal time slot assigner is disabled. The RFM offset calculation formula has to be used. CMR2.IRSP = 1: Internally generated frame synchronization pulse sourced by the DCO-R circuitry. Together with registers RC1/0 the frame begin on the receive system interface is defined. The pulse is active low for one 2.048-MHz period. The SYPR offset calculation formula has to be used. Page 261 010...RMFB: Receive Multiframe Begin (Output) RMFB is only valid, if the receive buffer is not bypassed. Addendum 5 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Text Corrections Table 1 Text Corrections (cont'd) Page 261 100...RSIG: Receive Signaling Data (Output) RSIG is only valid, if the receive buffer is not bypassed. Page 283 "A data stream containing all zeros..." should read "A data stream containing all zeros or all ones..." Page 304 The reset value for register CIS is "x0000000B", undefined bit positions CIS(7:4) should be ignored. Page 310 CMDR.RMC: Confirmation from CPU to QuadFALC that the current frame or data block has been fetched following an RPF or RME interrupt, thus the occupied space in the RFIFO can be released. While the FIFO is empty, RMC must not be set. If RMC is given while RFIFO is already cleared, the next incoming data block is cleared instantly, although interrupts are generated. This might lead to incorrect software behavior. Page 325 MCSP/SSP = 10 is also available in T1 F12 mode to handle multiple terminal (FT-)framing candidates Page 332 with SD = system data rate 2.048 Mbit/s (system clocking n x 2.048 MHz) with SD = system data rate 1.544 Mbit/s (system clocking n x 1.544 MHz) See page 166 for further description. Page 335 with SD = 2.048 Mbit/s system data rate with SD = 1.544 Mbit/s system data rate See page 166 for further description. Page 343 The following sentence is added: JATT is only used to define the jitter attenuation during remote loop operation. Jitter attenuation during normal operation is not affected. Page 348 The line loopback code is transmitted in unframed mode. LLB code does not overwrite the FS/DL-bits. Page 351 This bit together with SIC1.SSC1/0 enables the system interface to run with a clock of 1.544, 3.088, 6.176 or 12.352 MHz (SSC2 = 1) or 2.048, 4.096, 8.192 or 16.384 MHz (SSC2 = 0). See also register SIC1.SSC1/0. Addendum 6 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Text Corrections Table 1 Text Corrections (cont'd) Page 353 Addition to description of RESX: CMR2.IXSC = 1: value of RESX bit has no impact on the selected edge of the PCM highway clock but value of RESR bit is used as RESX. Example: If RESR = 0, the rising edge of PCM highway clock is the selected one for sampling data on XDI and vice versa. Page 353 Addition to description of RESR: If bit CMR2.IRSP is set, the behavior of signal RFM (if used) is inverse (1 = falling edge, 0 = rising edge). Page 355 "CMR2.DXSS" should read "CMR1.DXSS" Page 356 DCF = 0: The DCO-R circuitry is frequency centered - in master mode if no 1.544- or 2.048-MHz reference clock on pin SYNC is provided or - in slave mode if a loss of signal occurs in combination with no 1.544- or 2.048-MHz clock on pin SYNC or - a gapped clock is provided at pin RCLKI and this clock is inactive or stopped. Page 356 IRSP = 0: The frame sync pulse for the receive system interface is sourced by SYPR (if SYPR is applied). If SYPR is not applied, the frame sync pulse is derived from the RDO output signal internally (free running). The use of IRSP = 0 is recommended. IRSP = 1: The frame sync pulse for the receive system interface is internally sourced by the DCO-R circuitry. This internally generated frame sync signal can be output (active low) on multi function ports RP(A to D) (RPC(2:0) = 001). Note: This is the only exception where the use of RFM and SYPR is allowed at the same time. Because only one set of offset registers (RC1/0) is available, programming is done by using the SYPR calculation formula in the same way as for the external SYPR pulse. Bit IRSC must be set for correct operation. Addendum 7 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Text Corrections Table 1 Text Corrections (cont'd) Page 361 001...RFM: Receive Frame Marker (Output) CMR2.IRSP = 0: The Receive Frame Marker is active high for one 2.0481.544-MHz period during any bit position of the current frame. Programming of the bit position is done by using registers RC1/0. The internal time slot assigner is disabled. The RFM offset calculation formula has to be used. CMR2.IRSP = 1: Internally generated frame synchronization pulse sourced by the DCO-R circuitry. Together with registers RC1/0 the frame begin on the receive system interface is defined. The pulse is active low for one 1.544-MHz period. The SYPR offset calculation formula has to be used. Page 361 010...RMFB: Receive Multiframe Begin (Output) RMFB is only valid, if the receive buffer is not bypassed. Page 362 100...RSIG: Receive Signaling Data (Output) RSIG is only valid, if the receive buffer is not bypassed. Page 362 RPC(2:0) = 111, RFSP The last sentence of this chapter shall read: "This marker is active low for 488 648 ns..." Page 363 0011 = TCLK: Transmit Clock (Input) A 1.544/6.176 MHz clock has to be sourced by the system if the internal generated transmit clock (DCO-X) is not used. Optionally this input is used as a synchronization clock for the DCO-X circuitry with a frequency of 1.544 or 2.0486.176 MHz. Page 382 "A data stream containing all zeros..." should read "A data stream containing all zeros or all ones..." Page 398 Transmit CAS Register Empty In F12 and F72 format this interrupt occurs every 24 frames to inform the user that new bit robbing data has to be may be written to the XS1...12 registers. Page 403 The reset value for register CIS is "x0000000B", undefined bit positions CIS(7:4) should be ignored. Addendum 8 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Table Corrections 2 Table Corrections 2.1 Page 383, Alarm Simulation Table 68 Alarm Simulation States Tested Alarms ESC(2:0) = 0 1 2 LFA 2.2 5 6 7 x Page 406, DC Characteristics Symbol Limit Values Min. Unit Notes Max. Transmitter output current IX 100 105 mA XL1, XL2 Page 407, DC Characteristics Parameter Symbol Limit Values Min. Receiver differential voltage of a mark (between RL1 and RL2) 2.4 4 x Parameter 2.3 3 Unit Notes Max. VR VDDR +0.3 5.25 V RL1, RL2 Page 406/408, DC Characteristics Parameter Symbol Limit Values Min. Average power supply current (digital line interface mode) Unit Notes Max. IDD 150 mA LIM1.DRS = 15) 5) System interface at 16 MHz, PRBS data Addendum 9 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Table Corrections 2.5 No. Page 414, Table 73 Parameter Limit Values Min. 1 Address, BHE setup time 2.6 No. Typ. Unit Max. 15 5 ns Page 421, Table 78 Parameter Limit Values Min. Typ. Unit Max. SCLKR input mode 1 RDO delay 0 45 35 ns 2 RSIGM, RMFB, DLR, RFM1), FREEZE, RSIG marker delay 0 55 45 ns SCLKR output mode 1A RDO delay -55 0 9 -20 20 ns 2A RSIGM, RMFB, DLR, RFM1), FREEZE, RSIG marker delay -55 0 9 -20 20 ns 1) Timing for RMF is valid only for active high polarity selection. Addendum 10 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Table Corrections 2.7 No. Page 422/423, Table 79 Parameter Limit Values Min. Typ. Unit Max. SCLKR output mode 3A SYPR/SYPX setup time 10 0 ns 4A SYPR/SYPX hold time 0 10 ns 6A XMFS setup time 10 0 ns 7A XMFS hold time 0 10 ns 2.8 No. Page 424, Table 80 Parameter Limit Values Min. Typ. Max. 0 9 -20 20 Unit SCLKR output mode 1A XMFB, DLX, XSIGM delay 2.9 No. ns Page 425, Table 81 Parameter Limit Values Min. Typ. Unit Max. SCLKR output mode 3A XSIG setup time 10 0 ns 4A XSIG hold time 20 10 ns Addendum 11 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Table Corrections 2.10 No. Page 430, Table 86 Parameter Limit Values Min. Typ. Unit Max. 1 SYNC high time 30 122 % ns 2 SYNC low time 30 122 % ns 2.11 Page 435/436, Table 90 Parameter Symbol Test Values Test Signal AIS 215-1 Pulse Mask Programming 2.12 XPM2 BD 00H XPM1 03H XPM0 00 BDH all-ones PRBS pattern Page 436, Table 91 Parameter Symbol Test Values Test Signal Pulse Mask Programming Addendum Unit Notes AIS 215-1 XPM2 9f 02H XPM1 27H XPM0 02 9FH 12 Unit Notes all-ones PRBS pattern Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Figure Corrections 3 Figure Corrections 3.1 Page 58/117 Receive Clock Selection (E1/T1/J1) The following figure has been added to chapter 4.1 and chapter 5.1, respectively. recovered clock channel 1 recovered clock channel 2 recovered clock channel 3 recovered clock channel 4 A DCO-R channel 1 A A: controlled by CMR1.DRSS(1:0) B: controlled by GPC1.R1S(1:0) DCO-R channel 2 A DCO-R channel 3 A DCO-R channel 4 C: controlled by CMR1.RS(1:0) C B RCLK1 C RCLK2 C RCLK3 C RCLK4 F0131_2 Figure (new) Receive Clock Selection Addendum 13 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Figure Corrections 3.2 Page 173, Transmit Signalling and Clocking SYPX SCLKX T TS31 XDI 4567 XSIG ABCD TS0 TS1 TS2 TS3 F 01 234567012 34567012 34567 A BCD A BCD FS/DLchannel T F ABCD Figure 63 TS4 0123 A BCD Idle-channel = Time slot offset (XC0, XC1) = FS/DL-bit = Signaling bits for time slots0...23, time slot mapping according to channel translation mode 0, read only during last frame of a multiframe F0136_2 2.048 MHz Transmit Signaling Clocking (T1/J1) 125 s SYPX SCLKX T TS23 TS0 TS1 TS23 XDI 4 5 6 7F 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 XSIG ABCDF ABCD ABCD A BCDF ESF XSIG ABABF ABAB ABAB ABABF F12 T F ABCD ABAB Figure 64 Addendum = Time slot offset (XC0, XC1) = FS/DL-bit = ESF signaling bits for time slots0...23 read only during last frame of a multiframe, = F12 signaling bits for time slots0...23 read only during last frame of a multiframe (bit positions 4/5) 0 1 2 3 4 5 6 7F F0137_2 1.544 MHz Transmit Signaling Highway (T1/J1) 14 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Figure Corrections 3.3 Page 174/175, Signaling Marker Examples Multiframe n (F12 for example) Frame 1 Frame 6 Frame 12 Frame 1 RDO XDI RMFB XMFB A: Channel Translation Mode 0 RDO XDI 24 FS/ DL 1 2 3 4 5 6 7 8 9 19 20 21 22 23 24 FS/ DL 1 FS/ DL 1 RSIGM1) XSIGM B: Channel Translation Mode 1 RDO XDI FS/ DL 1 2 3 4 5 6 19 20 21 22 23 24 RSIGM1) XSIGM Notes: 1) RSIGM and XSIGM are programmed to mark only channel 24 in this example (via RTR(4:1) and TTR(4:1)). F0267_1 Figure 65 Addendum Signaling Marker for CAS/CAS-CC Applications (T1/J1) 15 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Figure Corrections Multiframe n (F12 for example) Frame 1 Frame 6 Frame 12 Frame 1 RDO XDI RMFB XMFB A: Channel Translation Mode 0 RDO XDI RSIGM1) XSIGM 24 FS/ DL 1 2 3 4 5 6 7 8 9 19 20 21 22 23 24 FS/ DL 1 FS/ DL 1 2) B: Channel Translation Mode 1 RDO XDI FS/ DL 1 2 3 4 5 6 19 20 21 22 23 24 RSIGM1) XSIGM Notes: 1) RSIGM and XSIGM mark the robbed bit positions in frames 6 and 12 of each multiframe, if XCO.BRM is set high. 2) robbed-bit marker every sixth frame Figure 66 Addendum F0267_2 Signaling Marker for CAS-BR Applications (T1/J1) 16 Rev. 1, 2004-02-02 QuadFALC(R) PEB 22554 HT Figure Corrections 3.4 Page 421, System Interface Marker Timing positive edge timing 1) positive edge timing 1) negative edge timing1) negative edge timing 1) SCLKR 1(A) RDO RSIG RSIGM DLR RFM RMFB FREEZE 2(A) data valid 1(A) 2(A) data valid 1) active edge can be programmed to be positive or negative possible negative delay values are not explicitely drawn Figure 91 F0011 System Interface Marker Timing 3.5 Page 438, Protection Circuitry 1:1 RL1 R3 PTC A R2 B VDD RL2 VSS Fuse 1.25 A A R3 PTC Fuse 1.25 A (R) FALC RJ45 1:2.4 XL1 PTC R1 A B VDD XL2 VSS A PTC R1 Fuse 1.25 A A SMP 100LC-35 (~65 pF) F0262_2 B SMP P3500SC (~60 pF) Figure 105 Fuse 1.25 A Protection Circuitry Examples The circuit shown in Figure 105 has been checked against ITU-T K.20 and K.21 and fulfills the lightning surge tests. Addendum 17 Rev. 1, 2004-02-02