19-4932; Rev 5; 12/14
GENERAL DESCRIPTION
The DS2482-800 is an I2C-to-1-Wire bridge device
that interfaces directly to standard (100kHz max) or
fast (400kHz max) I2C masters to perform
bidirectional protocol conversion between the I2C
master and any downstream 1-Wire slave devices.
Relative to any attached 1-Wire slave device, the
DS2482-800 is a 1-Wire master. Internal factory-
trimmed timers relieve the system host processor
from generating time-critical 1-Wire waveforms,
supporting both standard and Overdrive 1-Wire
communication speeds. To optimize 1-Wire
waveform generation, the DS2482-800 performs
slew-rate control on rising and falling 1-Wire edges
and has a programmable feature to mask the fast
presence p ulse edge that som e 1-W ire slave devices
can generate. Programmable strong pullup features
support 1-Wire power delivery to 1-Wire devices such
as EEPROMs and sensors. The DS2482-800
combines these features with eight independent
1-Wire I/O channels. The I2C slave address
assignment is controlled by three binary address
inputs, resolving potential conflicts with other I2C
slave devices in the system.
APPLICATIONS
Wireless Base Stations
Central Office Switches
PBXs
Rack-Based Servers
Medical Clinical Diagnostic Equipment
TYPICAL OPERATING CIRCUIT
BENEFITS AND FEATURES
• Allows Easy Interface Between an I2C Micro Port
and a 1-Wire Slave
o I2C Host Interface Supports 100kHz and
400kHz I2C Communication Speeds
o 8 Channels of Independently Operated
1-Wire I/O
o 1-Wire Master I/O with Selectable Active or
Passive 1-Wire Pullup
o Provides Reset/Presence, 8-Bit, Single-Bit,
and 3-Bit 1-Wire I/O Sequences
o Standard and Overdrive 1-Wire
Communication Speeds
o Three Address Inputs for I2C Address
Assignment
• Minimizes Line Noise, Reducing System EMI
o Slew-Contr ol led 1-Wire Edges
• Supports EEPROMs, Temp Sensors, or Other
1-Wire Slaves That Have Momentary High Source
Current Modes
o Strong 1-Wire Pullup Provided by an
Internal Low-Impedance Signal Path
o PCTLZ Output to Optionally Control an
External MOSFET for Stronger Pullup
Requirements
• Wide Operating Range: 2.9V to 5.5V, -40°C to
+85°C
• 16-Pin SO Package (150 mils)
ORDERING INFORMATION
PART
TEMP
RANGE
PIN-
PACKAGE
DS2482S-800+
-40 to +85°C
16 SO
DS2482S-800+T&R
-40 to +85°C
16 SO
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IO2
IO1
IO0
GND
IO4
IO5
IO6
IO7
IO3
SCL
SDA
V
CC
NC
AD2
AD1
AD0
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
DS2482-800
8-Channel 1-
Wire M aster
DS2482-800: 8-Channel 1-Wire Master
2 of 23
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground
-0.5V, +6V
Maximum Current Into Any Pin
±20mA
Operating Temperature Range
-40°C to +85°C
Junction Temperature
+150°C
Storage Temperature Range
-55°C to +125°C
Lead Temperature (soldering, 10s)
+300°C
Soldering Temperature (reflow)
+260°C
Stresses beyond those listed under “Absol ute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operat ion of the device at these or any other conditions beyond those indicat ed in the operati onal sect ions of the specifications is
not implied. Exposure to the absolute maximum rating condit i ons for extended periods may aff ect device reliability.
ELECTRICAL CHARACTERISTI CS
(VCC = 2.9V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Suppl y Voltage VCC
3.3V
2.9
3.3
3.7
V
5V
4.5
5.0
5.5
Operating Current
ICC
(Note 1)
0.75
mA
1-Wire Input High VIH1
3.3V (Notes 2, 3)
1.9
V
5V (Notes 2, 3)
3.4
1-Wire Input Low VIL1
3.3V (Notes 2, 3)
0.75
V
5V (Notes 2, 3) 1.0
1-Wire Weak Pullup Resistor RWPU (Note 4) 800 1675 Ω
1-Wire Output Low
VOL1
At 4mA load
0.4
V
Active Pullup On Time tAPUOT
Standard (Notes 4, 16)
2.3
2.5
2.7
µs
Overdrive (Notes 4, 16)
0.4
0.5
0.6
Strong Pullup Voltage Drop ∆VSTRPU VCC ≥ 3.2V, 1.5mA load 0.3 V
VCC ≥ 5.2 V, 3mA load 0.5
3.3V Pulldown Slew Rate
(Note 6) PDSRC
Standard (3.3V ±10%)
1
4.2
V/µs
Overdrive (3.3V
±
10%)
5 22.1
5V Pulldo wn Slew Rate
(Note 6)
PDSRC
Standard (5.0V ±10%)
2
6.5
V/µs
Overdrive (5.0V ±10%)
10
40
3.3V Pullup Slew Rate (Note 6) PUSRC
Standard (3.3V ±10%)
0.8
4
V/µs
Overdrive (3.3V
±
10%)
2.7
20
5V Pullup Slew Rate (Note 6) PUSRC
Standard (5.0V ±10%)
1.3
6
V/µs
Overdrive (5.0V
±
10%)
3.4 31
Power-On Reset Trip Point VPOR 2.2 V
1-Wire TIMING (Note 15) See Figures 4, 5, and 6
Write 1/Read Low Time tW1L
Standard
7.6
8
8.4
µs
Overdrive 0.9 1 1.1
Read Sample Time tMSR Standard 13.3 14 15 µs
Overdrive
1.4
1.5
1.8
1-Wire Time Slot tslot Standard 65.8 69.3 72.8 µs
Overdrive
9.9
10.5
11.0
Fall Time High-to-Low at
Standard Speed (Note 6) tF1
3.3V to 0V (Note 5) 0.54 3.0
µs
5.0V to 0V (Note 5)
0.55
2.2
Fall Time High-to-Low at
Overdrive Speed (Note 6)
3.3V to 0V (Note 5)
0.10
0.59
5.0V to 0V (Note 5) 0.09 0.44
DS2482-800: 8-Channel 1-Wire Master
3 of 23
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Write 0 Low Time tW0L Standard 60 64 68 µs
Overdrive
7.1
7.5
7.9
Write 0 Recovery Time tREC0 Standard 5.0 5.3 5.6 µs
Overdrive
2.8
3.0
3.2
Reset Low Time tRSTL
Standard
570
600
630
µs
Overdrive
68.4
72
75.6
Presence-Detect Sample Time tMSP Standard 66.5 70 73.5 µs
Overdrive
7.1
7.5
7.9
Sampling for Short and
Interrupt tSI Standard 7.6 8 8.4 µs
Overdrive
0.7
0.75
0.8
Reset High Time tRSTH Standard 554.8 584 613.2 µs
Overdrive
70.3
74
77.7
I2C-Pins (Note 7) See Figure 9
LOW Level Input Voltage VIL VCC = 2.9V to 3.7V -0.5
0.25 ×
VCC
V
VCC = 4.5V to 5.5V
0.22 ×
VCC
HIGH Level Input Voltage VIH
0.7 ×
VCC
V
CC
+
0.5V
V
Hysteresis of Schmitt Trigger
Inputs
Vhys
0.05 ×
VCC
V
LOW Level Output Voltage at
3mA Sink Current
VOL 0.4 V
Output Fall Time from V
Ihmin
to
VILmax with a Bus Capacitance
from 10pF to 400pF
tof 60 250 ns
Pulse Width of Spikes that are
Suppressed by the Input Filter
tSP SDA and SCL pins only 50 ns
Input Current Each I/O Pin with
an Input Voltage Bet ween
0.1VCCmax and 0.9VCCmax
Ii (Notes 8, 9) -10 +10 µA
Input Capacitance
Ci
(Note 8)
10
pF
SCL Clock Frequency
fSCL
0
400
kHz
Hold Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated.
tHD:STA 0.6 µs
LOW Period of the SCL Clock
tLOW
1.3
µs
HIGH Period of the SCL Clock
tHIGH
0.6
µs
Setup Time for a Repeated
START Condition
tSU:STA 0.6 µs
Data Hold Time
tHD:DAT
(Notes 10, 11)
0.9
µs
Data Setup Time
tSU:DAT
(Note 12)
250
ns
Setup Time for STOP Condition
tSU:STO
0.6
µs
Bus Free Time Between a
STOP and START Condition
tBUF 1.3 µs
Capacitive Load for Each Bus
Line
Cb (Note 13) 400 pF
Oscillator Warm-U p Time
tOSCWUP
(Note 14)
100
µs
DS2482-800: 8-Channel 1-Wire Master
4 of 23
Note 5:
Fall time high to low (tF1) is derived from PDSRC, referenced from 0.9 × VCC to 0.1 × VCC.
Note 6:
These values apply at full load, i.e., 1nF at standard speed and 0.3nF at Overdrive speed. For reduced
load, the pulldown slew rate is slightly faster.
Note 7:
All I2C timing values are referred to VIHmin and VILmax levels.
Note 8:
Applies to SD A, SCL, and AD0, AD 1, AD2.
Note 9:
I/O pins of the DS2482 do not obstruct the SDA and SCL lines if VCC is switched off.
Note 10:
The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the V
IHmin
of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
Note 11:
The maximum t
HD
:
DAT
has only to be met if the device does not stretch the low period (t
LOW
) of the SCL
signal.
Note 12:
A Fast-mode I2C -bus device can be used in a standard-mode I2C -bus system, but the requirement
tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must
output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns (according to the
standard-mode I
2
C -bus specification) before the SCL line is released.
Note 13:
C
B
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
to I
2
C-Bus Specification v2.1 are allowed.
Note 14:
I2C communication should not take place for the max tOSCWUP time following a power-on reset.
Note 15:
Except for t
F1
, all 1-Wire timing specifications and t
APUOT
are derived from the same timing circuit.
Therefore, if one of these parameters is found to be off the typical value, it is safe to assume that all of
these parameters deviate from their typical value in the same direction and by the same degree.
PIN DESCRIPTION
Note 1:
Operating current with 1-Wire write byte sequence followed by continuous Read of Status Register at
400kHz in Overdrive.
Note 2:
With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the
passive pullup on threshold VIL1 may not be reached in the available time. With Overdrive speed the
capacitive load on the 1-Wire bus must not exceed 300pF.
Note 3:
Active pullup guaranteed to turn on between VIL1MAX and VIH1MIN.
Note 4:
Active or resistive pullup choice is configurable.
PIN
NAME
FUNCTION
1
IO3
IO Driver for 1-Wire Line #3
2
SCL
I2C Serial Clock Input; must be tied to VCC through a pullup resistor.
3
SDA
I2C Serial Data Input/Output; must be tied to VCC through a pullup resistor.
4
VCC
Power Supp l y Input
5
NC
Not Connected
6
AD2
I2C Address Inputs; must be tied to VCC or GND. These inputs determine the I2C slave
address of the device, see Figure 8.
7
AD1
8
AD0
9
IO7
IO Driver for 1-Wire Line #7
10
IO6
IO Driver for 1-Wire Line #6
11
IO5
IO Driver for 1-Wire Line #5
12
IO4
IO Driver for 1-Wire Line #4
13
GND
Ground Reference
14
IO0
IO Driver for 1-Wire Line #0
15
IO1
IO Driver for 1-Wire Line #1
16
IO2
IO Driver for 1-Wire Line #2
DS2482-800: 8-Channel 1-Wire Master
5 of 23
Figure 1. Block Diagram
I²C
Interface
Controller
SDA
SCL
Config
Register
I/O
Controller
Status
Register
Line
XCVR
Channel
Select
Line
XCVR
Line
XCVR
Line
XCVR
Line
XCVR
Line
XCVR
Line
XCVR
Line
XCVR
AD0
AD1
AD2
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
Read Data
Register
T-Time OSC
DETAILED DESCRIPTION
The DS2482-800 is a self-timed 8-channel 1-Wire master, which supports advanced 1-Wire waveform features
including standard and Overdrive speeds, active pullup, and strong pullup for power delivery. Once supplied with
command and data, the I/O controller of the DS2482 performs time-critical 1-Wire communication functions such as
reset/presence detect cycle, read-byte, write-byte, single-bit R/W and triplet for ROM Search, without requiring
interaction with the host processor. The host obtains feedback (completion of a 1-Wire function, presence pulse,
1-Wire short, search direction taken) through the Status Register and data through the Read Data register. The
DS2482 communicates with a host processor through its I2C bus interface in standard-mode or in fast-mode. The
logic state of three address pins (2 address pins with the 1-channel version) determines the I2C slave address of
the DS2482, allowing up to 8 devices operating on the same bus segment without requiring a hub.
DEVICE REGISTERS
The DS2482 has four registers that the I2C host can read: Channel Selection, Configuration, Status, and Read
Data. These registers are addressed by a read pointer. The position of the read pointer, i.e., the register that the
host will read in a subsequent read access, is defined by the instruction that the has DS2482 executed last. The
host has read and write access to the Channel Selection and Configuration Registers to select one of several
1-Wire channels and to enable certain 1-Wire features.
DS2482-800: 8-Channel 1-Wire Master
6 of 23
Channel Selection Registe r
The content of the Channel Sel ection Register specifies whic h of the channels is selected and wil l be the target of
subsequent 1-Wire communication commands. The DS2482-800 supports eight 1-Wire communication channels
IO0 to IO7. Only one of these channels can be active/selected at any time. Once selected, a 1-Wire channel
remains selected until a different channel is selected through the Channel Select command or by initiating a
device reset. After a device reset (power-up cycle or initiated by the Device Reset command) the IO0 channel is
selected.
Configura tion Register
The DS2482 supports allows three 1-Wire features that are enabled or selected through the Configuration Register.
These features are:
Active Pullup (APU)
Strong Pullup (SPU)
1-Wire Speed (1WS)
These features can be selected in any combination. They apply equally to all 1-Wire channels. While APU, PPM
and 1WS maintain their state, SPU returns to its inactive state as soon as the strong pullup has ended.
Configura tion Register Bit Assignment
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
1WS SPU 1 APU 1WS SPU 0 APU
After a device reset (power-up cycle or initiated by the Device Reset command) the Configuration Register reads
00h. When writing to the Configuration Register, the new data is accepted only if the upper nibble (bits 7 to 4) is the
one's complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.
Active Pullup (APU)
The APU bit controls whether an active pullup (controlled slew-rate transistor) or a passive pullup (RWPU resistor)
will be used to dr ive a 1-Wire line from low to high. W hen APU = 0, ac tive pul lup i s disable d (resis tor mode) . Active
Pullup should always be selected unless there is only a single slave on the 1-Wire line. The active pullup does
not apply to the rising edge of a p resence pulse or a recovery after a sh o rt on the 1-Wire line.
The circuit that controls rising edges (Figure 2) operates as follows: At t1 the pulldown (from DS2482 or 1-Wire
slave) ends. From this point on the 1-Wire bus is pulled high through RWPU internal to the DS2482. VCC and the
capacit ive load of the 1-W ire line determ ine the s lope. In cas e that active pu llup is dis abled (AP U = 0), the res istive
pullup co ntinues, as repr esented by the solid lin e. With active p ul lu p en abl ed ( AP U = 1), when at t2 the vo lta ge has
reached a level between VIL1max and VIH1min, the DS2482 actively pulls the 1-Wire line high applying a controlled
slew rate, as represented by the dashed line. The active pullup continues until tAPUOT is expired at t3. From that time
on the resistive pullup will continue.
Figure 2. Rising E dge Pullup
VCC
0V
1-Wire bus is
discharged
VIL1MAX
VIH1MIN
tAPUOT
t1
t2
t3
APU = 1
APU = 0
DS2482-800: 8-Channel 1-Wire Master
7 of 23
Strong P u llup (SPU)
The SPU bit controls whether the DS2482 applies a low-impedance pullup to VCC on the 1-Wire line after the last
bit of either a 1-Wire Write Byte command or after a 1-Wire Single Bit command has completed. The strong
pullup featur e is comm onl y used with 1-Wire EEPROM devices when c o p ying s cr atc hpad dat a to the main m emory
or when performing a SHA-1 computation, and with parasitically powered temperature sensors or A-to-D
converters. The respective device data sheets specify the location in the communications protocol after which the
strong pullup should be applied. The SPU bit in the configuration register of the DS2482 m ust be set imm ediately
prior to issuing the command that puts the 1-Wire device into the state where it needs the extra power.
If SPU is 1, the DS2482 applies active pullup to the rising edge of the time slot in which the strong pullup starts,
regardless of the APU bit setting. However, in contrast to setting APU = 1 for active pullup, the low-impedance
pullup will not end after tAPUOT is expired. Instead, as shown in Figure 3, the low-impedance pullup remains active
until: a) th e next 1-Wire communic ation com mand (the t ypical c ase) , b) by writing t o the C onf iguration Regi s ter with
the SPU bit being 0 (altern ative), or c) by issuing the Device Reset comm and. Additionall y, when the pullup ends,
the SPU bit is automatically reset to 0. Using the strong pullup does not change the state of the APU bit in the
Configuration Register. Note: Strong pullup also affects the 1-Wire Reset command. If enabled, it can cause
incorrect reading of the presence pulse and may cause a violation of the device's absolute maximum rating.
Figure 3. Low -Imped ance Pullup Timing
V
cc
0V
Write 1
Write 0
Edges with
active pull-up
Pull-up DS2482 P ul l -down DS2482 Low Impedance Pull -up
Next
Time
Slot
tSLOT
Last bit of 1-Wire Write Byte or 1-Wire Single Bit Function
DS2482-800: 8-Channel 1-Wire Master
8 of 23
1-Wire Speed (1WS)
The 1WS bit determines the timing of any 1-Wire communication generated by the DS2482. All 1-Wire slave
devices s upport standar d speed (1W S = 0), where the trans fer of a single bit (t SLOT in Figure 3) is com pleted within
65µs. Many 1-Wire device can also communicate at a higher data rate, called Overdrive speed. To change from
standard to Overdrive speed, a 1-W ire device needs t o receive an Overdrive Skip ROM or Overdr ive Match ROM
command, as explained in the device data sheets. The change in speed occurs immediately after the 1-Wire device
has received the speed-changing command code. The DS2482 must take part in this speed change to stay
synchron ized. T his is acc omplished b y writ ing to th e Configura tion R egister with the 1W S bit bei ng 1 immediately
after the 1-Wire Byte command that changes the speed of a 1-Wire device. Writing to the Configuration Register
with the 1WS bit being 0 followed by a 1-Wire Reset command changes the DS2482 and any 1-Wire devices on
the active 1-Wire line back to standard speed.
Status Register
The read-only Status Register is the general means for the DS2482 to report bit-type data from the 1-Wire side,
1-Wire busy status and its own reset status to the host processor. All 1-Wire communication commands and the
Device Res et command positio n the read po inter at the Stat us R egister for the host pr ocess or to read with m inim al
protocol o verhead. Status inf ormation is u pdated dur ing the execution of certain c omm ands only. Details are given
in the description of the various status bits below.
Status Register Bit Assign men t
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
DIR TSB SBR RST LL SD PPD 1WB
1-Wire Busy (1WB)
The 1WB bit reports to t he hos t pr oc ess or wheth er th e 1-Wire line is bus y. During 1-Wire communication 1WB is 1;
once the command is completed, 1WB returns to its default 0. Details on when 1WB changes state and for how
long it remains at 1 are found in the Function Commands section.
Presence Pulse Detect (PPD)
The PPD bit is u pdated with ever y 1-W ire Reset com mand. If the DS2482 detec ts a prese nce pu lse from a 1-Wire
device at tMSP during the Presence Detect cycle, the PPD bit will be set to 1. This bit will return to its default 0 if
there is no presence pulse or if the 1-Wire line is shorted during a subsequent 1-Wire Reset command.
Short Detected (SD)
The SD bit is updated with every 1-W ire Reset command. If the DS2482 detects a logic 0 on the 1-W ire line at tSI
during the Presence Detect cycle, the SD bit will be set to 1. This bit will return to its default 0 with a subsequent
1-Wire Reset command provided that t he short has been removed. If SD is 1, PPD will be 0. The DS2482 cannot
distinguish between a short and a DS1994 or DS2404 signaling a 1-Wire interrupt. For this reason, if a
DS2404/DS1994 is used in the application, the interrupt function must be disabled. The interrupt signaling is
explained in the respective device data sheets.
Logic Level (L L )
The LL bit reports the logic state of the active 1-W ire line without initiating any 1-Wire communication. T he 1-Wire
line is sampled for this purpose every time the Status Register is read. The sampling and updating of the LL bit
takes place when the host processor has addressed the DS2482 in read mode (during the acknowledge cycle),
provided that the Read Pointer is positioned at the Status Register.
Device Reset (RST)
If the RST bit is 1, the DS2482 has performed an internal reset cycle, either caused by a power-on reset or from
executing the Device Reset command. The RST bit is cleared automatically when the DS2482 executes a Write
Configuration command to restore the selection of the desired 1-Wire features.
DS2482-800: 8-Channel 1-Wire Master
9 of 23
Single Bit Result (SBR)
The SBR bit reports the log ic state of the active 1-W ire line sam pled at tMSR of a 1-Wire Single Bit comm and or the
first bit of a 1-W ire Triplet comm and. The power-on def ault of SBR is 0. If the 1-W ire Single Bit comm and sends a
0-bit, SBR s hould be 0. W ith a 1-W ire Triplet com mand, SBR could b e 0 as well as 1, depending on the r esponse
of the 1-Wire devices connected. The same result applies to a 1-Wire Single Bit command that sends a 1-bit.
Triplet Second Bit (TSB)
The TSB bit reports the logic state of the active 1-Wire line sampled at tMSR of the second bit of a 1-W ire Triplet
command. The power-on default of TSB is 0. This bit is updated only with a 1-Wire Triplet command and has no
function with oth er commands.
Branch Direction Taken (DI R)
Whenever a 1-Write Triplet command is executed, this bit reports to the host processor the search direction that
was chosen by the 3rd bit of the triplet. The power-on default of DIR is 0. This bit is updated only with a 1-Wire
Triplet command and has no function with other commands. For additional information see the description of the
1-Wire Triplet command and Application Note 187: 1-Wire Search Algorithm.
FUNCTION COMMANDS
The DS2482 understands nine function commands, which fall into four categories: device control, I2C
communication, 1-Wire setup and 1-Wire communication. The feedback path to the host is controlled by a read
pointer, which is s et autom aticall y by each f unctio n comm and f or the host to eff icientl y access relevant inform ation.
The host proc es sor s e nds these com mands and ap plic abl e p arameters as s tr ings of one or t wo bytes us ing the I2C
interface. The I2C protocol requires that each byte be acknowledged by the receiving part y to confirm acceptance
or not be acknowledged to indicate an error condition (invalid code or parameter) or to end the communication.
Details of the I2C protocol including acknowledge are found in the I2C interface description of this document.
Device Reset
Command Code
F0h
Command Parameter
None
Description
Performs a global reset of device state machine logic, which in turn
selects IO0 as the active 1-Wire channel.
Term inates any ongoing 1 -Wire communication.
Typical Use
Device initialization after power-up; re-initialization (reset) as desired.
Restriction
None (can be executed at any time)
Error Response
None
Command Dur ation
Maximum 525ns, counted from falling SCL edge of the command code
acknowledge bit.
1-Wire Activity
Ends maximum 262.5ns after the falling SCL edge of the command code
acknowledge bit.
Read Pointer Position
Status Register (for busy polling)
Status Bits Affected
RST set to 1,
1WB, PPD, SD, SBR, TSB, DIR set to 0
Configura tion Bits Affected
1WS, APU, SPU set to 0
DS2482-800: 8-Channel 1-Wire Master
10 of 23
Set Read Poin t er
Command Code
E1h
Command Parameter
Pointer Code
Description
Sets the read pointer to the specified register. Overwrites the read pointer
position of any 1-Wire communication command in progress.
Typical Use
To prepare reading the result from a 1-Wire Byte command; random read
access of registers.
Restriction
None (can be executed at any time)
Error Response
If the pointer code is not valid, the pointer code will not be acknowledged
and the command will be ignored.
Command Duration
None; the read pointer is updated on the rising SCL edge of the pointer
code acknowledge bit.
1-Wire Activity
Not Affected
Read Pointer Position
As Specified by the Pointer Code
Status Bits Affected
None
Configura tion Bits Affected
None
Valid Pointer Codes
Write Configura ti on
Command Code
D2h
Command Parameter
Configuration By te
Description
Writes a new config ur ati on b yte. The new settings take effect
immediately. NOTE: When writing to the Configuration Register, the new
data is accepted only if the upper nibble (bits 7 to 4) is the one's
complement of the lower nibble (bits 3 to 0). When read, the upper nibble
is always 0h.
Typical Use
Defining the features for subsequent 1-Wire communication.
Restriction
1-Wire activity must have ended before the DS2482 can process this
command.
Error Response
Command code and parameter will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
Command Dur ation
None; the configuration register is updated on the rising SCL edge of the
configuration byte acknowledge bit.
1-Wire Activity
None
Read Pointer Position
Configuration Register (to verify write)
Status Bits Affected
RST set to 0
Configura tion Bits Affected
1WS, SPU, APU updated
Register Selection Code
Status Register F0h
Read Data Register E1h
Channel Selection Register D2h
Configuration Register C3h
DS2482-800: 8-Channel 1-Wire Master
11 of 23
Channel Select
Command Code
C3h
Command Parameter
Selection Code
Description
Sets the 1-Wire IO channel for subsequent 1-Wire communication
commands. NOTE: The selection code read back is different from the
code written. See the table below for the respective values.
Typical Use
Selecting a 1-Wire IO channel other that IO0; randomly selecting one of
the available 1-Wire IO channels.
Restriction
1-Wire activity must have ended before the DS2482 can process this
command.
Error Response
Command code and parameter will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
If the selection code is not valid, the selection code will not be
acknowledged and the command will be ignored.
Command Dur ation
None; the channel selection register is updated on the rising SCL edge of
the selection code acknowledge bit.
1-Wire Activity
None
Read Pointer Position
Channel Selection Register (to verify write)
Status Bits Affected
None
Configura tion Bits Affected
None
Valid Channel Selection Codes
Channel Selection Code (to be written) Code (read back)
Channel IO0 (default) F0h B8h
Channel IO1 E1h B1h
Channel IO2 D2h AAh
Channel IO3 C3h A3h
Channel IO4 B4h 9Ch
Channel IO5 A5h 95h
Channel IO6 96h 8Eh
Channel IO7 87h 87h
Figure 4. 1-Wire Reset/Presence Detect Cycle
DS2482-800: 8-Channel 1-Wire Master
12 of 23
1-Wire Reset
Command Code
B4h
Command Parameter
None
Description
Generates a 1-Wire Reset/Presence Detect cycle (Figure 4) at the
selected IO channel. The state of the 1-Wire line is sampled at tSI and tMSP
and the result is reported to the host processor through the status register,
bits PPD and SD.
Typical Use
To initiate or end any 1-Wire communication sequence.
Restriction
1-Wire activity must have ended before the DS2482 can process this
command. Strong pullup (see SPU bit) should not be used in conjunction
with the 1-Wire Reset command. If SPU is enabled, the PPD bit may not
be valid and may cause a violation of the device's absolute maximum
rating.
Error Response
Command code will not be acknowledged if 1WB = 1 at the time the
command code is received and the command will be ignored.
Command Duration
t
RSTL
+ t
RSTH
+ maximum 262.5ns, counted from the falling SCL edge of the
command code acknowledge bit.
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the command
code acknowledge bit.
Read Pointer Position
Status Register (for busy polling)
Status Bits Affected
1WB (set to 1 for t
RSTL
+ t
RSTH
),
PPD is updated at tRSTL + tMSP,
SD is updated at tRSTL + tSI
Configura tion Bits Affected
1WS, APU, SPU apply
1-Wire Single Bit
Command Code
87h
Command Parameter
Bit Byte
Description
Generates a single 1-Wire time slot with a bit value ‘V’ as specified by the
bit byte at the selected 1-Wire IO channel. A ‘V’ value of 0b will generate a
write-zero time slot (Figure 5), a value of 1b will generate a write one slot,
which also functions as a read data time slot (Figure 6). In either case the
logic lev el at the 1-Wire line is tested at tMSR and SBR is updated.
Typical Use
To perform single bit writes or reads on a 1-Wire IO channel when single
bit communication is necessary (the exc epti on).
Restriction
1-Wire activity must have ended before the DS2482 can process this
command.
Error Response
Command code and bit byte will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
Command Dur ation
t
SLOT
+ maximum 262.5ns, counted from the falling SCL edge of the first
bit (MS bit) of the bit byte.
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the MS bit of the
bit byte.
Read Pointer Position
Status Register (for busy polling and data reading)
Status Bits Affected
1WB (set to 1 for t
SLOT
)
SBR is updated at tMSR
DIR (may change its state)
Configura tion Bits Affected
1WS, APU, SPU apply
Bit Allocation in the Bit Byte
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
V
x
x
x
x
x
x
x
x = don’t care
DS2482-800: 8-Channel 1-Wire Master
13 of 23
Figure 5. Write-0 Time Slot
Pullup (see Fig. 2) DS2482 Pulldo wn
t
REC0
V
cc
V
IH1
V
IL1
0V
t
F1
t
SLOT
t
W0L
t
MSR
Figure 6. Write-1 and Read-Dat a Time Sl ot
NOTE on Figure 7: Depending on its internal s tate, a 1-W ir e slave d evice will tr ansm it data to its mast er (e.g., the
DS2482). When responding with a 0, a 1-Wire slave will start pulling the line low during tW1L; its internal timing
generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, a
1-Wir e slave wil l n ot hol d t h e l ine l o w at al l, and th e vo lt age star ts ris i ng as s oo n a s tW1L is over. 1-Wire de vic e da ta
sheets use the term tRL instead of tW1L to describe a read-data time slot. Technically, tRL and tW1L have identical
specifications and cannot be distinguished from each other.
1-Wire Write Byte
Command Code
A5h
Command Parameter
Data Byte
Description
Writes single data byte to selected 1-Wire IO channel.
Typical Use
To write commands or data to a 1-Wire IO channel; equivalent to
executing eight 1-Wire Single Bit commands, but faster due to less I2C
traffic.
Restriction
1-Wire activity must have ended before the DS2482 can process this
command.
Error Response
Command code and data byte will not be acknowledged if 1WB = 1 at the
time the command code is received and the command will be ignored.
Command Dur ation
8 × t
SLOT
+ maximum 262.5ns, counted from falling edge of the last bit (LS
bit) of the data byte.
1-Wire Activity
Begins maximum 262.5ns after falling SCL edge of the LS bit of the data
byte (i.e., before the data byte acknowledge).
NOTE: The bit order on the I2C bus and the 1-Wire line is different.
(1-Wire: LS-bit first; I2C: MS-bit first) Therefore, 1-Wire activity cannot
begin before the DS2482 has received the full data byte.
Read Pointer Position
Status Register (for busy polling)
Status Bits Affected
1WB (set to 1 for 8 × tSLOT)
Configura tion Bits Affected
1WS, SPU, APU apply
DS2482-800: 8-Channel 1-Wire Master
14 of 23
1-Wire Read Byte
Command Code
96h
Command Parameter
None
Description
Generates ei ght read data time slots on the selected 1-Wire IO channel
and stores result in the Read Data Register.
Typical Use
To read data from a 1-Wire IO channel; equivalent to executing eight
1-Wire Single Bit commands with V = 1 (write 1 time slot), but faster due
to less I
2
C traffic.
Restriction
1-Wire activity must have ended before the DS2482 can process this
command.
Error Response
Command code will not be acknowledged if 1WB = 1 at the time the
command code is received and the command will be ignored.
Command Duration
8 × t
SLOT
+ maximum 262.5ns, counted from the falling SCL edge of the
command code acknowledge bit.
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the command
code acknowledge bit.
Read Pointer Position
Status Register (for busy polling)
NOTE: To read the data byte received from the 1-Wire IO channel, issue
the Set Read Pointer command and select the Read Data Register. Then
access the DS2482 in read mode.
Status Bits Affected
1WB (set to 1 for 8 × tSLOT)
Configuration Bits Affected
1WS, APU apply
1-Wire Triplet
Command Code
78h
Command Parameter
Direc tion Byte
Description
Generates three times slots, two read-time slots and one-write time slot, at
the selected 1-Wire IO channel. The type of write-time slot depends on the
result of the read-time slots and the direction byte.
The direction byte determines the type of write-time slot if both read-time
slots are 0 (a ty pical case). In this case the DS2482 will generate a write-1
time slot if V = 1 and a write-0 time slot if V = 0.
If the read-time slots are 0 and 1, there will follow a write 0 time slot.
If the read-time slots are 1 and 0, there will follow a write 1 time slot.
If the read-time slots are both 1 (error case), the subsequent write time
slot will be a write 1.
Typical Use
To perform a 1-Wire Search ROM sequence; a full sequence requires this
command to be executed 64 times to identify and address one device.
Restriction
1-Wire activity must have ended before the DS2482 can process this
command.
Error Response
Command code and direction byte will not be acknowledged if 1WB = 1 at
the time the command code is received and the command will be ignored.
Command Dur ation
3 × t
SLOT
+ maximum 262.5ns, counted from the falling SCL edge of the
first bit (MS bit) of the direction byte.
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the MS bit of the
direction b yte.
Read Pointer Position
Status Register (for busy polling)
Status Bits Affected
1WB (set to 1 for 3 × t
SLOT
)
SBR is updated at the first tMSR
TSB and DIR are updated at the second tMSR (i.e., at tSLOT + tMSR)
Configura tion Bits Affected
1WS, APU apply
DS2482-800: 8-Channel 1-Wire Master
15 of 23
Bit Allocation in the Direction Byte
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
V
x
x
x
x
x
x
x
x = don’t care
I2C INTERFACE
General Characteristics
The I2C bus uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are
bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no
communication, both lin es are HIGH. T he output stages of devices connected to the bus m ust have an open-drain
or open-collector to perform the wired-AND function. Data on the I2C bus can be transferred at rates of up to
100kbps in the Standard-mode, up to 400kbps in the Fast-mode. The DS2482 works in both modes.
A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The
device that controls the communication is called a “master.” The devices that are controlled by the master are
“slaves.” To be individually accessed, each device must have a slave address that does not conflict with other
devices on the bus.
Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL),
controls the bus access, generates the START and STOP conditions, and determines the number of data bytes
transferred between START and STOP (Figure 7). Data is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave.
Figure 7. I2C Protocol Overview
SCL
SDA
1
2
6
7
8
ACK
9
9
1
2
8
MS-bit
R/W
Slave Address
ACK
bit
Acknowledgment
from Receiver
ACK
bit
START
Condition
ACK
Repeated if more bytes
are transferred
STOP Condition
Repeated START
Condition
Idle
Slave Address
The slave address to wh ich the DS248 2 responds is shown in Figure 8. The logi c states at the a ddress pin s AD0,
AD1 and AD2 determine the value of the address bits A0, A1, and A2. The address pins allow the device to
respond t o one of eig ht possible sl ave addres ses. T he slave addres s is part of the slave-a ddress/c ontrol byte. T he
last bit of the slave-address/control byte (R/W) defines the data direction. When set to a 0, subsequent data will
flow from master to slave (write access); when set to a 1, data will flow from slave to master (read access).
DS2482-800: 8-Channel 1-Wire Master
16 of 23
Figure 8. DS2482 Slave Address
A6
A5
A4
A3
A2
A1
A0
0
0
1
1
AD2
AD1
AD0
R/W
7-Bit Slave Address
Most Signi-
ficant Bit
Determines
Read or Write
AD2, AD1, AD0
Pin States
I2C Definitions
The following terminology is commonly used to describe I2C data transfers. The timing references are defined in
Figure 9.
Bus Idle or Not Busy: Both, SDA and SCL , are in act ive and in the ir logic H IGH states.
START Condition: To initiate communication with a slave, the master has to generate a START condition. A
START condition is defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH.
STOP Condition: To end communication with a slave, the master has to generate a STOP condition. A STOP
condition is defined as a change in state of SDA from LOW to HIGH while SCL remains HIGH.
Repeated START Condition: Repeated starts are commonly used for read accesses to select a specific data
source or address to read from. The master can use a repeated START condition at the end of a data transfer to
immediately initiate a new data transfer following the current one. A repeated START condition is generated the
same way as a normal START condition, but without leaving the bus idle after a STOP condition.
Data Valid: W ith the exception of the START and STOP condition, transitions of SDA may occur only during the
LOW state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus
the required setup a nd ho ld time (tHD:DAT after the f all in g ed ge of SC L a nd t SU:DAT befor e the ris in g edg e of SC L, s ee
Figure 9) . T her e is one c lock puls e p er b it of data. D at a is shifted in to the r ec eiv in g d ev ice dur i ng the ris i ng e dge of
the SCL.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum
tSU:DAT + tR in Figure 9) before the next rising edge of SCL to start reading. The slave shifts out each data bit on
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
Acknowledge: Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the
receipt of eac h b yte. The master must generate a c l oc k puls e that is as s oc iat ed w ith th is ac knowledge b it. A devic e
that ack nowledges m ust pull SDA LOW dur ing the ackno wledge c lock pulse in su ch a wa y that SDA is s table LOW
during t he HIGH period of the acknowledg e-related clock pulse plus the required setup and hold t ime (tHD:DAT after
the falling edge of SCL and tSU:DAT before the rising edge of SCL).
Not Acknowledged by Slave: A slave device may be unable to receive or transmit data, e.g., because it is busy
perform ing some real-tim e f unction. In this cas e the slave device will not ack nowledge its slave a ddress and leave
the SDA line HIGH.
A slave dev ice that is r eady to comm unicate will ac kno wledge at least its slave addres s. However , som e time later
the slave may refuse to accept data, e.g., because of an invalid command code or parameter. In this case the slave
device w ill not ack nowledge an y of the b ytes that it re fuses and wil l leave SDA HIGH. In either case, af ter a slave
has failed to acknowledge, the master first needs to generate a repeated START condition or a STOP condition
followed by a START condition to begin a new data transfer.
DS2482-800: 8-Channel 1-Wire Master
17 of 23
Not Acknowledged by Master: At some time when receiving data, the master must signal an end of data to the
slave devic e. To ac hieve th is, the m as ter does not ac kno wledge th e last b yte that it has recei ved f rom the s lave. In
response, the slave releases SDA, allowing the master to generate the STOP condition.
Figure 9. I2C Timing Diagram
SCL
SDA
STOP
START
t
BUF
t
HD:STA
t
LOW
t
R
t
HD:DAT
t
HIGH
t
SU:DAT
Repeated
START
t
SU:STA
t
F
t
HD:STA
t
SP
t
SU:STO
Spike
Suppression
NOTE: Timing is referenced to VILMAX and VIHMIN.
Writing to the DS2482
To write to the DS2 482, the master m ust ac c ess the d ev ice i n writ e mode, i.e., th e s la ve addr es s must be s ent with
the directi on bit s et to 0 . T he next b yte to be s ent is a comm and code, which, depend ing on t he com m and, ma y be
followed by a command parameter. The DS2482 will acknowledge valid command codes and expected/valid
command parameters. Additional bytes or invalid command parameters will never be acknowledged.
Reading from the DS2482
To read f rom the DS2 482, the m aster mus t access the dev ice in read m ode, i. e., th e slave addr ess must be sent
with the direction bit set to 1. The read pointer determines the register that the master will read from. The master
may continue reading the same register over and over again, without having to re-address the device, e. g., to
watch the 1W B c hanging from 1 to 0. To read f rom a diff erent regis ter, the m aster m ust iss ue the Set Read Point er
command and then access the DS2482 again in read mode.
I2C Communication—Legend
SYMBOL DESCRIPTION SYMBOL DESCRIPTION
S S TART Condition DRST Command "Device Reset", F0h
AD,0 Select DS2482 for Write Access WCFG Command "Write Configuration", D2h
AD,1 Select DS2482 for Read Access CHSL Command "Channel Select", C3h
Sr Repeated START Condition SRP Command "Set Read Pointer", E1h
P S TOP Condition 1WRS Command "1-Wire Reset", B4h
A Acknowledged 1WWB Command "1-Wire Write Byte", A5h
A\ Not Acknowledged 1WRB Command "1-Wire Read Byte", 96h
(Idle) Bus Not Busy 1WSB Command "1-Wire Single Bit", 87h
<byte> Transfer of 1 Byte 1WT Command "1-Wire Triplet", 78h
DS2482-800: 8-Channel 1-Wire Master
18 of 23
Data Direc tion Codes
Master-to-Slave Slave-to-Master
I2C Communication Exampl es
Device Reset, e.g., after power-up
S AD,0 A DRST A Sr AD,1 A <byte>
A\ P
This example includes an optional read access to verify the success of the command.
Write Configu ration, e.g., before starting 1-Wire activity power-up
Case A: 1-Wire idle (1WB = 0)
S AD,0 A WCFG
A <byte>
A Sr AD,1 A <byte>
A\ P
This example includes an optional read access to verify the success of the command.
Case B: 1-Wire busy (1WB = 1)
S AD,0 A WCFG
A\ P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
Channel Select, e.g., to select another 1-Wire channel
Case A: 1-Wire idle (1WB = 0)
S AD,0 A CHSL A E1h A Sr AD,1 A <byte>
A\ P
E1h is the valid channel selection code for IO1. This example includes an optional read access to verify the
success of t he command.
Case B: 1-Wire idle (1WB = 0), invalid channel selection code
S AD,0 A CHSL A E5h A\ P
E5h is an invalid channel selection code.
Case C: 1-Wire busy (1WB = 1)
S AD,0 A CHSL A\ P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
Set Read P o inter, e.g., to rea d from another regis ter
Case A: valid read pointer code
S AD,0 A SRP A C3h A P
C3h is the valid read pointer code for the configuration register.
Case B: invalid read pointer code
S AD,0 A SRP A E5h A\ P
E5h is an invalid read pointer code.
DS2482-800: 8-Channel 1-Wire Master
19 of 23
1-Wire Reset, e.g., to begin or end 1-Wire communication
Case A: 1-Wire idle (1WB = 0), no busy polling to read the result
S AD,0 A 1WRS A P (Idle) S AD,1 A <byte>
A\ P
In the first cycle, the master sends the command; then the master waits (Idle) for the 1-Wire Reset to complete. In
the second cycle the DS2482 is accessed to read the result of the 1-Wire Reset from the Status Register.
Case B: 1-Wire idle (1WB = 0), busy polling until the 1-Wi re Command is completed, then read the result
S AD,0 A 1WRS A Sr AD,1 A <byte>
A <byte>
A\ P
Case C: 1-Wire busy (1WB = 1)
S AD,0 A 1WRS A\ P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
1-Wire Write B yte, e.g., to send a command code to a 1-Wire IO chann el
Case A: 1-Wire idle (1WB = 0), no busy polling
S AD,0 A 1WWB
A 33h A P (Idle)
33h is the valid 1-Wire ROM function command for Read ROM. The idle time is needed for the 1-Wire function to
complete. There is no data read back from the 1-Wire line with this command.
Case B: 1-Wire idle (1WB = 0), busy polling until the 1-Wi re Command is completed.
S AD,0 A 1WWB
A 33h A
Sr AD,1 A <byte>
A <byte>
A\ P
When 1WB has changed from 1 to 0, the 1-Wire Write Byte command is completed.
Case C: 1-Wire busy (1WB = 1)
S AD,0 A 1WWB
A\ P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
1-Wire Read Byte, e. g., to read a byte from a 1-Wire IO channel
Case A: 1-Wire idle (1WB = 0), no busy polling, set read pointer after idle time.
S AD,0 A 1WRB A P (Idle)
S AD,0 A SRP A E1h A Sr AD,1 A <byte>
A\ P
The idle time is needed for the 1-Wire function to complete. Then set the read pointer to the read data register
(code E1h) and access the device again to read the data byte that was obtained from the 1-Wire IO channel.
Case B: 1-Wire idle (1WB = 0), no busy polling, set read pointer before idle time.
S AD,0 A 1WRB A Sr AD,0 A SRP A E1h A P
(Idle) S AD,1 A <byte>
A\ P
The read pointer is set to the read data register (code E1h) while the 1-Wire Read Byte command is still in
progress. Then, after the 1-Wire function is completed, the device is accessed to read the data byte that was
obtained from the 1-Wire IO channel.
Repeat until the 1WB bit has changed to 0
Repeat until the 1WB
bit has changed to 0
DS2482-800: 8-Channel 1-Wire Master
20 of 23
Case C: 1-Wire idle (1WB = 0), busy polling until the 1-Wire Command is completed.
S AD,0 A 1WRB A
Sr AD,1 A <byte>
A <byte>
A\
Sr AD,0 A SRP A E1h A Sr AD,1 A <byte>
A\ P
Poll the Status Register until the 1WB bit has changed from 1 to 0. Then set the read pointer to the read data
register (code E1h) and access the device again to read the data byte that was obtained from the 1-Wire IO
channel.
Case D: 1-Wire busy (1WB = 1)
S AD,0 A 1WRB A\ P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
1-Wire Single Bit, e. g., to generate a single time slot on a 1-Wire IO channel
Case A: 1-Wire idle (1WB = 0), no busy polling
S AD,0 A 1WSB A <byte>
A P (Idle)
S AD,1 A <byte>
A\ P
The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result
from the 1-Wire single-bit command.
Case B: 1-Wire idle (1WB = 0), busy polling until the 1-Wi re Command is completed.
S AD,0 A 1WSB A <byte>
A
Sr AD,1 A <byte>
A <byte>
A\ P
When 1WB has changed from 1 to 0, the Status Register holds the valid result of the 1-Wire Single Bit command.
Case C: 1-Wire busy (1WB = 1)
S AD,0 A 1WSB A\ P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
1-Wire Triple t, e.g., to perform a Search ROM function on a 1-Wire IO channel
Case A: 1-Wire idle (1WB = 0), no busy polling
S AD,0 A 1WT A <byte>
A P (Idle)
S AD,1 A <byte>
A\ P
The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result
from the 1-Wire Triplet command.
Case B: 1-Wire idle (1WB = 0), busy polling until the 1-Wi re Command is completed.
S AD,0 A 1WT A <byte>
A
Sr AD,1 A <byte>
A <byte>
A\ P
When 1WB has changed from 1 to 0, the Status Register holds the valid result of the 1-Wire Triplet command.
Repeat until the 1WB
bit has changed to 0
Repeat until the 1WB
bit has changed to 0
Repeat until the 1WB
bit has changed to 0
DS2482-800: 8-Channel 1-Wire Master
21 of 23
Case C: 1-Wire busy (1WB = 1)
S AD,0 A 1WT A\ P
The master should stop and restart as soon as the DS2482 does not acknowledge the command code.
Figure 10. Application Schematic
Applic ation Information
SDA and SCL Pullup Resistors
SDA is an open-dra in out put o n the D S2 482 th at requ ires a pu llup res istor to rea li ze high l ogic l evels. Beca us e the
DS2482 uses SCL only as input (no clock stretching) the master can drive SCL either through an open-
drain/collector output with a pullup resistor or a push-pull output.
Pullup Resistor RP Sizing
According to the I2C specification, a slave device must be able to sink at least 3mA at a VOL of 0.4V. This DC
condition determines the minimum value of the pullup resistor: Rpmin = (VCC - 0.4V)/3mA. With an operating
voltage of 5.5 V, th e minim um value f or the p ul lup resistor is 1.7kΩ. T he "Mi nimum RP" line in F igure 11 show s ho w
the minimum pullup resistor changes with the operating voltage.
For I2C systems, the rise time and fall time are measured from 30% to 70% of the pullup voltage. The maximum
bus capacitance CB is 400pF. The maximum rise time at standard speed must not exceed 1000ns and 300ns at
fast speed. Assuming maximum rise time, the maximum resistor value at any given capacitance Cb is calculated
as: Rpmaxs = 1000ns/(CB*ln(7/3)) (standard speed) and Rpmaxf = 300ns/(CB*ln(7/3)) (fast speed). For a bus
capacitance of 400pF the maximum pullup resistor values are 2.95kΩ at standard speed and 885Ω at fast speed. A
value between of 1.7k
Ω
and 2.95k
Ω
meets all requirements at standard speed.
Since a 885Ω pullup res istor , as would b e requir ed t o m eet the r ise tim e s pecific ation at f ast speed and 4 00pF bus
capacita nce, is l o wer t han Rpmin at 5.5V, a dif f er ent a ppr oach is n ec ess ary. The "Max. Loa d…" line in F igur e 11 is
generated by first calculating the minimum pullup resistor at any given operating voltage ("Minimum Rp" line) and
then calculating the respective bus capacitance that yields a rise time of 300ns.
DS2482-800: 8-Channel 1-Wire Master
22 of 23
Only for pullup v oltages of 3V an d lower can the m ax im um permissible bus c apac itance of 400pF be m aintaine d. A
reduced bus capacitance of 300pF is acceptable for pullup voltages of 4V and lower. For fast speed operation at
any pullup voltage, the bus capacitance must not exceed 200pF. The corresponding pullup resistor value at the
voltage is indicated by the "Minimum Rp" line.
Figure 11. I2C F ast Mode Pullup Resistor Selection Chart
0
400
800
1200
1600
2000
12345
Pul l -up Volta ge
Mi ni m um Rp (Ohms)
0
100
200
300
400
500
Load (pF)
" M i ni m um Rp" M ax. Load at M i n. Rp fast m ode
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note
that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
16 SO (150 mils) S16+5 21-0041 90-0097
DS2482-800: 8-Channel 1-Wire Master
For pr icing, de l ivery , and o rder ing infor mation , p lea se co nta ct M ax im Dire ct a t 1-888-629-4642, or v isit M ax im Inte gra ted ’s webs i te at w ww . maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.
© 2014 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. 23
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
6/04
Initial release
—
11/04
EC table changes (PUSRC and tF1)
2
Upper I2C slave address bits changed from 0110b to 0011b
16
8/08
Removed the 1-Wire line termination resistor and references to it from the
Typical Operating Circuit and Figure 11. Deleted I2C trademark note; added
package information section.
1, 21, 22
11/09
Conversion to lead (Pb) free product.
1
Removed the presence pulse masking feature.
1, 3, 4, 5, 6,
7, 9, 10, 11,
12
Revised the recommendation on the use of active pullup.
6
1/12
Updated the So lder ing Inf or mation.
2
Added a note to Strong Pullup (SPU) description.
7
Updated the 1-Wire Reset command description, sections Restriction and
Configuration Bits Affected.
12
Added the Land Pattern column to Pack age Information section.
22
12/14
Updated the Benefits and Features section.
1
