Order this document by MC33171/D
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
P SUFFIX
PLASTIC PACKAGE
CASE 626
11
88
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
P SUFFIX
PLASTIC PACKAGE
CASE 646
14
1
14 1
PIN CONNECTIONS
PIN CONNECTIONS
DUAL
QUAD
7
6
5
(Single, Top View)
(Top View)
Offset Null 1
2
3
4
8
7
6
5
Noninv. Input
VEE
NC
VCC
Output
Offset Null
Inv. Input
V EE
Inputs 1 Inputs 2
Output 2
Output 1 VCC
1
2
3
4
8
+
–
+
––
+
2
1
Inputs 1
Output 1
VCC
Inputs 2
Output 2
Output 4
Inputs 4
VEE
Inputs 3
Output 3
(Top View)
1
2
3
4
5
6
78
9
10
11
12
13
14
4
23
1
–
+–
+
+
–+
–
1
MOTOROLA ANALOG IC DEVICE DATA
Quality bipolar fabrication with innovative design concepts are employed
for the MC33171/72/74 series of monolithic operational amplifiers. These
devices operate at 180 µA per amplifier and offer 1.8 MHz of gain bandwidth
product and 2.1 V/µs slew rate without the use of JFET device technology.
Although this series can be operated from split supplies, it is particularly
suited for single supply operation, since the common mode input voltage
includes ground potential (VEE). With a Darlington input stage, these devices
exhibit high input resistance, low input offset voltage and high gain. The all
NPN output stage, characterized by no deadband crossover distortion and
large output voltage swing, provides high capacitance drive capability,
excellent phase and gain margins, low open loop high frequency output
impedance and symmetrical source/sink AC frequency response.
The MC33171/72/74 are specified over the industrial/ automotive
temperature ranges. The complete series of single, dual and quad
operational amplifiers are available in plastic as well as the surface mount
packages.
•Low Supply Current: 180 µA (Per Amplifier)
•Wide Supply Operating Range: 3.0 V to 44 V or ±1.5 V to ±22 V
•Wide Input Common Mode Range, Including Ground (VEE)
•Wide Bandwidth: 1.8 MHz
•High Slew Rate: 2.1 V/µs
•Low Input Offset Voltage: 2.0 mV
•Large Output Voltage Swing: –14.2 V to +14.2 V (with ±15 V Supplies)
•Large Capacitance Drive Capability: 0 pF to 500 pF
•Low Total Harmonic Distortion: 0.03%
•Excellent Phase Margin: 60°C
•Excellent Gain Margin: 15 dB
•Output Short Circuit Protection
•ESD Diodes Provide Input Protection for Dual and Quad
ORDERING INFORMATION
Op Amp
Function Device Operating
Temperature Range Package
Single MC33171D
MC33171P TA = –40° to +85°C
TA = –40° to +85°CSO–8
Plastic DIP
Dual MC33172D
MC33172P TA = –40° to +85°C
TA = –40° to +85°CSO–8
Plastic DIP
Quad MC33174D
MC33174P TA = –40° to +85°C
TA = –40° to +85°CSO–14
Plastic DIP
Motorola, Inc. 1996 Rev 0
MC33171 MC33172 MC33174
2MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC/VEE ±22 V
Input Differential Voltage Range VIDR (Note 1) V
Input Voltage Range VIR (Note 1) V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Operating Ambient Temperature Range TA–40 to +85 °C
Operating Junction Temperature TJ+150 °C
Storage Temperature Range Tstg –65 to +150 °C
NOTES: 1.Either or both input voltages must not exceed the magnitude of VCC or VEE.
2.Power dissipation must be considered to ensure maximum junction temperature (TJ)
is not exceeded.
Q1 Q3 Q4 Q5 Q6 Q7 VCC
Q2 R1 C1 R2
Q9 Q10
Q8
–
+
Inputs
Q11
Q17
D2 R6 R7 Q18
C2 D3 R8
Output
Q19
Q16Q15
Q14
Q13
Q12
D1
R3 R4
R5
Current
Limit
VEE/Gnd
Offset Null
(MC33171)
Bias
Representative Schematic Diagram
(Each Amplifier)
MC33171 MC33172 MC33174
3
MOTOROLA ANALOG IC DEVICE DATA
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL connected to ground, TA = Tlow to Thigh [Note 3],
unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Input Offset Voltage (VCM = 0 V)
VCC = +15 V, VEE = –15 V, TA = +25°C
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh
VIO —
—
—
2.0
2.5
—
4.5
5.0
6.5
mV
Average Temperature Coefficient of Offset Voltage ∆VIO/∆T — 10 — µV/°C
Input Bias Current (VCM = 0 V)
TA = +25°C
TA = Tlow to Thigh
IIB —
—20
—100
200
nA
Input Offset Current (VCM = 0 V)
TA = +25°C
TA = Tlow to Thigh
IIO —
—5.0
—20
40
nA
Large Signal Voltage Gain (VO = ±10 V< RL = 10 k)
TA = +25°C
TA = Tlow to Thigh
AVOL 50
25 500
——
—
V/mV
Output Voltage Swing
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = Tlow to Thigh
VOH 3.5
13.6
13.3
4.3
14.2
—
—
—
—
V
VCC = +5.0 V, VEE = 0 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = +25°C
VCC = +15 V, VEE = –15 V, RL = 10 k, TA = Tlow to Thigh
VOL —
—
—
0.05
–14.2
—
0.15
–13.6
–13.3
Output Short Circuit (TA = +25°C)
Input Overdrive = 1.0 V, Output to Ground
Source
Sink
ISC
3.0
15 5.0
27 —
—
mA
Input Common Mode Voltage Range
TA = +25°C
TA = Tlow to Thigh
VICR VEE to (VCC –1.8)
VEE to (VCC –2.2)
V
Common Mode Rejection Ratio (RS ≤ 10 k) TA = +25°C CMRR 80 90 — dB
Power Supply Rejection Ratio (RS = 100 Ω) TA = +25°C PSRR 80 100 — dB
Power Supply Current (Per Amplifier)
VCC = +5.0 V, VEE = 0 V, TA = +25°C
VCC = +15 V, VEE = –15 V, TA = +25°C
VCC = +15 V, VEE = –15 V, TA = Tlow to Thigh
ID—
—
—
180
220
—
250
250
300
µA
NOTE: 3. Tlow = –40°CT
high = +85°C
MC33171 MC33172 MC33174
4MOTOROLA ANALOG IC DEVICE DATA
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, RL connected to ground, TA = +25°C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Slew Rate (Vin = –10 V to +10 V, RL = 10 k, CL = 100 pF)
AV +1
AV –1
SR 1.6
—2.1
2.1 —
—
V/µs
Gain Bandwidth Product (f = 100 kHz) GBW 1.4 1.8 — MHz
Power Bandwidth
AV = +1.0 RL = 10 k, VO = 20 Vpp, THD = 5% BWp — 35 — kHz
Phase Margin
RL = 10 k
RL = 10 k, CL = 100 pF
φm—
—60
45 —
—
Degree
s
Gain Margin
RL = 10 k
RL = 10 k, CL = 100 pF
Am—
—15
5.0 —
—
dB
Equivalent Input Noise Voltage
RS = 100 Ω, f = 1.0 kHz en— 32 — nV/ Hz√
Equivalent Input Noise Current (f = 1.0 kHz) In— 0.2 — pA/ Hz√
Differential Input Resistance
Vcm = 0 V Rin —300 — MΩ
Input Capacitance Ci— 0.8 — pF
Total Harmonic Distortion
AV = +10, RL = 10 k, 2.0 Vpp ≤ VO ≤ 20 Vpp, f = 10 kHz THD — 0.03 — %
Channel Separation (f = 10 kHz) CS — 120 — dB
Open Loop Output Impedance (f = 1.0 MHz) zo— 100 — Ω
Figure 1. Input Common Mode Voltage Range
versus Temperature Figure 2. Split Supply Output Saturation
versus Load Current
V , INPUT COMMON MODE VOLTAGE RANGE (V)
ICR
TA, AMBIENT TEMPERATURE (
°
C)
VCC VCC/VEE =
±
1.5 V to
±
22 V
∆
VIO = 5.0 mV
V , OUTPUT SATURATION VOL TAGE (V)
sat
IL, LOAD CURRENT (
±
mA)
Source
Sink
VEE
VCC
VEE
VCC/VEE =
±
5.0 V to
±
22 V
TA = 25
°
C
0
–2.4
0.1
0
–0.8
–1.6
0
–1.0
1.0
0
–55 –25 0 25 50 75 100 125 0 1.0 2.0 3.0 4.0
MC33171 MC33172 MC33174
5
MOTOROLA ANALOG IC DEVICE DATA
1. TA = –55
°
C
2. TA = 25
°
C
3. TA = 125
°
C
Dual
Quad
1
2
3
Single
3
2
1
1
2
3
VCC/VEE =
±
15 V
AV = +1.0
RL = 10 k
CL = 100 pF
TA = 25
°
C
AV = 1000
AV = 100
AV = 10 AV = 1.0
Figure 3. Open Loop Voltage Gain and
Phase versus Frequency Figure 4. Phase Margin and Percent
Overshoot versus Load Capacitance
Figure 5. Normalized Gain Bandwidth Product
and Slew Rate versus Temperature Figure 6. Small and Large Signal
Transient Response
Figure 7. Output Impedance and Frequency Figure 8. Supply Current versus Supply Voltage
0
0
5.0
µ
s/DIV
50 mV/DIV10 V/DIV
5.0
µ
s/DIV
f, FREQUENCY (Hz)
, EXCESS PAHSE (DEGREES)
φ
1
2
34
120
140
160
180
200
220
, OPEN LOOP VOLTAGE GAIN (dB)
VOL
Gain
Margin
= 15 dB
Phase
Margin
= 58
°
VCC/VEE =
±
15 V
RL = 10 k
Vout = 0 V
TA = 25
°
C
1 — Phase
2 — Phase, CL = 100 pF
3 — Gain
4 — Gain, CL = 100 pF
m, PHASE MARGIN (DEGREES)
φ
CL, LOAD CAPACITANCE (pF)
70
60
50
40
30
20
10
%, PERCENT OVERSHOOT
%
φ
m
0
VCC/VEE =
±
15 V
AVOL = +1.0
RL = 10 k
∆
VO = 20 mVpp
TA = 25
°
C
TA, AMBIENT TEMPERATURE (
°
C)
GBW AND SR (NORMALIZED)
GBW
SR
VCC/VEE =
±
15 V
RL = 10 k
f, FREQUENCY (Hz)
z , OUTPUT IMPEDANCE ( )
Ω
o
VCC/VEE, SUPPLY VOLTAGE (
±
V)
D
I , I , POWER SUPPLY CURRENT (mA)
CC
A
3
0
20
10
0
–10
–20
–30
70
60
50
40
30
20
10
0
1.3
1.2
1.1
1.0
0.9
0.8
0.7
140
120
100
80
60
40
20
0
1.1
0.9
0.7
0.5
0.3
0.1
100 k 1.0 M 10 M 10 20 50 100 200 500 1.0 k
–55 –25 0 25 50 75 100 125
200 2.0 k 20 k 200 k 2.0 M 0 5.0 10 15 20 25
VCC/VEE =
±
15 V
VCM = 0 V
VO = 0 V
∆
IO =
±
0.5 mA
TA = 25
°
C
MC33171 MC33172 MC33174
6MOTOROLA ANALOG IC DEVICE DATA
APPLICATIONS INFORMATION – CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
MC33171/72/74 amplifier family is similar to low power op
amp products utilizing JFET input devices, these amplifiers
offer additional advantages as a result of the PNP transistor
differential inputs and an all NPN transistor output stage.
Because the input common mode voltage range of this
input stage includes the VEE potential, single supply
operation is feasible to as low as 3.0 V with the common
mode input voltage at ground potential.
The input stage also allows differential input voltages up to
±44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
between VCC and VEE supply voltages as shown by the
maximum rating table. In practice, although
not
recommended,
the input voltages can exceed the VCC
voltage by approximately 3.0 V and decrease below the VEE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur . It is also possible to source
up to 5.0 mA of current from VEE through either inputs’
clamping diode without damage or latching, but phase
reversal may again occur. If at least one input is within the
common mode input voltage range and the other input is
within the maximum input voltage range, no phase reversal
will occur. If both inputs exceed the upper common mode
input voltage limit, the output will be forced to its lowest
voltage state.
Since the input capacitance associated with the small
geometry input device is substantially lower (0.8 pF) than that
of a typical JFET (3.0 pF), the frequency response for a given
input source resistance is greatly enhanced. This becomes
evident in D–to–A current to voltage conversion applications
where the feedback resistance can form a pole with the input
capacitance of the op amp. This input pole creates a 2nd
Order system with the single pole op amp and is therefore
detrimental to its settling time. In this context, lower input
capacitance is desirable especially for higher values of
feedback resistances (lower current DACs). This input pole
can be compensated for by creating a feedback zero with a
capacitance across the feedback resistance, if necessary, to
reduce overshoot. For 10 kΩ of feedback resistance, the
MC33171/72/74 family can typically settle to within 1/2 LSB
of 8 bits in 4.2 µs, and within 1/2 LSB of 12 bits in 4.8 µs for
a 10 V step. In a standard inverting unity gain fast settling
configuration, the symmetrical slew rate is typically
±2.1 V/µs. In the classic noninverting unity gain
configuration the typical output positive slew rate is also
2.1 V/µs, and the corresponding negative slew rate will
usually exceed the positive slew rate as a function of the fall
time of the input waveform.
The all NPN output stage, shown in its basic form on the
equivalent circuit schematic, offers unique advantages over
the more conventional NPN/PNP transistor Class AB output
stage. A 10 kΩ load resistance can typically swing within 0.8 V
of the positive rail (VCC) and negative rail (VEE), providing a
28.4 Vpp swing from ±15 V supplies. This large output swing
becomes most noticeable at lower supply voltages.
The positive swing is limited by the saturation voltage of
the current source transistor Q7, the VBE of the NPN pull–up
transistor Q17, and the voltage drop associated with the
short circuit resistance, R5. For sink currents less than
0.4 mA, the negative swing is limited by the saturation
voltage of the pull–down transistor Q15, and the voltage drop
across R4 and R5. For small valued sink currents, the above
voltage drops are negligible, allowing the negative swing
voltage to approach within millivolts of VEE. For sink currents
(> 0.4 mA), diode D3 clamps the voltage across R4. Thus the
negative swing is limited by the saturation voltage of Q15,
plus the forward diode drop of D3 (≈VEE +1.0 V). Therefore
an unprecedented peak–to–peak output voltage swing is
possible for a given supply voltage as indicated by the output
swing specifications.
If the load resistance is referenced to VCC instead of
ground for single supply applications, the maximum possible
output swing can be achieved for a given supply voltage. For
light load currents, the load resistance will pull the output to
VCC during the positive swing and the output will pull the load
resistance near ground during the negative swing. The load
resistance value should be much less than that of the
feedback resistance to maximize pull–up capability.
Because the PNP output emitter–follower transistor has
been eliminated, the MC33171/72/74 family offers a 15 mA
minimum current sink capability , typically to an output voltage
of (VEE +1.8 V). In single supply applications the output can
directly source or sink base current from a common emitter
NPN transistor for current switching applications.
In addition, the all NPN transistor output stage is inherently
faster than PNP types, contributing to the bipolar amplifier ’s
improved gain bandwidth product. The associated high
frequency low output impedance (200 Ω typ @ 1.0 MHz)
allows capacitive drive capability from 0 pF to 400 pF without
oscillation in the noninverting unity gain configuration. The
60°C phase margin and 15 dB gain margin, as well as the
general gain and phase characteristics, are virtually
independent of the source/sink output swing conditions. This
allows easier system phase compensation, since output
swing will not be a phase consideration. The AC
characteristics of the MC33171/72/74 family also allow
excellent active filter capability, especially for low voltage
single supply applications.
Although the single supply specification is defined at 5.0 V,
these amplifiers are functional to at least 3.0 V @ 25°C.
However slight changes in parametrics such as bandwidth,
slew rate, and DC gain may occur.
If power to this integrated circuit is applied in reverse
polarity, or if the IC is installed backwards in a socket, large
unlimited current surges will occur through the device that
may result in device destruction.
As usual with most high frequency amplifiers, proper lead
dress, component placement and PC board layout should
be exercised for optimum frequency performance. For
example, long unshielded input or output leads may result in
unwanted input/output coupling. In order to preserve the
relatively low input capacitance associated with these
amplifiers, resistors connected to the inputs should be
immediately adjacent to the input pin to minimize additional
stray input capacitance. This not only minimizes the input
pole for optimum frequency response, but also minimizes
extraneous “pick up” at this node. Supply decoupling with
adequate capacitance immediately adjacent to the supply pin
is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
The output of any one amplifier is current limited and thus
protected from a direct short to ground. However , under such
conditions, it is important not to allow the device to exceed
the maximum junction temperature rating. T ypically for ±15 V
supplies, any one output can be shorted continuously to
ground without exceeding the maximum temperature rating.
MC33171 MC33172 MC33174
7
MOTOROLA ANALOG IC DEVICE DATA
Figure 9. AC Coupled Noninverting Amplifier
with Single +5.0 V Supply Figure 10. AC Coupled Inverting Amplifier
with Single +5.0 V Supply
Figure 11. DC Coupled Inverting Amplifier
Maximum Output Swing with Single
+5.0 V Supply Figure 12. Offset Nulling Circuit
Figure 13. Active High–Q Notch Filter Figure 14. Active Bandpass Filter
2.2 k 510 k VCC
100 k
Cin
Vin
1.0 k
+
–
COVO
3.6 Vpp
AV = 101
BW ( –3.0 dB) = 20 kHz
VO 0
100 k 100 k
VCC
100 k COVO
+
–
10 k
Cin
Vin
AV = 10
BW ( –3.0 dB) = 200 kHz
10 k
100 k
100 k VCC
50 k
RL
4.7 k +
–
100 k 1.0 M
VO
Vin 4.2 Vpp
VO 2.5 V
AV = 10
BW ( –3.0 dB) = 200 kHz
VCC
7
36
25
1
410 k
VEE
+
–
Offset Nulling range is approximately
±
80 mV with
a 10 k potentiometer, MC33171 only.
Vin
–
+VO
0.01
2C
0.02 2R
32 k
fo = 1.0 kHz
fo = 1
4
π
RC
Vin
≥
0.2 Vdc
2C
0.02
16 k16 k
Vin
R1
1.1 k
R2
5.6 k
R3
2.2 k
–
+VO
C
0.047
0.4
VCC
fo = 30 kHz
Q = 10
HO = 1.0
R1 = R3
2 HOR2 =
R3 = Q
π
foC
R1 R3
4Q2R1 –R3
Qo fo
GBW < 0.1
Given fo = center frequency
Ao = Gain at center frequency
Choose Value fo, Q, Ao, C
For less than 10% error for operational amplifier, where fo and GBW are expressed in Hz.
C
0.047
RL
100 kRL
RCR
VCC Then:
3.8 Vpp
VO 0
MC33171 MC33172 MC33174
8MOTOROLA ANALOG IC DEVICE DATA
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE R
OUTLINE DIMENSIONS
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M––– 10 ––– 10
N0.76 1.01 0.030 0.040
__
SEATING
PLANE
14
58
A0.25 MCBSS
0.25 MBM
h
q
C
X 45
_
L
DIM MIN MAX
MILLIMETERS
A1.35 1.75
A1 0.10 0.25
B0.35 0.49
C0.18 0.25
D4.80 5.00
E1.27 BSCe3.80 4.00
H5.80 6.20
h
0 7
L0.40 1.25
q
0.25 0.50
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
EH
A
Be
B
A1
CA
0.10
MC33171 MC33172 MC33174
9
MOTOROLA ANALOG IC DEVICE DATA
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
ISSUE F
OUTLINE DIMENSIONS
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
17
14 8
B
A
F
HG D K
C
N
L
J
M
SEATING
PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 19.56
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L0.300 BSC 7.62 BSC
M0 10 0 10
N0.015 0.039 0.39 1.01
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE
D14 PL K
C
J
M
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
____
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10 MOTOROLA ANALOG IC DEVICE DATA
NOTES
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11
MOTOROLA ANALOG IC DEVICE DATA
NOTES
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12 MOTOROLA ANALOG IC DEVICE DATA
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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MC33171/D
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