Features
•High-performance, Low-power 8/16-bit Atmel® AVR® XMEGATM Microcontroller
•Non-volatile Program and Data Memories
– 64 KB - 256 KB of In-System Self-Programmable Flash
– 4 KB - 8 KB Boot Code Section with Independent Lock Bits
– 2 KB - 4 KB EEPROM
– 4 KB - 16 KB Internal SRAM
•Peripheral Features
– Four-channel DMA Controller with support for external requests
– Eight-channel Event System
– Seven 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Capture channels
Three Timer/Counters with 2 Output Compare or Input Capture channels
High Resolution Extensions on all Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– Seven USARTs
IrDA Extension on 1 USART
– AES and DES Crypto Engine
– Two Two-wire Interfaces with dual address match (I2C and SMBus compatible)
– Three SPI (Serial Peripheral Interfaces)
– 16-bit Real Time Counter with Separate Oscillator
– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters
– One Two-channel, 12-bit, 1 Msps Digital to Analog Converter
– Four Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
•Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interfaces
JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming
PDI (Program and Debug Interface) for programming, test and debugging
•I/O and Packages
– 50 Programmable I/O Lines
– 64-lead TQFP
– 64-pad QFN
•Operating Voltage
– 1.6 – 3.6V
•Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
Typical Applications
•Industrial control •Climate control •Hand-held battery applications
•Factory automation •ZigBee •Power tools
•Building control •Motor control •HVAC
•Board control •Networking •Metering
•White Goods •Optical •Medical Applications
8/16-bit
XMEGA A3
Microcontroller
ATxmega256A3
ATxmega192A3
ATxmega128A3
ATxmega64A3
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XMEGA A3
1. Ordering Information
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. For packaging information, see ”Packaging information” on page 61.
Ordering Code Flash E2SRAM Speed (MHz) Power Supply Package(1)(2)(3) Temp
ATxmega256A3-AU 256 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V
64A
-40°C - 85°C
ATxmega192A3-AU 192 KB + 8 KB 2 KB 16 KB 32 1.6 - 3.6V
ATxmega128A3-AU 128 KB + 8 KB 2 KB 8 KB 32 1.6 - 3.6V
ATxmega64A3-AU 64 KB + 4 KB 2 KB 4 KB 32 1.6 - 3.6V
ATxmega256A3-MH 256 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V
64M2
ATxmega192A3-MH 192 KB + 8 KB 2 KB 16 KB 32 1.6 - 3.6V
ATxmega128A3-MH 128 KB + 8 KB 2 KB 8 KB 32 1.6 - 3.6V
ATxmega64A3-MH 64 KB + 4 KB 2 KB 4 KB 32 1.6 - 3.6V
Package Type
64A 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64M2 64-Pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 7.65 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
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XMEGA A3
2. Pinout/Block Diagram
Figure 2-1. Block diagram and pinout.
Notes: 1. For full details on pinout and alternate pin functions refer to ”Pinout and Pin Functions” on page 49.
2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good
mechanical stability.
INDEX CORNER
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PF2
PF1
PF0
VCC
GND
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
VCC
GND
PD7
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
GND
VCC
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PA2
PA1
PA0
AVCC
GND
PR1
PR0
RESET/PDI
PDI
PF7
PF6
VCC
GND
PF5
PF4
PF3
FLASH
RAM
E
2
PROM
DMA
Interrupt Controller
OCD
ADC A
ADC B
DAC B
AC A0
AC A1
AC B0
AC B1
Port A
Port B
Event System ctrl
Port R
Power
Control
Reset
Control
Watchdog
OSC/CLK
Control BOD POR
RTC
EVENT ROUTING NETWORK
DATA BU S
DATA BU S
VREF
TEMP
Port C Port D Port E Port F
CPU
T/C0:1
USART0:1
SPI
TWI
T/C0:1
USART0:1
SPI
T/C0:1
USART0:1
SPI
TWI
T/C0
USART0
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XMEGA A3
3. Overview
The Atmel® AVR® XMEGA™ A3 is a family of low power, high performance and peripheral rich
CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching
1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize
power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conven-
tional single-accumulator or CISC based microcontrollers.
The XMEGA A3 devices provide the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,
eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose
I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare
modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Periph-
eral Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional
differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators
with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate
internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this
can also be used for On-chip Debug and programming.
The XMEGA A3 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and
all peripherals to continue functioning. The Power-down mode saves the SRAM and register
contents but stops the oscillators, disabling all other functions until the next TWI or pin-change
interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is
sleeping. This allows very fast start-up from external crystal combined with low power consump-
tion. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run. To further reduce power consumption, the peripheral clock for each individual peripheral
can optionally be stopped in Active mode and Idle sleep mode.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The pro-
gram Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader
running in the device can use any interface to download the application program to the Flash
memory. The Bootloader software in the Boot Flash section will continue to run while the Appli-
cation Flash section is updated, providing true Read-While-Write operation. By combining an
8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3 is a power-
ful microcontroller family that provides a highly flexible and cost effective solution for many
embedded applications.
The XMEGA A3 devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, programmers,
and evaluation kits.
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XMEGA A3
3.1 Block Diagram
Figure 3-1. XMEGA A3 Block Diagram
PE[0..7]
PORT E (8)
TCE0:1
USARTE0:1
TWIE
SPIE
TCF0
USARTF0
PORT F (8)
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (8)
DMA
Controller
BUS
Controller
SRAM
ADCA
ACA
DACB
ADCB
ACB
OCD
PDI
CPU
PA[0..7]
PB[0..7]/
JTAG
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event System
Controller
JTAG
PDI_DATA
RESET/
PDI_CLK
PORT B
Sleep
Controller
Flash EEPROM
NVM Controller
DES
AES
IRCOM
PORT C (8)
PC[0..7]
TCC0:1
USARTC0:1
TWIC
SPIC
PD[0..7]
PORT R (2)
XTAL1
XTAL2
PR[0..1]
PORT D (8)
TCD0:1
USARTD0:1
SPID
TOSC1
TOSC2
EVENT ROUTING NETWORK
PF[0..7]
To Clock
Generator
Int. Ref.
AREFA
AREFB
Tempref
VCC/10
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XMEGA A3
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4.1 Recommended reading
• XMEGA Manual
• XMEGA Application Notes
This device data sheet only contains part specific information and a short description of each
peripheral and module. The XMEGA Manual describes the modules and peripherals in depth.
The XMEGA application notes contain example code and show applied use of the modules and
peripherals.
The XMEGA Manual and Application Notes are available from http://www.atmel.com/avr.
5. Disclaimer
For devices that are not available yet, typical values contained in this datasheet are based on
simulations and characterization of other AVR XMEGA microcontrollers manufactured on the
same process technology. Min. and Max values will be available after the device is
characterized.
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XMEGA A3
6. AVR CPU
6.1 Features
•8/16-bit high performance AVR RISC Architecture
– 138 instructions
– Hardware multiplier
•32x8-bit registers directly connected to the ALU
•Stack in RAM
•Stack Pointer accessible in I/O memory space
•Direct addressing of up to 16M bytes of program and data memory
•True 16/24-bit access to 16/24-bit I/O registers
•Support for 8-, 16- and 32-bit Arithmetic
•Configuration Change Protection of system critical features
6.2 Overview
The XMEGA A3 uses an 8/16-bit AVR CPU. The main function of the AVR CPU is to ensure cor-
rect program execution. The CPU must therefore be able to access memories, perform
calculations and control peripherals. Interrupt handling is described in a separate section. Figure
6-1 on page 7 shows the CPU block diagram.
Figure 6-1. CPU block diagram
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
Flash
Program
Memory
Instruction
Decode
Program
Counter
OCD
32 x 8 General
Purpose
Registers
ALU Multiplier/
DES
Instruction
Register
STATUS/
CONTROL
Peripheral
Module 1 Peripheral
Module 2 EEPROM PMICSRAM
DATA BUS
DATA BUS
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XMEGA A3
This concept enables instructions to be executed in every clock cycle. The program memory is
In-System Re-programmable Flash memory.
6.3 Register File
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File - in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing - enabling efficient address calculations. One of these address pointers can
also be used as an address pointer for look up tables in Flash program memory.
6.4 ALU - Arithmetic Logic Unit
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations
between registers or between a constant and a register. Single register operations can also be
executed. Within a single clock cycle, arithmetic operations between general purpose registers
or between a register and an immediate are executed. After an arithmetic or logic operation, the
Status Register is updated to reflect information about the result of the operation.
The ALU operations are divided into three main categories – arithmetic, logical, and bit-func-
tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy
implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both
signed and unsigned multiplication and fractional format.
6.5 Program Flow
When the device is powered on, the CPU starts to execute instructions from the lowest address
in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to
be fetched. After a reset, the PC is set to location ‘0’.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number uses a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited
by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to
the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory
space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can
easily be accessed through the five different addressing modes supported in the AVR CPU.
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XMEGA A3
7. Memories
7.1 Features
•Flash Program Memory
– One linear address space
– In-System Programmable
– Self-Programming and Bootloader support
– Application Section for application code
– Application Table Section for application code or data storage
– Boot Section for application code or bootloader code
– Separate lock bits and protection for all sections
– Built in fast CRC check of a selectable flash program memory section
•Data Memory
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
– I/O Memory
Configuration and Status registers for all peripherals and modules
16 bit-accessible General Purpose Register for global variables or flags
– Bus arbitration
Safe and deterministic handling of CPU and DMA Controller priority
– Separate buses for SRAM, EEPROM, I/O Memory and External Memory access
Simultaneous bus access for CPU and DMA Controller
•Production Signature Row Memory for factory programmed data
Device ID for each microcontroller device type
Serial number for each device
Oscillator calibration bytes
ADC, DAC and temperature sensor calibration data
•User Signature Row
One flash page in size
Can be read and written from software
Content is kept after chip erase
7.2 Overview
The AVR architecture has two main memory spaces, the Program Memory and the Data Mem-
ory. In addition, the XMEGA A3 features an EEPROM Memory for non-volatile data storage. All
three memory spaces are linear and require no paging. The available memory size configura-
tions are shown in ”Ordering Information” on page 2. In addition each device has a Flash
memory signature row for calibration data, device identification, serial number etc.
Non-volatile memory spaces can be locked for further write or read/write operations. This pre-
vents unrestricted access to the application software.
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XMEGA A3
7.3 In-System Programmable Flash Program Memory
The XMEGA A3 devices contains On-chip In-System Programmable Flash memory for program
storage, see Figure 7-1 on page 10. Since all AVR instructions are 16- or 32-bits wide, each
Flash address location is 16 bits.
The Program Flash memory space is divided into Application and Boot sections. Both sections
have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Pro-
gram Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash
memory.
A third section inside the Application section is referred to as the Application Table section which
has separate Lock bits for storage of write or read/write protection. The Application Table sec-
tion can be used for storing non-volatile data or application software.
The Application Table Section and Boot Section can also be used for general application
software.
Figure 7-1. Flash Program Memory (Hexadecimal address)
Word Address
0Application Section
(256 KB/192 KB/128 KB/64 KB)
...
1EFFF / 16FFF / EFFF / 77FF
1F000 / 17000 / F000 / 7800 Application Table Section
(8 KB/8 KB/8 KB/4 KB)
1FFFF / 17FFF / FFFF / 7FFF
20000 / 18000 / 10000 / 8000 Boot Section
(8 KB/8 KB/8 KB/4 KB)
20FFF / 18FFF / 10FFF / 87FF
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XMEGA A3
7.4 Data Memory
The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one lin-
ear address space, see Figure 7-2 on page 11. To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2. Data Memory Map (Hexadecimal address)
Byte Address ATxmega192A3 Byte Address ATxmega128A3 Byte Address ATxmega64A3
0I/O Registers
(4 KB)
0I/O Registers
(4 KB)
0I/O Registers
(4 KB)
FFF FFF FFF
1000 EEPROM
(2 KB)
1000 EEPROM
(2 KB)
1000 EEPROM
(2 KB)
17FF 17FF 17FF
RESERVED RESERVED RESERVED
2000 Internal SRAM
(16 KB)
2000 Internal SRAM
(8 KB)
2000 Internal SRAM
(4 KB)
5FFF 3FFF 2FFF
Byte Address ATxmega256A3
0I/O Registers
(4 KB)
FFF
1000
EEPROM
(4 KB)
1FFF
2000 Internal SRAM
(16 KB)
5FFF
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XMEGA A3
7.4.1 I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A3 is shown in the ”Periph-
eral Module Address Map” on page 56.
7.4.2 SRAM Data Memory
The XMEGA A3 devices have internal SRAM memory for data storage.
7.4.3 EEPROM Data Memory
The XMEGA A3 devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
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XMEGA A3
7.5 Production Signature Row
The Production Signature Row is a separate memory section for factory programmed data. It
contains calibration data for functions such as oscillators and analog modules.
The production signature row also contains a device ID that identify each microcontroller device
type, and a serial number that is unique for each manufactured device. The device ID for the
available XMEGA A3 devices is shown in Table 7-1 on page 13. The serial number consist of
the production LOT number, wafer number, and wafer coordinates for the device.
The production signature row can not be written or erased, but it can be read from both applica-
tion software and external programming.
Table 7-1. Device ID bytes for XMEGA A3 devices.
7.6 User Signature Row
The User Signature Row is a separate memory section that is fully accessible (read and write)
from application software and external programming. The user signature row is one flash page
in size, and is meant for static user parameter storage, such as calibration data, custom serial
numbers or identification numbers, random number seeds etc. This section is not erased by
Chip Erase commands that erase the Flash, and requires a dedicated erase command. This
ensures parameter storage during multiple program/erase session and on-chip debug sessions.
Device Device ID bytes
Byte 2 Byte 1 Byte 0
ATxmega64A3 42 96 1E
ATxmega128A3 42 97 1E
ATxmega192A3 44 97 1E
ATxmega256A3 42 98 1E
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XMEGA A3
7.7 Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in
the address (FPAGE) gives the page number and the least significant address bits (FWORD)
gives the word in the page.
Table 7-2. Number of words and Pages in the Flash.
Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA A3 devices.
EEEPROM write and erase operations can be performed one page or one byte at a time, while
reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Regis-
ter (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) gives
the page number and the least significant address bits (E2BYTE) gives the byte in the page.
Table 7-3. Number of bytes and Pages in the EEPROM.
Devices Flash Page Size FWORD FPAGE Application Boot
Size (words) Size No of Pages Size No of Pages
ATxmega64A3 64 KB + 4 KB 128 Z[7:1] Z[16:8] 64K 256 4 KB 16
ATxmega128A3 128 KB + 8 KB 256 Z[8:1] Z[17:9] 128K 256 8 KB 16
ATxmega192A3 192 KB + 8 KB 256 Z[8:1] Z[18:9] 192K 384 8 KB 16
ATxmega256A3 256 KB + 8 KB 256 Z[8:1] Z[18:9] 256K 512 8 KB 16
Devices EEPROM Page Size E2BYTE E2PAGE No of Pages
Size (Bytes)
ATxmega64A3 2 KB 32 ADDR[4:0] ADDR[10:5] 64
ATxmega128A3 2 KB 32 ADDR[4:0] ADDR[10:5] 64
ATxmega192A3 2 KB 32 ADDR[4:0] ADDR[10:5] 64
ATxmega256A3 4 KB 32 ADDR[4:0] ADDR[11:5] 128
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XMEGA A3
8. DMAC - Direct Memory Access Controller
8.1 Features
•Allows High-speed data transfer
– From memory to peripheral
– From memory to memory
– From peripheral to memory
– From peripheral to peripheral
•4 Channels
•From 1 byte and up to 16 M bytes transfers in a single transaction
•Multiple addressing modes for source and destination address
–Increment
– Decrement
– Static
•1, 2, 4, or 8 bytes Burst Transfers
•Programmable priority between channels
8.2 Overview
The XMEGA A3 has a Direct Memory Access (DMA) Controller to move data between memories
and peripherals in the data space. The DMA controller uses the same data bus as the CPU to
transfer data.
It has 4 channels that can be configured independently. Each DMA channel can perform data
transfers in blocks of configurable size from 1 to 64K bytes. A repeat counter can be used to
repeat each block transfer for single transactions up to 16M bytes. Each DMA channel can be
configured to access the source and destination memory address with incrementing, decrement-
ing or static addressing. The addressing is independent for source and destination address.
When the transaction is complete the original source and destination address can automatically
be reloaded to be ready for the next transaction.
The DMAC can access all the peripherals through their I/O memory registers, and the DMA may
be used for automatic transfer of data to/from communication modules, as well as automatic
data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or
from port pins. A wide range of transfer triggers is available from the peripherals, Event System
and software. Each DMA channel has different transfer triggers.
To allow for continuous transfers, two channels can be interlinked so that the second takes over
the transfer when the first is finished and vice versa.
The DMA controller can read from memory mapped EEPROM, but it cannot write to the
EEPROM or access the Flash.
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XMEGA A3
9. Event System
9.1 Features
•Inter-peripheral communication and signalling with minimum latency
•CPU and DMA independent operation
•8 Event Channels allows for up to 8 signals to be routed at the same time
•Events can be generated by
– Timer/Counters (TCxn)
– Real Time Counter (RTC)
– Analog to Digital Converters (ADCx)
– Analog Comparators (ACx)
– Ports (PORTx)
– System Clock (ClkSYS)
– Software (CPU)
•Events can be used by
– Timer/Counters (TCxn)
– Analog to Digital Converters (ADCx)
– Digital to Analog Converters (DACx)
– Ports (PORTx)
– DMA Controller (DMAC)
– IR Communication Module (IRCOM)
•The same event can be used by multiple peripherals for synchronized timing
•Advanced Features
– Manual Event Generation from software (CPU)
– Quadrature Decoding
– Digital Filtering
•Functions in Active and Idle mode
9.2 Overview
The Event System is a set of features for inter-peripheral communication. It enables the possibil-
ity for a change of state in one peripheral to automatically trigger actions in one or more
peripherals. What changes in a peripheral that will trigger actions in other peripherals are config-
urable by software. It is a simple, but powerful system as it allows for autonomous control of
peripherals without any use of interrupts, CPU or DMA resources.
The indication of a change in a peripheral is referred to as an event, and is usually the same as
the interrupt conditions for that peripheral. Events are passed between peripherals using a dedi-
cated routing network called the Event Routing Network. Figure 9-1 on page 17 shows a basic
block diagram of the Event System with the Event Routing Network and the peripherals to which
it is connected. This highly flexible system can be used for simple routing of signals, pin func-
tions or for sequencing of events.
The maximum latency is two CPU clock cycles from when an event is generated in one periph-
eral, until the actions are triggered in one or more other peripherals.
The Event System is functional in both Active and Idle modes.
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Figure 9-1. Event system block diagram.
The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators
(ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Com-
munication Module (IRCOM). Events can also be generated from software (CPU).
All events from all peripherals are always routed into the Event Routing Network. This consist of
eight multiplexers where each can be configured in software to select which event to be routed
into that event channel. All eight event channels are connected to the peripherals that can use
events, and each of these peripherals can be configured to use events from one or more event
channels to automatically trigger a software selectable action.
ADCx
DACx
Event Routing
Network
PORTx CPU
ACx
RTC
T/Cxn DMACIRCOM
ClkSYS
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10. System Clock and Clock options
10.1 Features
•Fast start-up time
•Safe run-time clock switching
•Internal Oscillators:
– 32 MHz run-time calibrated RC oscillator
– 2 MHz run-time calibrated RC oscillator
– 32.768 kHz calibrated RC oscillator
– 32 kHz Ultra Low Power (ULP) oscillator
•External clock options
– 0.4 - 16 MHz Crystal Oscillator
– 32.768 kHz Crystal Oscillator
– External clock
•PLL with internal and external clock options with 2 to 31x multiplication
•Clock Prescalers with 2 to 2048x division
•Fast peripheral clock running at 2 and 4 times the CPU clock speed
•Automatic Run-Time Calibration of internal oscillators
•Crystal Oscillator failure detection
10.2 Overview
XMEGA A3 has an advanced clock system, supporting a large number of clock sources. It incor-
porates both integrated oscillators, external crystal oscillators and resonators. A high frequency
Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a
wide range of clock frequencies from the clock source input.
It is possible to switch between clock sources from software during run-time. After reset the
device will always start up running from the 2 Mhz internal oscillator.
A calibration feature is available, and can be used for automatic run-time calibration of the inter-
nal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature.
A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and
switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 19 shows the prin-
cipal clock system in XMEGA A3.
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Figure 10-1. Clock system overview
Each clock source is briefly described in the following sub-sections.
10.3 Clock Options
10.3.1 32 kHz Ultra Low Power Internal Oscillator
The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock
source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock
source for the Real Time Counter. This oscillator cannot be used as the system clock source,
and it cannot be directly controlled from software.
10.3.2 32.768 kHz Calibrated Internal Oscillator
The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used
as the system clock source or as an asynchronous clock source for the Real Time Counter. It is
calibrated during production to provide a default frequency which is close to its nominal
frequency.
32 MHz
Run-time Calibrated
Internal Oscillator
32 kHz ULP
Internal Oscillator
32.768 kHz
Calibrated Internal
Oscillator
32.768 KHz
Crystal Oscillator
0.4 - 16 MHz
Crystal Oscillator
2 MHz
Run-Time Calibrated
Internal Oscillator
External
Clock Input
CLOCK CONTROL
UNIT
with PLL and
Prescaler
WDT/BOD
clkULP
RTC
clkRTC
EVSYS
PERIPHERALS
ADC
DAC
PORTS
...
clkPER
DMA
INTERRUPT
RAM
NVM MEMORY
FLASH
EEPROM
CPU
clkCPU
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10.3.3 32.768 kHz Crystal Oscillator
The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be
used as system clock source or as asynchronous clock source for the Real Time Counter.
10.3.4 0.4 - 16 MHz Crystal Oscillator
The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and
crystals ranging from 400 kHz to 16 MHz.
10.3.5 2 MHz Run-time Calibrated Internal Oscillator
The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator
as a source for calibrating the frequency run-time to compensate for temperature and voltage
drift hereby optimizing the accuracy of the oscillator.
10.3.6 32 MHz Run-time Calibrated Internal Oscillator
The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator
as a source for calibrating the frequency run-time to compensate for temperature and voltage
drift hereby optimizing the accuracy of the oscillator.
10.3.7 External Clock input
The external clock input gives the possibility to connect a clock from an external source.
10.3.8 PLL with Multiplication factor 1 - 31x
The PLL provides the possibility of multiplying a frequency by any number from 1 to 31. In com-
bination with the prescalers, this gives a wide range of output frequencies from all clock sources.
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11. Power Management and Sleep Modes
11.1 Features
•5 sleep modes
–Idle
– Power-down
–Power-save
–Standby
– Extended standby
•Power Reduction registers to disable clocks to unused peripherals
11.2 Overview
The XMEGA A3 provides various sleep modes tailored to reduce power consumption to a mini-
mum. All sleep modes are available and can be entered from Active mode. In Active mode the
CPU is executing application code. The application code decides when and which sleep mode to
enter. Interrupts from enabled peripherals and all enabled reset sources can restore the micro-
controller from sleep to Active mode.
In addition, Power Reduction registers provide a method to stop the clock to individual peripher-
als from software. When this is done, the current state of the peripheral is frozen and there is no
power consumption from that peripheral. This reduces the power consumption in Active mode
and Idle sleep mode.
11.3 Sleep Modes
11.3.1 Idle Mode
In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the
Interrupt Controller, Event System and DMA Controller are kept running. Interrupt requests from
all enabled interrupts will wake the device.
11.3.2 Power-down Mode
In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC)
clock source, are stopped. This allows operation of asynchronous modules only. The only inter-
rupts that can wake up the MCU are the Two Wire Interface address match interrupts, and
asynchronous port interrupts, e.g pin change.
11.3.3 Power-save Mode
Power-save mode is identical to Power-down, with one exception: If the RTC is enabled, it will
keep running during sleep and the device can also wake up from RTC interrupts.
11.3.4 Standby Mode
Standby mode is identical to Power-down with the exception that all enabled system clock
sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces
the wake-up time when external crystals or resonators are used.
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11.3.5 Extended Standby Mode
Extended Standby mode is identical to Power-save mode with the exception that all enabled
system clock sources are kept running while the CPU and Peripheral clocks are stopped. This
reduces the wake-up time when external crystals or resonators are used.
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12. System Control and Reset
12.1 Features
•Multiple reset sources for safe operation and device reset
– Power-On Reset
– External Reset
– Watchdog Reset
The Watchdog Timer runs from separate, dedicated oscillator
– Brown-Out Reset
Accurate, programmable Brown-Out levels
– PDI reset
– Software reset
•Asynchronous reset
– No running clock in the device is required for reset
•Reset status register
12.2 Resetting the AVR
During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Appli-
cation execution starts from the Reset Vector. The instruction placed at the Reset Vector should
be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector
address is the lowest Flash program memory address, ‘0’, but it is possible to move the Reset
Vector to the first address in the Boot Section.
The I/O ports of the AVR are immediately tri-stated when a reset source goes active. The reset
functionality is asynchronous, so no running clock is required to reset the device. After the
device is reset, the reset source can be determined by the application by reading the Reset Sta-
tus Register.
12.3 Reset Sources
12.3.1 Power-On Reset
The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.
12.3.2 External Reset
The MCU is reset when a low level is present on the RESET pin.
12.3.3 Watchdog Reset
The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled.
The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For
more details see ”WDT - Watchdog Timer” on page 24.
12.3.4 Brown-Out Reset
The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage
and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.
12.3.5 PDI reset
The MCU can be reset through the Program and Debug Interface (PDI).
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12.3.6 Software reset
The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.
13. WDT - Watchdog Timer
13.1 Features
•11 selectable timeout periods, from 8 ms to 8s.
•Two operation modes
– Standard mode
– Window mode
•Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator
•Configuration lock to prevent unwanted changes
13.2 Overview
The XMEGA A3 has a Watchdog Timer (WDT). The WDT will run continuously when turned on
and if the Watchdog Timer is not reset within a software configurable time-out period, the micro-
controller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset
the WDT, and prevent microcontroller reset.
The WDT has a Window mode. In this mode the WDR instruction must be run within a specified
period called a window. Application software can set the minimum and maximum limits for this
window. If the WDR instruction is not executed inside the window limits, the microcontroller will
be reset.
A protection mechanism using a timed write sequence is implemented in order to prevent
unwanted enabling, disabling or change of WDT settings.
For maximum safety, the WDT also has an Always-on mode. This mode is enabled by program-
ming a fuse. In Always-on mode, application software can not disable the WDT.
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14. PMIC - Programmable Multi-level Interrupt Controller
14.1 Features
•Separate interrupt vector for each interrupt
•Short, predictable interrupt response time
•Programmable Multi-level Interrupt Controller
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
•Interrupt vectors can be moved to the start of the Boot Section
14.2 Overview
XMEGA A3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrupts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both low-
and medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
14.3 Interrupt vectors
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for
specific interrupts in each peripheral. The base addresses for the XMEGA A3 devices are shown
in Table 14-1. Offset addresses for each interrupt available in the peripheral are described for
each peripheral in the XMEGA A manual. For peripherals or modules that have only one inter-
rupt, the interrupt vector is shown in Table 14-1. The program address is the word address.
Table 14-1. Reset and Interrupt Vectors
Program Address
(Base Address) Source Interrupt Description
0x000 RESET
0x002 OSCF_INT_vect Crystal Oscillator Failure Interrupt vector (NMI)
0x004 PORTC_INT_base Port C Interrupt base
0x008 PORTR_INT_base Port R Interrupt base
0x00C DMA_INT_base DMA Controller Interrupt base
0x014 RTC_INT_base Real Time Counter Interrupt base
0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base
0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base
0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base
0x030 SPIC_INT_vect SPI on port C Interrupt vector
0x032 USARTC0_INT_base USART 0 on port C Interrupt base
0x03D USARTC1_INT_base USART 1 on port C Interrupt base
0x03E AES_INT_vect AES Interrupt vector
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0x040 NVM_INT_base Non-Volatile Memory Interrupt base
0x044 PORTB_INT_base Port B Interrupt base
0x048 ACB_INT_base Analog Comparator on Port B Interrupt base
0x04E ADCB_INT_base Analog to Digital Converter on Port B Interrupt base
0x056 PORTE_INT_base Port E INT base
0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base
0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base
0x06A TCE1_INT_base Timer/Counter 1 on port E Interrupt base
0x072 SPIE_INT_vect SPI on port E Interrupt vector
0x074 USARTE0_INT_base USART 0 on port E Interrupt base
0x07A USARTE1_INT_base USART 1 on port E Interrupt base
0x080 PORTD_INT_base Port D Interrupt base
0x084 PORTA_INT_base Port A Interrupt base
0x088 ACA_INT_base Analog Comparator on Port A Interrupt base
0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base
0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base
0x0A6 TCD1_INT_base Timer/Counter 1 on port D Interrupt base
0x0AE SPID_INT_vector SPI D Interrupt vector
0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base
0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base
0x0D0 PORTF_INT_base Port F Interrupt base
0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base
0x0EE USARTF0_INT_base USART 0 on port F Interrupt base
Table 14-1. Reset and Interrupt Vectors (Continued)
Program Address
(Base Address) Source Interrupt Description
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15. I/O Ports
15.1 Features
•Selectable input and output configuration for each pin individually
•Flexible pin configuration through dedicated Pin Configuration Register
•Synchronous and/or asynchronous input sensing with port interrupts and events
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
•Asynchronous wake-up from all input sensing configurations
•Two port interrupts with flexible pin masking
•Highly configurable output driver and pull settings:
– Totem-pole
– Pull-up/-down
– Wired-AND
– Wired-OR
– Bus-keeper
– Inverted I/O
•Configuration of multiple pins in a single operation
•Read-Modify-Write (RMW) support
•Toggle/clear/set registers for Output and Direction registers
•Clock output on port pin
•Event Channel 0 output on port pin 7
•Mapping of port registers (virtual ports) into bit accessible I/O memory space
15.2 Overview
The XMEGA A3 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins,
ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asyn-
chronous input sensing, pin change interrupts and configurable output settings. All functions are
individual per pin, but several pins may be configured in a single operation.
15.3 I/O configuration
All port pins (Pn) have programmable output configuration. In addition, all port pins have an
inverted I/O function. For an input, this means inverting the signal between the port pin and the
pin register. For an output, this means inverting the output signal between the port register and
the port pin. The inverted I/O function can be used also when the pin is used for alternate
functions.
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15.3.1 Push-pull
Figure 15-1. I/O configuration - Totem-pole
15.3.2 Pull-down
Figure 15-2. I/O configuration - Totem-pole with pull-down (on input)
15.3.3 Pull-up
Figure 15-3. I/O configuration - Totem-pole with pull-up (on input)
15.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as
a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.
INn
OUTn
DIRn
Pn
INn
OUTn
DIRn
Pn
INn
OUTn
DIRn
Pn
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XMEGA A3
Figure 15-4. I/O configuration - Totem-pole with bus-keeper
15.3.5 Others
Figure 15-5. Output configuration - Wired-OR with optional pull-down
Figure 15-6. I/O configuration - Wired-AND with optional pull-up
INn
OUTn
DIRn
Pn
INn
OUTn
Pn
INn
OUTn
Pn
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15.4 Input sensing
•Sense both edges
•Sense rising edges
•Sense falling edges
•Sense low level
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports,
and the configuration is shown in Figure 15-7 on page 30.
Figure 15-7. Input sensing system overview
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
15.5 Port Interrupt
Each port has two interrupts with separate priority and interrupt vector. All pins on the port can
be individually selected as source for each of the interrupts. The interrupts are then triggered
according to the input sense configuration for each pin configured as source for the interrupt.
15.6 Alternate Port Functions
In addition to the input/output functions on all port pins, most pins have alternate functions. This
means that other modules or peripherals connected to the port can use the port pins for their
functions, such as communication or pulse-width modulation. ”Pinout and Pin Functions” on
page 49 shows which modules on peripherals that enable alternate functions on a pin, and
which alternate functions that are available on a pin.
INV ER TE D I/O
Interrupt
Control IREQ
Event
Pn
DQ
R
DQ
R
Synchronizer
INn
EDGE
DETECT
A synchronous sensing
Syn chrono us sensing
EDGE
DETECT
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16. T/C - 16-bits Timer/Counter with PWM
16.1 Features
•Seven 16-bit Timer/Counters
– Four Timer/Counters of type 0
– Three Timer/Counters of type 1
•Four Compare or Capture (CC) Channels in Timer/Counter 0
•Two Compare or Capture (CC) Channels in Timer/Counter 1
•Double Buffered Timer Period Setting
•Double Buffered Compare or Capture Channels
•Waveform Generation:
– Single Slope Pulse Width Modulation
– Dual Slope Pulse Width Modulation
– Frequency Generation
•Input Capture:
– Input Capture with Noise Cancelling
– Frequency capture
– Pulse width capture
– 32-bit input capture
•Event Counter with Direction Control
•Timer Overflow and Timer Error Interrupts and Events
•One Compare Match or Capture Interrupt and Event per CC Channel
•Supports DMA Operation
•Hi-Resolution Extension (Hi-Res)
•Advanced Waveform Extension (AWEX)
16.2 Overview
XMEGA A3 has seven Timer/Counters, four Timer/Counter 0 and three Timer/Counter 1. The
difference between them is that Timer/Counter 0 has four Compare/Capture channels, while
Timer/Counter 1 has two Compare/Capture channels.
The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the
microcontroller. A programmable prescaler is available to get a useful T/C resolution. Updates of
Timer and Compare registers are double buffered to ensure glitch free operation. Single slope
PWM, dual slope PWM and frequency generation waveforms can be generated using the Com-
pare Channels.
Through the Event System, any input pin or event in the microcontroller can be used to trigger
input capture, hence no dedicated pins is required for this. The input capture has a noise cancel-
ler to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width
measurements.
A wide range of interrupt or event sources are available, including T/C Overflow, Compare
match and Capture for each Compare/Capture channel in the T/C.
PORTC, PORTD and PORTE each has one Timer/Counter 0 and one Timer/Counter1. PORTF
has one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1,
TCE0, TCE1 and TCF0, respectively.
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Figure 16-1. Overview of a Timer/Counter and closely related peripherals
The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by
2 bits (4x). This is available for all Timer/Counters. See ”Hi-Res - High Resolution Extension” on
page 34 for more details.
The Advanced Waveform Extension can be enabled to provide extra and more advanced fea-
tures for the Timer/Counter. This are only available for Timer/Counter 0. See ”AWEX - Advanced
Waveform Extension” on page 33 for more details.
AWeX
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
Waveform
Generation
Buffer
Comparator
Hi-Res
Fault
Protection
Capture
Control
Base Counter
Counter Control Logic
Timer Period
Prescaler
DTI
Dead-Time
Insertion
Pattern
Generation
clkPER4
PORT
Event
System
clkPER
Timer/Counter
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17. AWEX - Advanced Waveform Extension
17.1 Features
•Output with complementary output from each Capture channel
•Four Dead Time Insertion (DTI) Units, one for each Capture channel
•8-bit DTI Resolution
•Separate High and Low Side Dead-Time Setting
•Double Buffered Dead-Time
•Event Controlled Fault Protection
•Single Channel Multiple Output Operation (for BLDC motor control)
•Double Buffered Pattern Generation
17.2 Overview
The Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in
Waveform Generation (WG) modes. The AWEX enables easy and safe implementation of for
example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications.
Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any
AWEX feature is enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that
enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG
output with dead time insertion between LS and HS switching. The DTI output will override the
normal port value according to the port override setting. Optionally the final output can be
inverted by using the invert I/O setting for the port pin.
The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is
connected to. In addition, the waveform generator output from Compare Channel A can be dis-
tributed to, and override all port pins. When the Pattern Generator unit is enabled, the DTI unit is
bypassed.
The Fault Protection unit is connected to the Event System. This enables any event to trigger a
fault condition that will disable the AWEX output. Several event channels can be used to trigger
fault on several different conditions.
The AWEX is available for TCC0. The notation of this is AWEXC.
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18. Hi-Res - High Resolution Extension
18.1 Features
•Increases Waveform Generator resolution by 2-bits (4x)
•Supports Frequency, single- and dual-slope PWM operation
•Supports the AWEX when this is enabled and used for the same Timer/Counter
18.2 Overview
The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform genera-
tion output by a factor of 4. When enabled for a Timer/Counter, the Fast Peripheral clock running
at four times the CPU clock speed will be as input to the Timer/Counter.
The High Resolution Extension can also be used when an AWEX is enabled and used with a
Timer/Counter.
XMEGA A3 devices have four Hi-Res Extensions that each can be enabled for each
Timer/Counters pair on PORTC, PORTD, PORTE and PORTF. The notation of these are
HIRESC, HIRESD, HIRESE and HIRESF, respectively.
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19. RTC - Real-Time Counter
19.1 Features
•16-bit Timer
•Flexible Tick resolution ranging from 1 Hz to 32.768 kHz
•One Compare register
•One Period register
•Clear timer on Overflow or Compare Match
•Overflow or Compare Match event and interrupt generation
19.2 Overview
The XMEGA A3 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an
accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the
32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare
register. For details, see Figure 19-1.
A wide range of Resolution and Time-out periods can be configured using the RTC. With a max-
imum resolution of 30.5 µs, time-out periods range up to 2000 seconds. With a resolution of 1
second, the maximum time-out period is over 18 hours (65536 seconds).
Figure 19-1. Real-time Counter overview
10-bit
prescaler Counter
Period
Compare
=
=
Overflow
Compare Ma tch
1.024 kH z
32.768 kH z
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20. TWI - Two Wire Interface
20.1 Features
•Two Identical TWI peripherals
•Simple yet Powerful and Flexible Communication Interface
•Both Master and Slave Operation Supported
•Device can Operate as Transmitter or Receiver
•7-bit Address Space Allows up to 128 Different Slave Addresses
•Multi-master Arbitration Support
•Up to 400 kHz Data Transfer Speed
•Slew-rate Limited Output Drivers
•Noise Suppression Circuitry Rejects Spikes on Bus Lines
•Fully Programmable Slave Address with General Call Support
•Address Recognition Causes Wake-up when in Sleep Mode
•I2C and System Management Bus (SMBus) compatible
20.2 Overview
The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock
(SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 indi-
vidually addressable devices. Since it is a multi-master bus, one or more devices capable of
taking control of the bus can be connected.
The only external hardware needed to implement the bus is a single pull-up resistor for each of
the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
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21. SPI - Serial Peripheral Interface
21.1 Features
•Three Identical SPI peripherals
•Full-duplex, Three-wire Synchronous Data Transfer
•Master or Slave Operation
•LSB First or MSB First Data Transfer
•Seven Programmable Bit Rates
•End of Transmission Interrupt Flag
•Write Collision Flag Protection
•Wake-up from Idle Mode
•Double Speed (CK/2) Master SPI Mode
21.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer
between different devices. Devices can communicate using a master-slave scheme, and data is
transferred both to and from the devices simultaneously.
PORTC, PORTD, and PORTE each has one SPI. Notation of these peripherals are SPIC, SPID,
and SPIE respectively.
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22. USART
22.1 Features
•Seven Identical USART peripherals
•Full Duplex Operation (Independent Serial Receive and Transmit Registers)
•Asynchronous or Synchronous Operation
•Master or Slave Clocked Synchronous Operation
•High-resolution Arithmetic Baud Rate Generator
•Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
•Odd or Even Parity Generation and Parity Check Supported by Hardware
•Data OverRun Detection
•Framing Error Detection
•Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
•Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
•Multi-processor Communication Mode
•Double Speed Asynchronous Communication Mode
•Master SPI mode for SPI communication
•IrDA support through the IRCOM module
22.2 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication module. The USART supports full duplex communication,
and both asynchronous and clocked synchronous operation. The USART can also be set in
Master SPI mode to be used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both direction, enabling continued data transmis-
sion without any delay between frames. There are separate interrupt vectors for receive and
transmit complete, enabling fully interrupt driven communication. Frame error and buffer over-
flow are detected in hardware and indicated with separate status flags. Even or odd parity
generation and parity check can also be enabled.
One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modula-
tion and demodulation for baud rates up to 115.2 kbps.
PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only.
Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0,
USARTE1 and USARTF0, respectively.
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23. IRCOM - IR Communication Module
23.1 Features
•Pulse modulation/demodulation for infrared communication
•Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps
•Selectable pulse modulation scheme
– 3/16 of baud rate period
– Fixed pulse period, 8-bit programmable
– Pulse modulation disabled
•Built in filtering
•Can be connected to and used by one USART at a time
23.2 Overview
XMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with
baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period,
fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation dis-
abled. There is one IRCOM available which can be connected to any USART to enable infrared
pulse coding/decoding for that USART.
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XMEGA A3
24. Crypto Engine
24.1 Features
•Data Encryption Standard (DES) CPU instruction
•Advanced Encryption Standard (AES) Crypto module
•DES Instruction
– Encryption and Decryption
– Single-cycle DES instruction
– Encryption/Decryption in 16 clock cycles per 8-byte block
•AES Crypto Module
– Encryption and Decryption
– Support 128-bit keys
– Support XOR data load mode to the State memory for Cipher Block Chaining
– Encryption/Decryption in 375 clock cycles per 16-byte block
24.2 Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two com-
monly used encryption standards. These are supported through an AES peripheral module and
a DES CPU instruction. All communication interfaces and the CPU can optionally use AES and
DES encrypted communication and data storage.
DES is supported by a DES instruction in the AVR XMEGA CPU. The 8-byte key and 8-byte
data blocks must be loaded into the Register file, and then DES must be executed 16 times to
encrypt/decrypt the data block.
The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key.
The key and data must be loaded into the key and state memory in the module before encryp-
tion/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is
done and decrypted/encrypted data can be read out, and an optional interrupt can be generated.
The AES Crypto Module also has DMA support with transfer triggers when encryption/decryp-
tion is done and optional auto-start of encryption/decryption when the state memory is fully
loaded.
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XMEGA A3
25. ADC - 12-bit Analog to Digital Converter
25.1 Features
•Two ADCs with 12-bit resolution
•2 Msps sample rate for each ADC
•Signed and Unsigned conversions
•4 result registers with individual input channel control for each ADC
•8 single ended inputs for each ADC
•8x4 differential inputs for each ADC
•4 internal inputs:
– Integrated Temperature Sensor
– DAC Output
– VCC voltage divided by 10
– Bandgap voltage
•Software selectable gain of 2, 4, 8, 16, 32 or 64
•Software selectable resolution of 8- or 12-bit.
•Internal or External Reference selection
•Event triggered conversion for accurate timing
•DMA transfer of conversion results
•Interrupt/Event on compare result
25.2 Overview
XMEGA A3 devices have two Analog to Digital Converters (ADC), see Figure 25-1 on page 42.
The two ADC modules can be operated simultaneously, individually or synchronized.
The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capa-
ble of converting up to 2 million samples per second. The input selection is flexible, and both
single-ended and differential measurements can be done. For differential measurements an
optional gain stage is available to increase the dynamic range. In addition several internal signal
inputs are available. The ADC can provide both signed and unsigned results.
This is a pipeline ADC. A pipeline ADC consists of several consecutive stages, where each
stage convert one part of the result. The pipeline design enables high sample rate at low clock
speeds, and remove limitations on samples speed versus propagation delay. This also means
that a new analog voltage can be sampled and a new ADC measurement started while other
ADC measurements are ongoing.
ADC measurements can either be started by application software or an incoming event from
another peripheral in the device. Four different result registers with individual input selection
(MUX selection) are provided to make it easier for the application to keep track of the data. Each
result register and MUX selection pair is referred to as an ADC Channel. It is possible to use
DMA to move ADC results directly to memory or peripherals when conversions are done.
Both internal and external analog reference voltages can be used. An accurate internal 1.0V
reference is available.
An integrated temperature sensor is available and the output from this can be measured with the
ADC. The output from the DAC, VCC/10 and the Bandgap voltage can also be measured by the
ADC.
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XMEGA A3
Figure 25-1. ADC overview
Each ADC has four MUX selection registers with a corresponding result register. This means
that four channels can be sampled within 1.5 µs without any intervention by the application other
than starting the conversion. The results will be available in the result registers.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop-
agation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB,
respectively.
ADC
Channel A
Register
Channel B
Register
Channel C
Register
Channel D
Register
Pin inputsPin inputs
1-64 X
Internal inputs
Channel A MUX selection
Channel B MUX selection
Channel C MUX selection
Channel D MUX selection
Event
Trigger
Configuration
Reference selection
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26. DAC - 12-bit Digital to Analog Converter
26.1 Features
•One DAC with 12-bit resolution
•Up to 1 Msps conversion rate for each DAC
•Flexible conversion range
•Multiple trigger sources
•1 continuous output or 2 Sample and Hold (S/H) outputs for each DAC
•Built-in offset and gain calibration
•High drive capabilities
•Low Power Mode
26.2 Overview
The XMEGA A3 features one two-channel, 12-bit, 1 Msps DACs with built-in offset and gain cal-
ibration, see Figure 26-1 on page 43.
A DAC converts a digital value into an analog signal. The DAC may use an internal 1.0 voltage
as the upper limit for conversion, but it is also possible to use the supply voltage or any applied
voltage in-between. The external reference input is shared with the ADC reference input.
Figure 26-1. DAC overview
The DAC has one continuous output with high drive capabilities for both resistive and capacitive
loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H)
channels, each with separate data conversion registers.
A DAC conversion may be started from the application software by writing the data conversion
registers. The DAC can also be configured to do conversions triggered by the Event System to
have regular timing, independent of the application software. DMA may be used for transferring
data from memory locations to DAC data registers.
The DAC has a built-in calibration system to reduce offset and gain error when loading with a
calibration value from software.
PORTB each has one DAC. Notation of this peripheral is DACB.
DAC
Channel A
Register
Channel B
Register
Event
Trigger
Configuration
Refe re nce sele c tion
Channel A
Channel B
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27. AC - Analog Comparator
27.1 Features
•Four Analog Comparators
•Selectable Power vs. Speed
•Selectable hysteresis
– 0, 20 mV, 50 mV
•Analog Comparator output available on pin
•Flexible Input Selection
– All pins on the port
– Output from the DAC
– Bandgap reference voltage.
– Voltage scaler that can perform a 64-level scaling of the internal VCC voltage.
•Interrupt and event generation on
– Rising edge
– Falling edge
–Toggle
•Window function interrupt and event generation on
– Signal above window
– Signal inside window
– Signal below window
27.2 Overview
XMEGA A3 features four Analog Comparators (AC). An Analog Comparator compares two volt-
ages, and the output indicates which input is largest. The Analog Comparator may be configured
to give interrupt requests and/or events upon several different combinations of input change.
Both hysteresis and propagation delays may be adjusted in order to find the optimal operation
for each application.
A wide range of input selection is available, both external pins and several internal signals can
be used.
The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They
have identical behavior but separate control registers.
Optionally, the state of the comparator is directly available on a pin.
PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.
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Figure 27-1. Analog comparator overview
AC0
+
-
Pin inputs
Internal inputs
Pin inputs
Internal inputs
VCC scaled Interrupt
sensitivity
control
Interrupts
AC1
+
-
Pin inputs
Internal inputs
Pin inputs
Internal inputs
VCC scaled
Events
Pin 0 output
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27.3 Input Selection
The Analog comparators have a very flexible input selection and the two comparators grouped
in a pair may be used to realize a window function. One pair of analog comparators is shown in
Figure 27-1 on page 45.
•Input selection from pin
– Pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator
– Pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator
•Internal signals available on positive analog comparator inputs
– Output from 12-bit DAC
•Internal signals available on negative analog comparator inputs
– 64-level scaler of the VCC, available on negative analog comparator input
– Bandgap voltage reference
•Output from 12-bit DAC
27.4 Window Function
The window function is realized by connecting the external inputs of the two analog comparators
in a pair as shown in Figure 27-2.
Figure 27-2. Analog comparator window function
AC0
+
-
AC1
+
-
Input signal
Upper limit of window
Lower limit of window
Interrupt
sensitivity
control
Interrupts
Events
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28. OCD - On-chip Debug
28.1 Features
•Complete Program Flow Control
– Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor
•Debugging on C and high-level language source code level
•Debugging on Assembler and disassembler level
•1 dedicated program address or source level breakpoint for AVR Studio / debugger
•4 Hardware Breakpoints
•Unlimited Number of User Program Breakpoints
•Unlimited Number of User Data Breakpoints, with break on:
– Data location read, write or both read and write
– Data location content equal or not equal to a value
– Data location content is greater or less than a value
– Data location content is within or outside a range
– Bits of a data location are equal or not equal to a value
•Non-Intrusive Operation
– No hardware or software resources in the device are used
•High Speed Operation
– No limitation on debug/programming clock frequency versus system clock frequency
28.2 Overview
The XMEGA A3 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s
development tools - provides all the necessary functions to debug an application. It has support
for program and data breakpoints, and can debug an application from C and high level language
source code level, as well as assembler and disassembler level. It has full Non-Intrusive Opera-
tion and no hardware or software resources in the device are used. The ODC system is
accessed through an external debugging tool which connects to the JTAG or PDI physical inter-
faces. Refer to ”Program and Debug Interfaces” on page 48.
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XMEGA A3
29. Program and Debug Interfaces
29.1 Features
•PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)
•JTAG Interface (IEEE std. 1149.1 compliant)
•Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG)
•Access to the OCD system
•Programming of Flash, EEPROM, Fuses and Lock Bits
29.2 Overview
The programming and debug facilities are accessed through the JTAG and PDI physical inter-
faces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no
general purpose pins are used. JTAG uses four general purpose pins on PORTB.
The PDI is an Atmel proprietary protocol for communication between the microcontroller and
Atmel’s or third party development tools.
29.3 IEEE 1149.1 (JTAG) Boundary-scan
The JTAG physical layer handles the basic low-level serial communication over four I/O lines
named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and
boundary scan.
29.3.1 Boundary-scan Order
Table 30-8 on page 53 shows the Scan order between TDI and TDO when the Boundary-scan
chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned
out. The scan order follows the pin-out order. Bit 4, 5, 6 and 7 of Port B is not in the scan chain,
since these pins constitute the TAP pins when the JTAG is enabled.
29.3.2 Boundary-scan Description Language Files
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description. BSDL files are available for
ATxmega256/192/128/64A3 devices.
See Table 30-8 on page 53 for ATxmega256/192/128/64A3 Boundary Scan Order.
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30. Pinout and Pin Functions
The pinout of XMEGA A3 is shown in ”” on page 2. In addition to general I/O functionality, each
pin may have several function. This will depend on which peripheral is enabled and connected to
the actual pin. Only one of the alternate pin functions can be used at time.
30.1 Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
30.1.1 Operation/Power Supply
30.1.2 Port Interrupt functions
30.1.3 Analog functions
30.1.4 Timer/Counter and AWEX functions
VCC Digital supply voltage
AVCC Analog supply voltage
GND Ground
SYNC Port pin with full synchronous and limited asynchronous interrupt function
ASYNC Port pin with full synchronous and full asynchronous interrupt function
ACn Analog Comparator input pin n
AC0OUT Analog Comparator 0 Output
ADCn Analog to Digital Converter input pin n
DACn Digital to Analog Converter output pin n
AREF Analog Reference input pin
OCnx Output Compare Channel x for Timer/Counter n
OCnx Inverted Output Compare Channel x for Timer/Counter n
OCnxLS Output Compare Channel x Low Side for Timer/Counter n
OCnxHS Output Compare Channel x High Side for Timer/Counter n
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30.1.5 Communication functions
30.1.6 Oscillators, Clock and Event
30.1.7 Debug/System functions
SCL Serial Clock for TWI
SDA Serial Data for TWI
SCLIN Serial Clock In for TWI when external driver interface is enabled
SCLOUT Serial Clock Out for TWI when external driver interface is enabled
SDAIN Serial Data In for TWI when external driver interface is enabled
SDAOUT Serial Data Out for TWI when external driver interface is enabled
XCKn Transfer Clock for USART n
RXDn Receiver Data for USART n
TXDn Transmitter Data for USART n
SS Slave Select for SPI
MOSI Master Out Slave In for SPI
MISO Master In Slave Out for SPI
SCK Serial Clock for SPI
TOSCn Timer Oscillator pin n
XTALn Input/Output for inverting Oscillator pin n
CLKOUT Peripheral Clock Output
EVOUT Event Channel 0 Output
RESET Reset pin
PDI_CLK Program and Debug Interface Clock pin
PDI_DATA Program and Debug Interface Data pin
T CK J TAG Test C l o ck
TDI JTAG Test Data In
T DO JTAG Te s t Data Ou t
T MS J TAG Te s t M o d e S e l ec t
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30.2 Alternate Pin Functions
The tables below show the main and alternate pin functions for all pins on each port. They also
show which peripheral that makes use of or enables the alternate pin function.
Table 30-1. Port A - Alternate functions
PORT A PIN # INTERRUPT ADCA POS ADCA NEG
ADAA
GAINPOS
ADCA
GAINNEG ACA POS ACA NEG ACA OUT REFA
GND 60
AVCC 61
PA0 62 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREF
PA1 63 SYNC ADC1 ADC1 ADC1 AC1 AC1
PA2 64 SYNC/ASYNC ADC2 ADC2 ADC2 AC2
PA3 1 SYNC ADC3 ADC3 ADC3 AC3 AC3
PA4 2 SYNC ADC4 ADC4 ADC4 AC4
PA5 3 SYNC ADC5 ADC5 ADC5 AC5 AC5
PA6 4 SYNC ADC6 ADC6 ADC6 AC6
PA7 5 SYNC ADC7 ADC7 ADC7 AC7 AC0 OUT
Table 30-2. Port B - Alternate functions
PORT B PIN # INTERRUPT
ADCB
POS
ADCB
NEG
ADCB
GAINPOS
ADCB
GAINNEG ACB POS ACB NEG ACB OUT DACB REFB JTAG
PB0 6 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREF
PB1 7 SYNC ADC1 ADC1 ADC1 AC1 AC1
PB2 8 SYNC/ASYNC ADC2 ADC2 ADC2 AC2 DAC0
PB3 9 SYNC ADC3 ADC3 ADC3 AC3 AC3 DAC1
PB4 10 SYNC ADC4 ADC4 ADC4 AC4 TMS
PB5 11 SYNC ADC5 ADC5 ADC5 AC5 AC5 TDI
PB6 12 SYNC ADC6 ADC6 ADC6 AC6 TCK
PB7 13 SYNC ADC7 ADC7 ADC7 AC7 AC0 OUT TDO
GND 14
VCC 15
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Table 30-3. Port C - Alternate functions
PORT C PIN # INTERRUPT TCC0 AWEXC TCC1 USARTC0 USARTC1 SPIC TWIC CLOCKOUT EVENTOUT
PC0 16 SYNC OC0A OC0ALS SDA
PC1 17 SYNC OC0B OC0AHS XCK0 SCL
PC2 18 SYNC/ASYNC OC0C OC0BLS RXD0
PC3 19 SYNC OC0D OC0BHS TXD0
PC4 20 SYNC OC0CLS OC1A SS
PC5 21 SYNC OC0CHS OC1B XCK1 MOSI
PC6 22 SYNC OC0DLS RXD1 MISO
PC7 23 SYNC OC0DHS TXD1 SCK CLKOUT EVOUT
GND 24
VCC 25
Table 30-4. Port D - Alternate functions
PORT D PIN # INTERRUPT TCD0 TCD1 USARTD0 USARTD1 SPID CLOCKOUT EVENTOUT
PD0 26 SYNC OC0A
PD1 27 SYNC OC0B XCK0
PD2 28 SYNC/ASYNC OC0C RXD0
PD3 29 SYNC OC0D TXD0
PD4 30 SYNC OC1A SS
PD5 31 SYNC OC1B XCK1 MOSI
PD6 32 SYNC RXD1 MISO
PD7 33 SYNC TXD1 SCK CLKOUT EVOUT
GND 34
VCC 35
Table 30-5. Port E - Alternate functions
PORT E PIN # INTERRUPT TCE0 TCE1 USARTE0 USARTE1 SPIE TWIE CLOCKOUT EVENTOUT TOSC
PE0 36 SYNC OC0A SDA
PE1 37 SYNC OC0B XCK0 SCL
PE2 38 SYNC/ASYNC OC0C RXD0
PE3 39 SYNC OC0D TXD0
PE4 40 SYNC OC1A SS
PE5 41 SYNC OC1B XCK1 MOSI
PE6 42 SYNC RXD1 MISO TOSC2
PE7 43 SYNC TXD1 SCK CLKOUT EVOUT TOSC1
GND 44
VCC 45
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Table 30-7. Port R - Alternate functions
Table 30-8. ATxmega256/192/128/64A3 Boundary Scan Order
Table 30-6. Port F - Alternate functions
PORT F PIN # INTERRUPT TCF0 USARTF0
PF0 46 SYNC OC0A
PF1 47 SYNC OC0B XCK0
PF2 48 SYNC/ASYNC OC0C RXD0
PF3 49 SYNC OC0D TXD0
PF4 50 SYNC
PF5 51 SYNC
PF6 54 SYNC
PF7 55 SYNC
GND 52
VCC 53
PORT R PIN # INTERRUPT PROGR XTAL
PDI 56 PDI_DATA
RESET 57 PDI_CLOCK
PRO 58 SYNC XTAL2
PR1 59 SYNC XTAL1
Bit Number Signal Name Module
149 PQ3.Bidir
PORT Q
148 PQ3.Control
147 PQ2.Bidir
146 PQ2.Control
145 PQ1.Bidir
144 PQ1.Control
143 PQ0.Bidir
142 PQ0.Control
141 PK7.Bidir
PORT K
140 PK7.Control
139 PK6.Bidir
138 PK6.Control
137 PK5.Bidir
136 PK5.Control
135 PK4.Bidir
134 PK4.Control
133 PK3.Bidir
132 PK3.Control
131 PK2.Bidir
130 PK2.Control
129 PK1.Bidir
128 PK1.Control
127 PK0.Bidir
126 PK0.Control
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125 PJ7.Bidir
PORT J
124 PJ7.Control
123 PJ6.Bidir
122 PJ6.Control
121 PJ5.Bidir
120 PJ5.Control
119 PJ4.Bidir
118 PJ4.Control
117 PJ3.Bidir
116 PJ3.Control
115 PJ2.Bidir
114 PJ2.Control
113 PJ1.Bidir
112 PJ1.Control
111 PJ0.Bidir
110 PJ0.Control
109 PH7.Bidir
PORT H
108 PH7.Control
107 PH6.Bidir
106 PH6.Control
105 PH5.Bidir
104 PH5.Control
103 PH4.Bidir
102 PH4.Control
101 PH3.Bidir
100 PH3.Control
99 PH2.Bidir
98 PH2.Control
97 PH1.Bidir
96 PH1.Control
95 PH0.Bidir
94 PH0.Control
93 PF7.Bidir
PORT F
92 PF7.Control
91 PF6.Bidir
90 PF6.Control
89 PF5.Bidir
88 PF5.Control
87 PF4.Bidir
86 PF4.Control
85 PF3.Bidir
84 PF3.Control
83 PF2.Bidir
82 PF2.Control
81 PF1.Bidir
80 PF1.Control
79 PF0.Bidir
78 PF0.Control
77 PE7.Bidir
PORT E
76 PE7.Control
75 PE6.Bidir
74 PE6.Control
73 PE5.Bidir
72 PE5.Control
71 PE4.Bidir
70 PE4.Control
69 PE3.Bidir
68 PE3.Control
67 PE2.Bidir
66 PE2.Control
65 PE1.Bidir
64 PE1.Control
63 PE0.Bidir
62 PE0.Control
Bit Number Signal Name Module
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61 PD7.Bidir
PORT D
60 PD7.Control
59 PD6.Bidir
58 PD6.Control
57 PD5.Bidir
56 PD5.Control
55 PD4.Bidir
54 PD4.Control
53 PD3.Bidir
52 PD3.Control
51 PD2.Bidir
50 PD2.Control
49 PD1.Bidir
48 PD1.Control
47 PD0.Bidir
46 PD0.Control
45 PC7.Bidir
PORT C
44 PC7.Control
43 PC6.Bidir
42 PC6.Control
41 PC5.Bidir
40 PC5.Control
39 PC4.Bidir
38 PC4.Control
37 PC3.Bidir
36 PC3.Control
35 PC2.Bidir
34 PC2.Control
33 PC1.Bidir
32 PC1.Control
31 PC0.Bidir
30 PC0.Control
29 PB3.Bidir
PORT B
28 PB3.Control
27 PB2.Bidir
26 PB2.Control
25 PB1.Bidir
24 PB1.Control
23 PB0.Bidir
22 PB0.Control
21 PA7.Bidir
PORT A
20 PA7.Control
19 PA6.Bidir
18 PA6.Control
17 PA5.Bidir
16 PA5.Control
15 PA4.Bidir
14 PA4.Control
13 PA3.Bidir
12 PA3.Control
11 PA2.Bidir
10 PA2.Control
9 PA1.Bidir
8 PA1.Control
7 PA0.Bidir
6 PA0.Control
5 PR1.Bidir
PORT R
4PR1.Control
3 PR0.Bidir
2PR0.Control
1 RESET.Observe_Only RESET
0 PDI_DATA.Observe_Only PDI Data
Bit Number Signal Name Module
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31. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA A3. For
complete register description and summary for each peripheral module, refer to the XMEGA A
Manual.
Base Address Name Description
0x0000 GPIO General Purpose IO Registers
0x0010 VPORT0 Virtual Port 0
0x0014 VPORT1 Virtual Port 1
0x0018 VPORT2 Virtual Port 2
0x001C VPORT3 Virtual Port 2
0x0030 CPU CPU
0x0040 CLK Clock Control
0x0048 SLEEP Sleep Controller
0x0050 OSC Oscillator Control
0x0060 DFLLRC32M DFLL for the 32 MHz Internal RC Oscillator
0x0068 DFLLRC2M DFLL for the 2 MHz RC Oscillator
0x0070 PR Power Reduction
0x0078 RST Reset Controller
0x0080 WDT Watch-Dog Timer
0x0090 MCU MCU Control
0x00A0 PMIC Programmable MUltilevel Interrupt Controller
0x00B0 PORTCFG Port Configuration
0x00C0 AES AES Module
0x0100 DMA DMA Controller
0x0180 EVSYS Event System
0x01C0 NVM Non Volatile Memory (NVM) Controller
0x0200 ADCA Analog to Digital Converter on port A
0x0240 ADCB Analog to Digital Converter on port B
0x0320 DACB Digital to Analog Converter on port B
0x0380 ACA Analog Comparator pair on port A
0x0390 ACB Analog Comparator pair on port B
0x0400 RTC Real Time Counter
0x0480 TWIC Two Wire Interface on port C
0x04A0 TWIE Two Wire Interfaceon port E
0x0600 PORTA Port A
0x0620 PORTB Port B
0x0640 PORTC Port C
0x0660 PORTD Port D
0x0680 PORTE Port E
0x06A0 PORTF Port F
0x07E0 PORTR Port R
0x0800 TCC0 Timer/Counter 0 on port C
0x0840 TCC1 Timer/Counter 1 on port C
0x0880 AWEXC Advanced Waveform Extension on port C
0x0890 HIRESC High Resolution Extension on port C
0x08A0 USARTC0 USART 0 on port C
0x08B0 USARTC1 USART 1 on port C
0x08C0 SPIC Serial Peripheral Interface on port C
0x08F8 IRCOM Infrared Communication Module
0x0900 TCD0 Timer/Counter 0 on port D
0x0940 TCD1 Timer/Counter 1 on port D
0x0990 HIRESD High Resolution Extension on port D
0x09A0 USARTD0 USART 0 on port D
0x09B0 USARTD1 USART 1 on port D
0x09C0 SPID Serial Peripheral Interface on port D
0x0A00 TCE0 Timer/Counter 0 on port E
0x0A40 TCE1 Timer/Counter 1 on port E
0x0A80 AWEXE Advanced Waveform Extensionon port E
0x0A90 HIRESE High Resolution Extension on port E
0x0AA0 USARTE0 USART 0 on port E
0x0AB0 USARTE1 USART 1 on oirt E
0x0AC0 SPIE Serial Peripheral Interface on port E
0x0B00 TCF0 Timer/Counter 0 on port F
0x0B90 HIRESF High Resolution Extension on port F
0x0BA0 USARTF0 USART 0 on port F
57
8068T–AVR–12/10
XMEGA A3
32. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
Arithmetic and Logic Instructions
ADD Rd, Rr Add without Carry Rd ←Rd + Rr Z,C,N,V,S,H 1
ADC Rd, Rr Add with Carry Rd ←Rd + Rr + C Z,C,N,V,S,H 1
ADIWRd, K Add Immediate to Word Rd ←Rd + 1:Rd + K Z,C,N,V,S 2
SUB Rd, Rr Subtract without Carry Rd ←Rd - Rr Z,C,N,V,S,H 1
SUBI Rd, K Subtract Immediate Rd ←Rd - K Z,C,N,V,S,H 1
SBC Rd, Rr Subtract with Carry Rd ←Rd - Rr - C Z,C,N,V,S,H 1
SBCI Rd, K Subtract Immediate with Carry Rd ←Rd - K - C Z,C,N,V,S,H 1
SBIWRd, K Subtract Immediate from Word Rd + 1:Rd ←Rd + 1:Rd - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Rd ←Rd • Rr Z,N,V,S 1
ANDI Rd, K Logical AND with Immediate Rd ←Rd • K Z,N,V,S 1
OR Rd, Rr Logical OR Rd ←Rd v Rr Z,N,V,S 1
ORI Rd, K Logical OR with Immediate Rd ←Rd v K Z,N,V,S 1
EOR Rd, Rr Exclusive OR Rd ←Rd ⊕ Rr Z,N,V,S 1
COM Rd One’s Complement Rd ←$FF - Rd Z,C,N,V,S 1
NEG Rd Two’s Complement Rd ←$00 - Rd Z,C,N,V,S,H 1
SBR Rd,K Set Bit(s) in Register Rd ←Rd v K Z,N,V,S 1
CBR Rd,K Clear Bit(s) in Register Rd ←Rd • ($FFh - K) Z,N,V,S 1
INC Rd Increment Rd ←Rd + 1 Z,N,V,S 1
DEC Rd Decrement Rd ←Rd - 1 Z,N,V,S 1
TST Rd Test for Zero or Minus Rd ←Rd • Rd Z,N,V,S 1
CLR Rd Clear Register Rd ←Rd ⊕ Rd Z,N,V,S 1
SER Rd Set Register Rd ←$FF None 1
MUL Rd,Rr Multiply Unsigned R1:R0 ←Rd x Rr (UU) Z,C 2
MULS Rd,Rr Multiply Signed R1:R0 ←Rd x Rr (SS) Z,C 2
MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ←Rd x Rr (SU) Z,C 2
FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ←Rd x Rr<<1 (UU) Z,C 2
FMULS Rd,Rr Fractional Multiply Signed R1:R0 ←Rd x Rr<<1 (SS) Z,C 2
FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ←Rd x Rr<<1 (SU) Z,C 2
DES K Data Encryption if (H = 0) then R15:R0
else if (H = 1) then R15:R0
←
←
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
1/2
Branch Instructions
RJMP k Relative Jump PC ←PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC(15:0)
PC(21:16)
←
←
Z,
0
None 2
EIJMP Extended Indirect Jump to (Z) PC(15:0)
PC(21:16)
←
←
Z,
EIND
None 2
JMP k Jump PC ←k None 3
RCALL k Relative Call Subroutine PC ←PC + k + 1 None 2 / 3(1)
ICALL Indirect Call to (Z) PC(15:0)
PC(21:16)
←
←
Z,
0
None 2 / 3(1)
EICALL Extended Indirect Call to (Z) PC(15:0)
PC(21:16)
←
←
Z,
EIND
None 3(1)
58
8068T–AVR–12/10
XMEGA A3
CALL k call Subroutine PC ←k None 3 / 4(1)
RET Subroutine Return PC ←STACK None 4 / 5(1)
RETI Interrupt Return PC ←STACK I 4 / 5(1)
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ←PC + 2 or 3 None 1 / 2 / 3
CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1
CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1
CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ←PC + 2 or 3 None 1 / 2 / 3
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ←PC + 2 or 3 None 1 / 2 / 3
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ←PC + 2 or 3 None 2 / 3 / 4
SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ←PC + 2 or 3 None 2 / 3 / 4
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC + k + 1 None 1 / 2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC + k + 1 None 1 / 2
BREQ k Branch if Equal if (Z = 1) then PC ←PC + k + 1 None 1 / 2
BRNE k Branch if Not Equal if (Z = 0) then PC ←PC + k + 1 None 1 / 2
BRCS k Branch if Carry Set if (C = 1) then PC ←PC + k + 1 None 1 / 2
BRCC k Branch if Carry Cleared if (C = 0) then PC ←PC + k + 1 None 1 / 2
BRSH k Branch if Same or Higher if (C = 0) then PC ←PC + k + 1 None 1 / 2
BRLO k Branch if Lower if (C = 1) then PC ←PC + k + 1 None 1 / 2
BRMI k Branch if Minus if (N = 1) then PC ←PC + k + 1 None 1 / 2
BRPL k Branch if Plus if (N = 0) then PC ←PC + k + 1 None 1 / 2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ←PC + k + 1 None 1 / 2
BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ←PC + k + 1 None 1 / 2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ←PC + k + 1 None 1 / 2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ←PC + k + 1 None 1 / 2
BRTS k Branch if T Flag Set if (T = 1) then PC ←PC + k + 1 None 1 / 2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ←PC + k + 1 None 1 / 2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ←PC + k + 1 None 1 / 2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ←PC + k + 1 None 1 / 2
BRIE k Branch if Interrupt Enabled if (I = 1) then PC ←PC + k + 1 None 1 / 2
BRID k Branch if Interrupt Disabled if (I = 0) then PC ←PC + k + 1 None 1 / 2
Data Transfer Instructions
MOV Rd, Rr Copy Register Rd ←Rr None 1
MOVWRd, Rr Copy Register Pair Rd+1:Rd ←Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd ←K None 1
LDS Rd, k Load Direct from data space Rd ←(k) None 2(1)(2)
LD Rd, X Load Indirect Rd ←(X) None 1(1)(2)
LD Rd, X+ Load Indirect and Post-Increment Rd
X
←
←
(X)
X + 1
None 1(1)(2)
LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1,
Rd ← (X)
←
←
X - 1
(X)
None 2(1)(2)
LD Rd, Y Load Indirect Rd ← (Y) ←(Y) None 1(1)(2)
LD Rd, Y+ Load Indirect and Post-Increment Rd
Y
←
←
(Y)
Y + 1
None 1(1)(2)
Mnemonics Operands Description Operation Flags #Clocks
59
8068T–AVR–12/10
XMEGA A3
LD Rd, -Y Load Indirect and Pre-Decrement Y
Rd
←
←
Y - 1
(Y)
None 2(1)(2)
LDD Rd, Y+q Load Indirect with Displacement Rd ←(Y + q) None 2(1)(2)
LD Rd, Z Load Indirect Rd ←(Z) None 1(1)(2)
LD Rd, Z+ Load Indirect and Post-Increment Rd
Z
←
←
(Z),
Z+1
None 1(1)(2)
LD Rd, -Z Load Indirect and Pre-Decrement Z
Rd
←
←
Z - 1,
(Z)
None 2(1)(2)
LDD Rd, Z+q Load Indirect with Displacement Rd ←(Z + q) None 2(1)(2)
STS k, Rr Store Direct to Data Space (k) ←Rd None 2(1)
ST X, Rr Store Indirect (X) ←Rr None 1(1)
ST X+, Rr Store Indirect and Post-Increment (X)
X
←
←
Rr,
X + 1
None 1(1)
ST -X, Rr Store Indirect and Pre-Decrement X
(X)
←
←
X - 1,
Rr
None 2(1)
ST Y, Rr Store Indirect (Y) ←Rr None 1(1)
ST Y+, Rr Store Indirect and Post-Increment (Y)
Y
←
←
Rr,
Y + 1
None 1(1)
ST -Y, Rr Store Indirect and Pre-Decrement Y
(Y)
←
←
Y - 1,
Rr
None 2(1)
STD Y+q, Rr Store Indirect with Displacement (Y + q) ←Rr None 2(1)
ST Z, Rr Store Indirect (Z) ←Rr None 1(1)
ST Z+, Rr Store Indirect and Post-Increment (Z)
Z
←
←
Rr
Z + 1
None 1(1)
ST -Z, Rr Store Indirect and Pre-Decrement Z ←Z - 1 None 2(1)
STD Z+q,Rr Store Indirect with Displacement (Z + q) ←Rr None 2(1)
LPM Load Program Memory R0 ←(Z) None 3
LPM Rd, Z Load Program Memory Rd ←(Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Increment Rd
Z
←
←
(Z),
Z + 1
None 3
ELPM Extended Load Program Memory R0 ←(RAMPZ:Z) None 3
ELPM Rd, Z Extended Load Program Memory Rd ←(RAMPZ:Z) None 3
ELPM Rd, Z+ Extended Load Program Memory and Post-
Increment
Rd
Z
←
←
(RAMPZ:Z),
Z + 1
None 3
SPM Store Program Memory (RAMPZ:Z) ←R1:R0 None -
SPM Z+ Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
←
←
R1:R0,
Z + 2
None -
IN Rd, A In From I/O Location Rd ←I/O(A) None 1
OUT A, Rr Out To I/O Location I/O(A) ←Rr None 1
PUSH Rr Push Register on Stack STACK ←Rr None 1(1)
POP Rd Pop Register from Stack Rd ←STACK None 2(1)
Bit and Bit-test Instructions
LSL Rd Logical Shift Left Rd(n+1)
Rd(0)
C
←
←
←
Rd(n),
0,
Rd(7)
Z,C,N,V,H 1
LSR Rd Logical Shift Right Rd(n)
Rd(7)
C
←
←
←
Rd(n+1),
0,
Rd(0)
Z,C,N,V 1
Mnemonics Operands Description Operation Flags #Clocks
60
8068T–AVR–12/10
XMEGA A3
Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid
for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
ROL Rd Rotate Left Through Carry Rd(0)
Rd(n+1)
C
←
←
←
C,
Rd(n),
Rd(7)
Z,C,N,V,H 1
ROR Rd Rotate Right Through Carry Rd(7)
Rd(n)
C
←
←
←
C,
Rd(n+1),
Rd(0)
Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ←Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0) ↔Rd(7..4) None 1
BSET s Flag Set SREG(s) ←1SREG(s)1
BCLR s Flag Clear SREG(s) ←0SREG(s)1
SBI A, b Set Bit in I/O Register I/O(A, b) ←1 None 1
CBI A, b Clear Bit in I/O Register I/O(A, b) ←0 None 1
BST Rr, b Bit Store from Register to T T ←Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ←T None 1
SEC Set Carry C ←1C1
CLC Clear Carry C ←0C1
SEN Set Negative Flag N ←1N1
CLN Clear Negative Flag N ←0N1
SEZ Set Zero Flag Z ←1Z1
CLZ Clear Zero Flag Z ←0Z1
SEI Global Interrupt Enable I ←1I1
CLI Global Interrupt Disable I ←0I1
SES Set Signed Test Flag S ←1S1
CLS Clear Signed Test Flag S ←0S1
SEV Set Two’s Complement Overflow V ←1V1
CLV Clear Two’s Complement Overflow V ←0V1
SET Set T in SREG T ←1T1
CLT Clear T in SREG T ←0T1
SEH Set Half Carry Flag in SREG H ←1H1
CLH Clear Half Carry Flag in SREG H ←0H1
MCU Control Instructions
BREAK Break (See specific descr. for BREAK) None 1
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep) None 1
WDR Watchdog Reset (see specific descr. for WDR) None 1
Mnemonics Operands Description Operation Flags #Clocks
61
8068T–AVR–12/10
XMEGA A3
33. Packaging information
33.1 64A
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) C
64A
2010-10-20
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1 A2 A
D1
D
e
E1 E
B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 15.75 16.00 16.25
D1 13.90 14.00 14.10 Note 2
E 15.75 16.00 16.25
E1 13.90 14.00 14.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
62
8068T–AVR–12/10
XMEGA A3
33.2 64M2
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
64M2, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, E
64M2
2010-10-20
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
A1 – 0.02 0.05
b
0.18 0.25 0.30
D
D2
7.50 7.65 7.80
8.90 9.00 9.10
8.90 9.00 9.10
E
E2
7.50 7.65 7.80
e
0.50 BSC
L 0.35 0.40
0.45
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D
E
Marked Pin# 1 ID
SEATING PLANE
A1
C
A
C
0.08
1
2
3
K0.20 0.27 0.40
2. Dimension and tolerance conform to ASMEY14.5M-1994.
0.20 REF
A3
A3
E2
D2
be
Pin #1 Corner
L
Pin #1
Triangle
Pin #1
Chamfer
(C 0.30)
Option A
Option B
Pin #1
Notch
(0.20 R)
Option C
K
K
Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
7.65 mm Exposed Pad, Micro Lead Frame Package (MLF)
63
8068T–AVR–12/10
XMEGA A3
34. Electrical Characteristics
All typical values are measured at T = 25°C unless other temperature condition is given. All min-
imum and maximum values are valid across operating temperature and voltage unless other
conditions are given.
34.1 Absolute Maximum Ratings*
34.2 DC Characteristics
Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin with respect to Ground..-0.5V to VCC+0.5V
Maximum Operating Voltage ............................................ 3.6V
DC Current per I/O Pin ............................................... 20.0 mA
DC Current VCC and GND Pins................................ 200.0 mA
Table 34-1. Current Consumption
Symbol Parameter Condition Min Typ Max Units
ICC
Power Supply Current(1)
Active 32 kHz, Ext. Clk VCC = 1.8V 25
µA
VCC = 3.0V 71
1 MHz, Ext. Clk VCC = 1.8V 317
VCC = 3.0V 697
2 MHz, Ext. Clk VCC = 1.8V 613 800
VCC = 3.0V 1340 1800
32 MHz, Ext. Clk VCC = 3.0V 15.7 18 mA
Idle 32 kHz, Ext. Clk VCC = 1.8V 3.6
µA
VCC = 3.0V 6.9
1 MHz, Ext. Clk VCC = 1.8V 112
VCC = 3.0V 215
2 MHz, Ext. Clk VCC = 1.8V 224 350
VCC = 3.0V 430 650
32 MHz, Ext. Clk VCC = 3.0V 6.9 8 mA
Power-down mode
All Functions Disabled, T = 25°C VCC = 3.0V 0.1 3
µA
All Functions Disabled, T = 85°C VCC = 3.0V 1.75 5
ULP, WDT, Sampled BOD, T = 25°C VCC = 1.8V 1 6
VCC = 3.0V 1 6
ULP, WDT, Sampled BOD, T=85°C VCC = 3.0V 2.7 10
64
8068T–AVR–12/10
XMEGA A3
Note: 1. All Power Reduction Registers set.
2. All parameters measured as the difference in current consumption between module enabled and disabled. All data at
VCC =3.0V, Clk
SYS = 1 MHz External clock with no prescaling.
ICC
Power-save mode
RTC 1 kHz from Low Power 32 kHz
TOSC, T = 25°C
VCC = 1.8V 0.5 4
µA
VCC = 3.0V 0.7 4
RTC from Low Power 32 kHz TOSC VCC = 3.0V 1.16
Reset Current
Consumption without Reset pull-up resistor current VCC = 3.0V 1300
Module current consumption(2)
ICC
RC32M 460
µA
RC32M w/DFLL Internal 32.768 kHz oscillator as DFLL source 594
RC2M 101
RC2M w/DFLL Internal 32.768 kHz oscillator as DFLL source 134
RC32K 27
PLL Multiplication factor = 10x 202
Watchdog normal mode 1
BOD Continuous mode 128
BOD Sampled mode 1
Internal 1.00 V ref 80
Temperature reference 74
RTC with int. 32 kHz RC as
source No prescaling 27
RTC with ULP as source No prescaling 1
ADC 250 kS/s - Int. 1V Ref 2.9
mA
DAC Normal Mode 1000 kS/s, Single channel, Int. 1V Ref 1.8
DAC Low-Power Mode 1000 KS/s, Single channel, Int. 1V Ref 0.95
DAC S/H Normal Mode Int.1.1V Ref, Refresh 16CLK 2.9
DAC Low-Power Mode S/H Int. 1.1V Ref, Refresh 16CLK 1.1
AC High-speed 195
µA
AC Low-power 103
USART Rx and Tx enabled, 9600 BAUD 5.4
DMA 128
Timer/Counter Prescaler DIV1 20
AES 223
Flash/EEPROM
Programming
Vcc = 2V 25 mA
Vcc = 3V 33
Table 34-1. Current Consumption (Continued)
Symbol Parameter Condition Min Typ Max Units
65
8068T–AVR–12/10
XMEGA A3
34.3 Operating Voltage and Frequency
The maximum CPU clock frequency of the XMEGA A3 devices is depending on VCC. As shown
in Figure 34-1 on page 65 the Frequency vs. VCC curve is linear between 1.8V < VCC <2.7V.
Figure 34-1. Maximum Frequency vs. Vcc
Table 34-2. Operating voltage and frequency
Symbol Parameter Condition Min Typ Max Units
ClkCPU CPU clock frequency
VCC = 1.6V 0 12
MHz
VCC = 1.8V 0 12
VCC = 2.7V 0 32
VCC = 3.6V 0 32
1.8
12
32
MHz
V
2.7 3.6
1.6
Safe Operating Area
66
8068T–AVR–12/10
XMEGA A3
34.4 Flash and EEPROM Memory Characteristics
Notes: 1. Programming is timed from the internal 2 MHz oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
Table 34-3. Endurance and Data Retention
Symbol Parameter Condition Min Typ Max Units
Flash
Write/Erase cycles 25°C 10K Cycle
85°C 10K
Data retention 25°C 100 Year
55°C 25
EEPROM
Write/Erase cycles 25°C 80K Cycle
85°C 30K
Data retention 25°C 100 Year
55°C 25
Table 34-4. Programming time
Symbol Parameter Condition Min Typ(1) Max Units
Chip Erase Flash, EEPROM(2) and SRAM Erase 40
ms
Flash
Page Erase 6
Page Write 6
Page WriteAutomatic Page Erase and Write 12
EEPROM
Page Erase 6
Page Write 6
Page WriteAutomatic Page Erase and Write 12
67
8068T–AVR–12/10
XMEGA A3
34.5 ADC Characteristics
Note: 1. Refer to ”Bandgap Characteristics” on page 68 for more parameter details.
Table 34-5. ADC Characteristics
Symbol Parameter Condition Min Typ Max Units
RES Resolution Programmable: 8/12 8 12 12 Bits
INL Integral Non-Linearity Differential mode, 500ksps -5 ±2 5 LSB
DNL Differential Non-Linearity Differential mode, 500ksps < ±1 LSB
Gain Error < ±10 mV
Offset Error < ±2 mV
ADCclk ADC Clock frequency Max is 1/4 of Peripheral Clock 2000 kHz
Conversion rate 2000 ksps
Conversion time
(propagation delay)
(RES+2)/2+GAIN
RES = 8 or 12, GAIN = 0, 1, 2 or 3 578
ADCclk
cycles
Sampling Time 1/2 ADCclk cycle 0.25 uS
Conversion range 0 VREF V
AVCC Analog Supply Voltage Vcc-0.3 Vcc+0.3 V
VREF Reference voltage 1.0 Vcc-0.6 V
Input bandwidth kHz
INT1V Internal 1.00V reference(1) 1.00 V
INTVCC Internal VCC/1.6 VCC/1.6 V
SCALEDVCC Scaled internal VCC/10 input VCC/10 V
RAREF Reference input resistance > 10 MΩ
Start-up time 12 24 ADCclk
cycles
Internal input sampling speed Temp. sensor, VCC/10, Bandgap 100 ksps
Table 34-6. ADC Gain Stage Characteristics
Symbol Parameter Condition Min Typ Max Units
Gain error 1 to 64 gain < ±1 %
Offset error < ±1
mV
Vrms Noise level at input 64x gain VREF = Int. 1V 0.12
VREF = Ext. 2V 0.06
Clock rate Same as ADC 1000 kHz
68
8068T–AVR–12/10
XMEGA A3
34.6 DAC Characteristics
34.7 Analog Comparator Characteristics
34.8 Bandgap Characteristics
Table 34-7. DAC Characteristics
Symbol Parameter Condition Min Typ Max Units
INL Integral Non-Linearity VCC = 1.6-3.6V VREF = Ext. ref 5
LSB
DNL Differential Non-Linearity VCC = 1.6-3.6V VREF = Ext. ref <±1
VREF= AVCC
Fclk Conversion rate 1000 ksps
AREF External reference voltage 1.1 AVCC-0.6 V
Reference input impedance >10 MΩ
Max output voltage Rload=100kΩAVCC*0.98
V
Min output voltage Rload=100kΩ0.015
Offset factory calibration accuracy Continues mode, VCC=3.0V,
VREF = Int 1.00V, T=85°C
±0.5 LSB
Gain factory calibration accuracy ±2.5
Table 34-8. Analog Comparator Characteristics
Symbol Parameter Condition Min Typ Max Units
Voff Input Offset Voltage VCC = 1.6 - 3.6V <±10 mV
Ilk Input Leakage Current VCC = 1.6 - 3.6V < 1000 pA
Vhys1 Hysteresis, No VCC = 1.6 - 3.6V 0
mVVhys2 Hysteresis, Small VCC = 1.6 - 3.6V mode = HS 20
Vhys3 Hysteresis, Large VCC = 1.6 - 3.6V mode = HS 40
tdelay Propagation delay
VCC = 3.0V, T= 85°C mode = HS 100
nsVCC = 1.6 - 3.6V mode = HS 110
VCC = 1.6 - 3.6V mode = LP 175
Table 34-9. Bandgap Voltage Characteristics
Symbol Parameter Condition Min Typ Max Units
Bandgap startup time As reference for ADC or DAC 1 Clk_PER + 2.5µs µs
As input to AC or ADC 1.5
Bandgap voltage 1.1 V
INT1V Internal 1.00V reference T= 85°C, After calibration 0.99 1 1.01
Variation over voltage and temperature VCC = 1.6 - 3.6V, T = -40°C to 85°C±2 %
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34.9 Brownout Detection Characteristics
Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
34.10 PAD Characteristics
Table 34-10. Brownout Detection Characteristics(1)
Symbol Parameter Condition Min Typ Max Units
BOD level 0 falling Vcc 1.62 1.63 1.7
V
BOD level 1 falling Vcc 1.9
BOD level 2 falling Vcc 2.17
BOD level 3 falling Vcc 2.43
BOD level 4 falling Vcc 2.68
BOD level 5 falling Vcc 2.96
BOD level 6 falling Vcc 3.22
BOD level 7 falling Vcc 3.49
Hysteresis BOD level 0-5 1 %
Table 34-11. PAD Characteristics
Symbol Parameter Condition Min Typ Max Units
VIH Input High Voltage VCC = 2.4 - 3.6V 0.7*VCC VCC+0.5
V
VCC = 1.6 - 2.4V 0.8*VCC VCC+0.5
VIL Input Low Voltage VCC = 2.4 - 3.6V -0.5 0.3*VCC
VCC = 1.6 - 2.4V -0.5 0.2*VCC
VOL Output Low Voltage GPIO
IOH = 15 mA, VCC = 3.3V 0.4 0.76
IOH = 10 mA, VCC = 3.0V 0.3 0.64
IOH = 5 mA, VCC = 1.8V 0.2 0.46
VOH Output High Voltage GPIO
IOH = -8 mA, VCC = 3.3V 2.6 2.9
IOH = -6 mA, VCC = 3.0V 2.1 2.7
IOH = -2 mA, VCC = 1.8V 1.4 1.6
IIL Input Leakage Current I/O pin <0.001 1 µA
IIH Input Leakage Current I/O pin <0.001 1
RPI/O pin Pull/Buss keeper Resistor 20 kΩ
RRST Reset pin Pull-up Resistor 20
Input hysteresis 0.5 V
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34.11 POR Characteristics
34.12 Reset Characteristics
34.13 Oscillator Characteristics
Table 34-12. Power-on Reset Characteristics
Symbol Parameter Condition Min Typ Max Units
VPOT- POR threshold voltage falling VCC
VCC falls faster than 1V/ms 0.4 0.8
VCC falls at 1V/ms or slower 0.8 1.3 V
VPOT+ POR threshold voltage rising VCC 1.3 1.59
Table 34-13. Reset Characteristics
Symbol Parameter Condition Min Typ Max Units
Minimum reset pulse width 90 1000 ns
Reset threshold voltage VCC = 2.7 - 3.6V 0.45*VCC V
VCC = 1.6 - 2.7V 0.42*VCC
Table 34-14. Internal 32.768 kHz Oscillator Characteristics
Symbol Parameter Condition Min Typ Max Units
Accuracy T = 85°C, VCC = 3V,
After production calibration -0.5 0.5 %
Table 34-15. Internal 2 MHz Oscillator Characteristics
Symbol Parameter Condition Min Typ Max Units
Accuracy T = 85°C, VCC = 3V,
After production calibration -1.5 1.5 %
DFLL Calibration step size T = 25°C, VCC = 3V 0.15
Table 34-16. Internal 32 MHz Oscillator Characteristics
Symbol Parameter Condition Min Typ Max Units
Accuracy T = 85°C, VCC = 3V,
After production calibration -1.5 1.5 %
DFLL Calibration stepsize T = 25°C, VCC = 3V 0.2
Table 34-17. Internal 32 kHz, ULP Oscillator Characteristics
Symbol Parameter Condition Min Typ Max Units
Output frequency 32 kHz ULP OSC T = 85°C, VCC = 3.0V 26 kHz
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Note: 1. See Figure 34-2 on page 71 for definition
Figure 34-2. TOSC input capacitance
The input capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal
when oscillating without external capacitors.
Notes: 1. Non-prescaled System Clock source.
2. Time from pin change on external interrupt pin to first available clock cycle. Additional interrupt response time is minimum 5
system clock source cycles.
Table 34-18. External 32.768kHz Crystal Oscillator and TOSC characteristics
Symbol Parameter Condition Min Typ Max Units
SF Safety factor Capacitive load matched to crystal
specification 3
ESR/R1
Recommended crystal equivalent
series resistance (ESR)
Crystal load capacitance 6.5pF 60 kΩ
Crystal load capacitance 9.0pF 35
CIN_TOSC
Input capacitance between TOSC
pins
Normal mode 1.7 pF
Low power mode 2.2
CL1 CL2
TOSC1 TOSC2
Device internal
External
32.768 KHz crystal
Table 34-19. Device wake-up time from sleep
Symbol Parameter Condition(1) Min Typ(2) Max Units
Idle Sleep, Standby and Extended
Standby sleep mode
Int. 32.768 kHz RC 130
µS
Int. 2 MHz RC 2
Ext. 2 MHz Clock 2
Int. 32 MHz RC 0.17
Power-save and Power-down Sleep
mode
Int. 32.768 kHz RC 320
Int. 2 MHz RC 10.3
Ext. 2 MHz Clock 4.5
Int. 32 MHz RC 5.8
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35. Typical Characteristics
35.1 Active Supply Current
Figure 35-1. Active Supply Current vs. Frequency
fSYS = 0 - 1.0 MHz External clock, T = 25°C
Figure 35-2. Active Supply Current vs. Frequency
fSYS = 1 - 32 MHz External clock, T = 25°C
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
0
100
200
300
400
500
600
700
800
900
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.9 1
Frequency [MHz]
ICC [uA]
3.3 V
3.0 V
2.7 V
0
2
4
6
8
10
12
14
16
18
20
04812 16 20 24 2832
Frequency [MHz]
ICC [mA]
2.2 V
1.8 V
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Figure 35-3. Active Supply Current vs. Vcc
fSYS = 1.0 MHz External Clock
Figure 35-4. Active Supply Current vs. VCC
fSYS = 32.768 kHz internal RC
85 °C
25 °C
-40 °C
0
100
200
300
400
500
600
700
800
900
1000
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
ICC [uA]
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
ICC [uA]
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Figure 35-5. Active Supply Current vs. Vcc
fSYS = 2.0 MHz internal RC
Figure 35-6. Active Supply Current vs. Vcc
fSYS = 32 MHz internal RC prescaled to 8 MHz
85 °C
25 °C
-40 °C
0
200
400
600
800
1000
1200
1400
1600
1800
2000
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
ICC [uA]
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
7
8
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
ICC [mA]
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Figure 35-7. Active Supply Current vs. Vcc
fSYS = 32 MHz internal RC
35.2 Idle Supply Current
Figure 35-8. Idle Supply Current vs. Frequency
fSYS = 0 - 1.0 MHz, T = 25°C
85 °C
25 °C
-40 °C
0
5
10
15
20
25
2.7 2.82.9 3 3.1 3.2 3.3 3.4 3.5 3.6
VCC [V]
ICC [mA]
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
0
50
100
150
200
250
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.9 1
Frequency [MHz]
ICC [uA]
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Figure 35-9. Idle Supply Current vs. Frequency
fSYS = 1 - 32 MHz, T = 25°C
Figure 35-10. Idle Supply Current vs. Vcc
fSYS = 1.0 MHz External Clock
3.3 V
3.0 V
2.7 V
0
1
2
3
4
5
6
7
8
04812 16 20 24 2832
Frequency [MHz]
ICC [mA]
1.8 V
2.2 V
85 °C
25 °C
-40 °C
0
50
100
150
200
250
300
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
ICC [uA]
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Figure 35-11. Idle Supply Current vs. Vcc
fSYS = 32.768 kHz internal RC
Figure 35-12. Idle Supply Current vs. Vcc
fSYS = 2.0 MHz internal RC
85 °C
25 °C
-40 °C
0
5
10
15
20
25
30
35
40
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
ICC [uA]
85 °C
25 °C
-40 °C
0
100
200
300
400
500
600
700
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
ICC [uA]
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Figure 35-13. Idle Supply Current vs. Vcc
fSYS = 32 MHz internal RC prescaled to 8 MHz
Figure 35-14. Idle Supply Current vs. Vcc
fSYS = 32 MHz internal RC
85 °C
25 °C
-40 °C
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
ICC [mA]
85 °C
25 °C
-40 °C
0
2
4
6
8
10
2.7 2.82.9 3 3.1 3.2 3.3 3.4 3.5 3.6
VCC [V]
ICC [mA]
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35.3 Power-down Supply Current
Figure 35-15. Power-down Supply Current vs. Temperature
Figure 35-16. Power-down Supply Current vs. Temperature
With WDT and sampled BOD enabled.
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090
Temperature [°C]
ICC [uA]
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
0
0.5
1
1.5
2
2.5
3
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090
Temperature [°C]
ICC [uA]
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35.4 Power-save Supply Current
Figure 35-17. Power-save Supply Current vs. Temperature
With WDT, sampled BOD and RTC from ULP enabled
35.5 Pin Pull-up
Figure 35-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
0
0.5
1
1.5
2
2.5
3
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090
Temperature [°C]
ICC [uA]
85 °C
25 °C
-40 °C
0
20
40
60
80
100
0 0.2 0.4 0.6 0.81 1.2 1.4 1.6 1.8
VRESET [V]
IRESET [uA]
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Figure 35-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
Figure 35-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
160
0 0.5 1 1.5 2 2.5 3
VRESET [V]
IRESET [uA]
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
160
180
0 0.5 1 1.5 2 2.5 3
VRESET [V]
IRESET [uA]
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35.6 Pin Output Voltage vs. Sink/Source Current
Figure 35-21. I/O Pin Output Voltage vs. Source Current
Vcc = 1.8V
Figure 35-22. I/O Pin Output Voltage vs. Source Current
Vcc = 3.0V
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-12 -10 -8-6 -4 -2 0
IPIN [mA]
VPIN [V]
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
3.5
-20 -18-16 -14 -12 -10 -8-6 -4 -2 0
IPIN [mA]
VPIN [V]
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Figure 35-23. I/O Pin Output Voltage vs. Source Current
Vcc = 3.3V
Figure 35-24. I/O Pin Output Voltage vs. Sink Current
Vcc = 1.8V
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
3.5
-20 -18-16 -14 -12 -10 -8-6 -4 -2 0
IPIN [mA]
VPIN [V]
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0246810 12 14 16 1820
IPIN [mA]
VPIN [V]
25°C85°C
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Figure 35-25. I/O Pin Output Voltage vs. Sink Current
Vcc = 3.0V
Figure 35-26. I/O Pin Output Voltage vs. Sink Current
Vcc = 3.3V
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0246810 12 14 16 1820
IPIN [mA]
VPIN [V]
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0246810 12 14 16 1820
IPIN [mA]
VPIN [V]
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35.7 Pin Thresholds and Hysteresis
Figure 35-27. I/O Pin Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as “1”
Figure 35-28. I/O Pin Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as “0”
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
Vthreshold [V]
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
Vthreshold [V]
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Figure 35-29. I/O Pin Input Hysteresis vs. VCC
Figure 35-30. Reset Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as “1”
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
Vthreshold [V]
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
VTHRESHOLD [V]
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Figure 35-31. Reset Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as “0”
35.8 Bod Thresholds
Figure 35-32. BOD Thresholds vs. Temperature
BOD Level = 1.6V
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
VTHRESHOLD [V]
Rising Vcc
Falling Vcc
1.61
1.62
1.63
1.64
1.65
1.66
1.67
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090
Temperature [°C]
VBOT [V]
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Figure 35-33. BOD Thresholds vs. Temperature
BOD Level = 2.9V
35.9 Oscillators and Wake-up Time
35.9.1 Internal 32.768 kHz Oscillator
Figure 35-34. Internal 32.768 kHz Oscillator Calibration Step Size
T = -40 to 85
°
C, VCC = 3V
Rising Vcc
Falling Vcc
2.9
2.92
2.94
2.96
2.98
3
3.02
3.04
3.06
-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090
Temperature [°C]
VBOT [V]
0326496128160 192 224 256
RC32KCAL[7..0]
0.05 %
0.20 %
0.35 %
0.50 %
0.65 %
0.80 %
Step size: f [kHz]
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35.9.2 Internal 2 MHz Oscillator
Figure 35-35. Internal 2 MHz Oscillator CALA Calibration Step Size
T = -40 to 85
°
C, VCC = 3V
Figure 35-36. Internal 2 MHz Oscillator CALB Calibration Step Size
T = -40 to 85
°
C, VCC = 3V
-0.30 %
-0.20 %
-0.10 %
0.00 %
0.10 %
0.20 %
0.30 %
0.40 %
0.50 %
016324864 8096112128
DFLLRC2MCALA
Step size: f [MHz]
0.00 %
0.50 %
1.00 %
1.50 %
2.00 %
2.50 %
3.00 %
0816 24 32 40 4856 64
DFLLRC2MCALB
Step size: f [MHz]
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35.9.3 Internal 32 MHZ Oscillator
Figure 35-37. Internal 32 MHz Oscillator CALA Calibration Step Size
T = -40 to 85
°
C, VCC = 3V
Figure 35-38. Internal 32 MHz Oscillator CALB Calibration Step Size
T = -40 to 85
°
C, VCC = 3V
-0.20 %
-0.10 %
0.00 %
0.10 %
0.20 %
0.30 %
0.40 %
0.50 %
0.60 %
016324864 80 96 112 128
DFLLRC32MCALA
Step size: f [MHz]
0.00 %
0.50 %
1.00 %
1.50 %
2.00 %
2.50 %
3.00 %
0816 24 32 40 4856 64
DFLLRC32MCALB
Step size: f [MHz]
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35.10 Module current consumption
Figure 35-39. AC current consumption vs. Vcc
Low-power Mode
Figure 35-40. Power-up current consumption vs. Vcc
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
Module current consumption [uA]
85 °C
25 °C
-40 °C
0
100
200
300
400
500
600
700
0.4 0.6 0.81 1.2 1.4 1.6
VCC [V]
ICC [uA]
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35.11 Reset Pulsewidth
Figure 35-41. Minimum Reset Pulse Width vs. Vcc
35.12 PDI Speed
Figure 35-42. PDI Speed vs. Vcc
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
tRST [ns]
25 °C
0
5
10
15
20
25
30
35
1.6 1.82 2.2 2.4 2.6 2.83 3.2 3.4 3.6
VCC [V]
fMAX [MHz]
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36. Errata
36.1 ATxmega256A3
36.1.1 rev. E
•Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
•VCC voltage scaler for AC is non-linear
•ADC has increased INL error for some operating conditions
•ADC gain stage output range is limited to 2.4 V
•ADC Event on compare match non-functional
•Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
•Accuracy lost on first three samples after switching input to ADC gain stage
•Configuration of PGM and CWCM not as described in XMEGA A Manual
•PWM is not restarted properly after a fault in cycle-by-cycle mode
•BOD will be enabled at any reset
•DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
•DAC has increased INL or noise for some operating conditions
•DAC refresh may be blocked in S/H mode
•Conversion lost on DAC channel B in event triggered mode
•EEPROM page buffer always written when NVM DATA0 is written
•Pending full asynchronous pin change interrupts will not wake the device
•Pin configuration does not affect Analog Comparator Output
•NMI Flag for Crystal Oscillator Failure automatically cleared
•Crystal start-up time required after power-save even if crystal is source for RTC
•RTC Counter value not correctly read after sleep
•Pending asynchronous RTC-interrupts will not wake up device
•TWI Transmit collision flag not cleared on repeated start
•Clearing TWI Stop Interrupt Flag may lock the bus
•TWI START condition at bus timeout will cause transaction to be dropped
•TWI Data Interrupt Flag (DIF) erroneously read as set
•WDR instruction inside closed window will not issue reset
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for another AC, the first comparator will be affected for up to
1 µs and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
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Figure 36-1. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/Workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed
3. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
– 6LSB for sample rates above 1Msps, and up to 8 LSB for 2Msps sample rate.
– 6LSB for reference voltage below 1.1V when VCC is above 3.0V.
– 20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/Workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL
error. Use the ADC in signed mode also for single ended measurements.
4. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
– 1x gain: 2.4 V
– 2x gain: 1.2 V
– 4x gain: 0.6 V
– 8x gain: 300 mV
– 16x gain: 150 mV
– 32x gain: 75 mV
– 64x gain: 38 mV
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
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Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
5. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INT-
MODE) is set to BELOW or ABOVE.
Problem fix/Workaround
Enable and use interrupt on compare match when using the compare function.
6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
None.
7. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input
channel must be disregarded to achieve 12-bit accuracy.
Problem fix/Workaround
Run three ADC conversions and discard these results after changing input channels to ADC
gain stage.
8. Configuration of PGM and CWCM not as described in XMEGA A Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM),
but not Common Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode
(CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode.
Problem fix/Workaround
9. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not
return to normal operation at first update after fault condition is no longer present.
Problem fix/Workaround
Do a write to any AWeX I/O register to re-enable the output.
10. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Table 36-1. Configure PWM and CWCM according to this table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
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XMEGA A3
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate out-
put when converting codes that give below 0.75V output:
– ±10 LSB for continuous mode
– ±200 LSB for Sample and Hold mode
Problem fix/Workaround
None.
12. DAC has increased INL or noise for some operating conditions
Some DAC configurations or operating condition will result in increased output error.
– Continous mode: ±5 LSB
– Sample and hold mode: ±15 LSB
– Sample and hold mode for reference above 2.0v: up to ±100 LSB
Problem fix/Workaround
None.
13. DAC refresh may be blocked in S/H mode
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workaround
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
14. Conversion lost on DAC channel B in event triggered mode
If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1
conversions are occasionally lost. This means that not all data-values written to the
Channel 1 data register are converted.
Problem fix/Workaround
Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Periph-
eral clock frequency so the conversion internal never is shorter than 1.5 µs.
15. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
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16. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the
sleep instruction is executed, will be ignored until the device is woken from another source
or the source triggers again. This applies when entering all sleep modes where the System
Clock is stopped.
Problem fix/Workaround
None.
17. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator
output.
Problem fix/Workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect
positive input to the negative AC input and vice versa), or use and external inverter to
change polarity of Analog Comparator output.
18. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when exe-
cuting the NMI interrupt handler.
Problem fix/Workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in
software is not required.
19. Crystal start-up time required after power-save even if crystal is source for RTC
Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be
ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscilla-
tor Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during
this period (0.5s).
Problem fix/Workaround
If faster start-up is required, go to sleep with internal oscillator as system clock.
20. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to
bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not
be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will
be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
21. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
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XMEGA A3
22. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
23. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the
hardware sets this flag due to a new address received, CLKHOLD is not cleared and the
SCL line is not released. This will lock the bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is
not IDLE, wait for the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
24. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
Problem fix/Workaround
None.
25. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
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XMEGA A3
26. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window
control register, the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
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XMEGA A3
36.1.2 rev. B
•Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
•VCC voltage scaler for AC is non-linear
•ADC has increased INL error for some operating conditions
•ADC gain stage output range is limited to 2.4 V
•ADC Event on compare match non-functional
•Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
•Accuracy lost on first three samples after switching input to ADC gain stage
•Configuration of PGM and CWCM not as described in XMEGA A Manual
•PWM is not restarted properly after a fault in cycle-by-cycle mode
•BOD will be enabled at any reset
•DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
•DAC has increased INL or noise for some operating conditions
•DAC refresh may be blocked in S/H mode
•Conversion lost on DAC channel B in event triggered mode
•EEPROM page buffer always written when NVM DATA0 is written
•Pending full asynchronous pin change interrupts will not wake the device
•Pin configuration does not affect Analog Comparator Output
•NMI Flag for Crystal Oscillator Failure automatically cleared
•Writing EEPROM or Flash while reading any of them will not work
•Crystal start-up time required after power-save even if crystal is source for RTC
•RTC Counter value not correctly read after sleep
•Pending asynchronous RTC-interrupts will not wake up device
•TWI Transmit collision flag not cleared on repeated start
•Clearing TWI Stop Interrupt Flag may lock the bus
•TWI START condition at bus timeout will cause transaction to be dropped
•TWI Data Interrupt Flag (DIF) erroneously read as set
•WDR instruction inside closed window will not issue reset
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for another AC, the first comparator will be affected for up to
1 µs and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
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XMEGA A3
Figure 36-2. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/Workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed
3. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
– 6LSB for sample rates above 1Msps, and up to 8LSB for 2Msps sample rate.
– 6LSB for reference voltage below 1.1V when VCC is above 3.0V.
– 20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/Workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL
error. Use the ADC in signed mode also for single ended measurements.
4. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
– 1x gain: 2.4 V
– 2x gain: 1.2 V
– 4x gain: 0.6 V
– 8x gain: 300 mV
– 16x gain: 150 mV
– 32x gain: 75 mV
– 64x gain: 38 mV
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
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XMEGA A3
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
5. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INT-
MODE) is set to BELOW or ABOVE.
Problem fix/Workaround
Enable and use interrupt on compare match when using the compare function.
6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
None.
7. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input
channel must be disregarded to achieve 12-bit accuracy.
Problem fix/Workaround
Run three ADC conversions and discard these results after changing input channels to ADC
gain stage.
8. Configuration of PGM and CWCM not as described in XMEGA A Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM),
but not Common Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode
(CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode.
Problem fix/Workaround
9. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not
return to normal operation at first update after fault condition is no longer present.
Problem fix/Workaround
Do a write to any AWeX I/O register to re-enable the output.
10. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Table 36-2. Configure PWM and CWCM according to this table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
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XMEGA A3
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate out-
put when converting codes that give below 0.75V output:
– ±10 LSB for continuous mode
– ±200 LSB for Sample and Hold mode
Problem fix/Workaround
None.
12. DAC has increased INL or noise for some operating conditions
Some DAC configurations or operating condition will result in increased output error.
– Continous mode: ±5 LSB
– Sample and hold mode: ±15 LSB
– Sample and hold mode for reference above 2.0v: up to ±100 LSB
Problem fix/Workaround
None.
13. DAC refresh may be blocked in S/H mode
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workaround
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
14. Conversion lost on DAC channel B in event triggered mode
If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1
conversions are occasionally lost. This means that not all data-values written to the
Channel 1 data register are converted.
Problem fix/Workaround
Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Periph-
eral clock frequency so the conversion internal never is shorter than 1.5 µs.
15. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
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XMEGA A3
16. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the
sleep instruction is executed, will be ignored until the device is woken from another source
or the source triggers again. This applies when entering all sleep modes where the System
Clock is stopped.
Problem fix/Workaround
None.
17. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator
output.
Problem fix/Workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect
positive input to the negative AC input and vice versa), or use and external inverter to
change polarity of Analog Comparator output.
18. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when exe-
cuting the NMI interrupt handler.
Problem fix/Workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in
software is not required.
19. Writing EEPROM or Flash while reading any of them will not work
The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while exe-
cuting code in Active mode.
Problem fix/Workaround
Enter IDLE sleep mode within 2.5 µs (Five 2 MHz clock cycles and 80 32 MHz clock cycles)
after starting an EEPROM or flash write operation. Wake-up source must either be
EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an
overflow interrupt 7 ms after the erase or write operation has started, or 13 ms after atomic
erase-and-write operation has started, and then enter IDLE sleep mode.
20. Crystal start-up time required after power-save even if crystal is source for RTC
Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be
ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscilla-
tor Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during
this period (0.5s).
Problem fix/Workaround
If faster start-up is required, go to sleep with internal oscillator as system clock.
21. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to
bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not
be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will
be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
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XMEGA A3
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
22. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
23. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
24. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the
hardware sets this flag due to a new address received, CLKHOLD is not cleared and the
SCL line is not released. This will lock the bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is
not IDLE, wait for the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
25. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
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XMEGA A3
Problem fix/Workaround
None.
26. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
27. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window
control register, the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
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XMEGA A3
36.1.3 rev. A
•Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
•ADC gain stage output range is limited to 2.4V
•Sampled BOD in Active mode will cause noise when bandgap is used as reference
•Flash Power Reduction Mode can not be enabled when entering sleep mode
•JTAG enable does not override Analog Comparator B output
•Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
•DAC refresh may be blocked in S/H mode
•BOD will be enabled after any reset
•Both DFLLs and both oscillators has to be enabled for one to work
•Operating frequency and voltage limitations
•Inverted I/O enable does not affect Analog Comparator Output
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for the another AC, the first comparator will be affected for up
to 1 us and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
2. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
3. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add
noise on the bandgap reference for ADC, DAC and Analog Comparator.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the
BOD must not be set in sampled mode.
– 1x gain: 2.4 V
– 2x gain: 1.2 V
– 4x gain: 0.6 V
– 8x gain: 300 mV
– 16x gain: 150 mV
– 32x gain: 75 mV
– 64x gain: 38 mV
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XMEGA A3
4. Flash Power Reduction Mode can not be enabled when entering sleep mode
If Flash Power Reduction Mode is enabled when a deep sleep mode, the device will only
wake up on every fourth wake-up request.
If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time
will vary with up to 16 CPU clock cycles.
Problem fix/Workaround
Disable Flash Power Reduction mode before entering sleep mode.
5. JTAG enable does not override Analog Comparator B output
When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT
on pin 7 if this is enabled.
Problem fix/Workaround
AC0OUT for ACB should not be enabled when JTAG is used. Use only analog comparator
output for ACA when JTAG is used, or use the PDI as debug interface.
6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC cannot be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
If internal voltages must be measured when VCC is below 2.7V, measure the internal 1.00V
reference instead of the bandgap.
7. DAC refresh may be blocked in S/H mode
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workarund
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
8. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
9. Both DFLLs and both oscillators has to be enabled for one to work
In order to use the automatic runtime calibration for the 2 MHz or the 32MHz internal oscilla-
tors, the DFLL for both oscillators and both oscillators has to be enabled for one to work.
Problem fix/Workaround
Enable both the DFLLs and both oscillators when using automatic runtime calibration for
one of the internal oscillators.
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XMEGA A3
10. Operating Frequency and Voltage Limitation
To ensure correct operation, there is a limit on operating frequency and voltage. Figure 36-3
on page 109 shows the safe operating area.
Figure 36-3. Operating Frequnecy and Voltage Limitation
Problem fix/Workaround
None, avoid using the device outside these frequnecy and voltage limitations.
11. Inverted I/O enable does not affect Analog Comparator Output
The inverted I/O pin function does not affect the Analog Comparator output function.
Problem fix/Workarund
Configure the analog comparator setup to give a inverted result (i.e. connect positive input to
the negative AC input and vice versa), or use and externel inverter to change polarity of
Analog Comparator Output.
MHz
V
3.6
2.4
30
15 Safe operating
area
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XMEGA A3
36.2 ATxmega192A3, ATxmega128A3, ATxmega64A3
36.2.1 rev. E
•Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
•VCC voltage scaler for AC is non-linear
•ADC has increased INL error for some operating conditions
•ADC gain stage output range is limited to 2.4 V
•ADC Event on compare match non-functional
•Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
•Accuracy lost on first three samples after switching input to ADC gain stage
•Configuration of PGM and CWCM not as described in XMEGA A Manual
•PWM is not restarted properly after a fault in cycle-by-cycle mode
•BOD will be enabled at any reset
•DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
•DAC has increased INL or noise for some operating conditions
•DAC refresh may be blocked in S/H mode
•Conversion lost on DAC channel B in event triggered mode
•EEPROM page buffer always written when NVM DATA0 is written
•Pending full asynchronous pin change interrupts will not wake the device
•Pin configuration does not affect Analog Comparator Output
•NMI Flag for Crystal Oscillator Failure automatically cleared
•Crystal start-up time required after power-save even if crystal is source for RTC
•RTC Counter value not correctly read after sleep
•Pending asynchronous RTC-interrupts will not wake up device
•TWI Transmit collision flag not cleared on repeated start
•Clearing TWI Stop Interrupt Flag may lock the bus
•TWI START condition at bus timeout will cause transaction to be dropped
•TWI Data Interrupt Flag (DIF) erroneously read as set
•WDR instruction inside closed window will not issue reset
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for another AC, the first comparator will be affected for up to
1 µs and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
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Figure 36-4. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/Workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed
3. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
– 6LSB for sample rates above 1Msps, and up to 8 LSB for 2Msps sample rate.
– 6LSB for reference voltage below 1.1V when VCC is above 3.0V.
– 20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/Workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL
error. Use the ADC in signed mode also for single ended measurements.
4. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
– 1x gain: 2.4 V
– 2x gain: 1.2 V
– 4x gain: 0.6 V
– 8x gain: 300 mV
– 16x gain: 150 mV
– 32x gain: 75 mV
– 64x gain: 38 mV
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
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Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
5. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INT-
MODE) is set to BELOW or ABOVE.
Problem fix/Workaround
Enable and use interrupt on compare match when using the compare function.
6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
None.
7. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input
channel must be disregarded to achieve 12-bit accuracy.
Problem fix/Workaround
Run three ADC conversions and discard these results after changing input channels to ADC
gain stage.
8. Configuration of PGM and CWCM not as described in XMEGA A Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM),
but not Common Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode
(CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode.
Problem fix/Workaround
9. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not
return to normal operation at first update after fault condition is no longer present.
Problem fix/Workaround
Do a write to any AWeX I/O register to re-enable the output.
10. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Table 36-3. Configure PWM and CWCM according to this table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
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Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate out-
put when converting codes that give below 0.75V output:
– ±10 LSB for continuous mode
– ±200 LSB for Sample and Hold mode
Problem fix/Workaround
None.
12. DAC has increased INL or noise for some operating conditions
Some DAC configurations or operating condition will result in increased output error.
– Continous mode: ±5 LSB
– Sample and hold mode: ±15 LSB
– Sample and hold mode for reference above 2.0v: up to ±100 LSB
Problem fix/Workaround
None.
13. DAC refresh may be blocked in S/H mode
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workaround
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
14. Conversion lost on DAC channel B in event triggered mode
If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1
conversions are occasionally lost. This means that not all data-values written to the
Channel 1 data register are converted.
Problem fix/Workaround
Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Periph-
eral clock frequency so the conversion internal never is shorter than 1.5 µs.
15. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
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16. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the
sleep instruction is executed, will be ignored until the device is woken from another source
or the source triggers again. This applies when entering all sleep modes where the System
Clock is stopped.
Problem fix/Workaround
None.
17. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator
output.
Problem fix/Workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect
positive input to the negative AC input and vice versa), or use and external inverter to
change polarity of Analog Comparator output.
18. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when exe-
cuting the NMI interrupt handler.
Problem fix/Workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in
software is not required.
19. Crystal start-up time required after power-save even if crystal is source for RTC
Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be
ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscilla-
tor Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during
this period (0.5s).
Problem fix/Workaround
If faster start-up is required, go to sleep with internal oscillator as system clock.
20. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to
bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not
be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will
be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
21. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
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22. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
23. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the
hardware sets this flag due to a new address received, CLKHOLD is not cleared and the
SCL line is not released. This will lock the bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is
not IDLE, wait for the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
24. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
Problem fix/Workaround
None.
25. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
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26. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window
control register, the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
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36.2.2 rev. B
•Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
•VCC voltage scaler for AC is non-linear
•ADC has increased INL error for some operating conditions
•ADC gain stage output range is limited to 2.4 V
•ADC Event on compare match non-functional
•Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
•Accuracy lost on first three samples after switching input to ADC gain stage
•Configuration of PGM and CWCM not as described in XMEGA A Manual
•PWM is not restarted properly after a fault in cycle-by-cycle mode
•BOD will be enabled at any reset
•DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
•DAC has increased INL or noise for some operating conditions
•DAC refresh may be blocked in S/H mode
•Conversion lost on DAC channel B in event triggered mode
•EEPROM page buffer always written when NVM DATA0 is written
•Pending full asynchronous pin change interrupts will not wake the device
•Pin configuration does not affect Analog Comparator Output
•NMI Flag for Crystal Oscillator Failure automatically cleared
•Writing EEPROM or Flash while reading any of them will not work
•Crystal start-up time required after power-save even if crystal is source for RTC
•RTC Counter value not correctly read after sleep
•Pending asynchronous RTC-interrupts will not wake up device
•TWI Transmit collision flag not cleared on repeated start
•Clearing TWI Stop Interrupt Flag may lock the bus
•TWI START condition at bus timeout will cause transaction to be dropped
•TWI Data Interrupt Flag (DIF) erroneously read as set
•WDR instruction inside closed window will not issue reset
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for another AC, the first comparator will be affected for up to
1 µs and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
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Figure 36-5. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/Workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed
3. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In signed mode INL is increased to:
– 6LSB for sample rates above 1Msps, and up to 8 LSB for 2Msps sample rate.
– 6LSB for reference voltage below 1.1V when VCC is above 3.0V.
– 20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.
In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used.
Problem fix/Workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL
error. Use the ADC in signed mode also for single ended measurements.
4. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
– 1x gain: 2.4 V
– 2x gain: 1.2 V
– 4x gain: 0.6 V
– 8x gain: 300 mV
– 16x gain: 150 mV
– 32x gain: 75 mV
– 64x gain: 38 mV
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V]
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Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
5. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INT-
MODE) is set to BELOW or ABOVE.
Problem fix/Workaround
Enable and use interrupt on compare match when using the compare function.
6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
None.
7. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input
channel must be disregarded to achieve 12-bit accuracy.
Problem fix/Workaround
Run three ADC conversions and discard these results after changing input channels to ADC
gain stage.
8. Configuration of PGM and CWCM not as described in XMEGA A Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM),
but not Common Waveform Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode
(CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode.
Problem fix/Workaround
9. PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not
return to normal operation at first update after fault condition is no longer present.
Problem fix/Workaround
Do a write to any AWeX I/O register to re-enable the output.
10. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Table 36-4. Configure PWM and CWCM according to this table:
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled
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Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate out-
put when converting codes that give below 0.75V output:
– ±10 LSB for continuous mode
– ±200 LSB for Sample and Hold mode
Problem fix/Workaround
None.
12. DAC has increased INL or noise for some operating conditions
Some DAC configurations or operating condition will result in increased output error.
– Continous mode: ±5 LSB
– Sample and hold mode: ±15 LSB
– Sample and hold mode for reference above 2.0v: up to ±100 LSB
Problem fix/Workaround
None.
13. DAC refresh may be blocked in S/H mode
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workaround
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
14. Conversion lost on DAC channel B in event triggered mode
If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1
conversions are occasionally lost. This means that not all data-values written to the
Channel 1 data register are converted.
Problem fix/Workaround
Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Periph-
eral clock frequency so the conversion internal never is shorter than 1.5 µs.
15. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
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16. Pending full asynchronous pin change interrupts will not wake the device
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the
sleep instruction is executed, will be ignored until the device is woken from another source
or the source triggers again. This applies when entering all sleep modes where the System
Clock is stopped.
Problem fix/Workaround
None.
17. Pin configuration does not affect Analog Comparator output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator
output.
Problem fix/Workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect
positive input to the negative AC input and vice versa), or use and external inverter to
change polarity of Analog Comparator output.
18. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when exe-
cuting the NMI interrupt handler.
Problem fix/Workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in
software is not required.
19. Writing EEPROM or Flash while reading any of them will not work
The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while exe-
cuting code in Active mode.
Problem fix/Workaround
Enter IDLE sleep mode within 2.5 µs (Five 2 MHz clock cycles and 80 32 MHz clock cycles)
after starting an EEPROM or flash write operation. Wake-up source must either be
EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an
overflow interrupt 7 ms after the erase or write operation has started, or 13 ms after atomic
erase-and-write operation has started, and then enter IDLE sleep mode.
20. Crystal start-up time required after power-save even if crystal is source for RTC
Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be
ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscilla-
tor Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during
this period (0.5s).
Problem fix/Workaround
If faster start-up is required, go to sleep with internal oscillator as system clock.
21. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to
bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not
be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will
be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
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Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
22. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
23. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start,
but is only cleared on start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
24. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the
hardware sets this flag due to a new address received, CLKHOLD is not cleared and the
SCL line is not released. This will lock the bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is
not IDLE, wait for the SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}
25. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
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Problem fix/Workaround
None.
26. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
27. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window
control register, the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
36.2.3 rev. A
Not sampled.
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37. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
37.1 8068T – 12/10
37.2 8068S – 09/10
37.3 8068R – 08/10
1. Datasheet status changed to complete: Preliminary removed from the front page.
2. Updated all tables in the “Electrical Characteristics” .
3. Updated ”Packaging information” on page 61.
4. Replaced Table 34-11 on page 69
5. Replaced Table 34-18 on page 71 and added the figure ”TOSC input capacitance” on page 71
6. Added ERRATA “rev. E” .
7. Added ERRATA “rev. B” .
8. Updated ERRATA for ADC (ADC has increased INL error for some operating conditions).
9. Updated the last page by Atmel new Brand Style Guide.
10. Updated ”Errata” on page 93.
1. Updated the Footnote 3 of ”Ordering Information” on page 2.
2. Updated Footnote 2 of Figure 2-1 on page 3.
3. Updated ”Data Memory Map (Hexadecimal address)” on page 11. 192A3 has 2 KB EEPROM.
4. Updated ”Features” on page 27. Event Channel 0 output on port pin 7.
5. Updated ”Absolute Maximum Ratings*” on page 63 by adding Icc for Flash/EEPROM
Programming.
6. Added AVCC in ”ADC Characteristics” on page 67.
7. Updated Start up time in ”ADC Characteristics” on page 67.
8. Updated ”DAC Characteristics” on page 68. Removed DC output impedence.
9. Updated Figure 35-6 on page 74. Replaced the figure by a correct one.
10. Fixed typo in “Errata” section.
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37.4 8068Q – 02/10
37.5 8068P – 02/10
37.6 8068O – 11/09
37.7 8068N – 10/09
37.8 8068M – 09/09
1. Added ”PDI Speed” on page 92.
1. Updated the device pin-out Figure 2-1 on page 3. PDI_CLK and PDI_DATA renamed only PDI.
2. Removed JTAG Reset from the datasheet.
3. Updated ”DAC - 12-bit Digital to Analog Converter” on page 43. DAC uses internal 1.0 voltage.
4. Added Table 34-19 on page 71.
5. Updated ”Timer/Counter and AWEX functions” on page 49.
6. Updated ”Alternate Pin Function Description” on page 49.
7. Updated all ”Electrical Characteristics” on page 63.
8. Updated ”PAD Characteristics” on page 69.
9. Changed Internal Oscillator Speed to ”Oscillators and Wake-up Time” on page 88.
10. Updated ”Errata” on page 93
1. Updated Table 34-3 on page 66, Endurance and Data Retention.
2. Updated Table 34-11 on page 69, Input hysteresis is in V and not in mV.
3. Updated ”Errata” on page 93.
1. Updated ”Errata” on page 93.
1. Updated ”Electrical Characteristics” on page 63.
2. Added ”Flash and EEPROM Memory Characteristics” on page 66.
3. Added Errata for ”ATxmega192A3, ATxmega128A3, ATxmega64A3” on page 110.
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37.9 8068L – 06/09
37.10 8068K – 02/09
37.11 8068J – 12/08
37.12 8068I – 11/08
37.13 8068H – 10/08
37.14 8068G – 09/08
1. Updated ”Ordering Information” on page 2.
2. Updated ”Features” on page 39.
3. Updated ”Overview” on page 43.
4. Updated ”Overview” on page 48.
5. Added ”Electrical Characteristics” on page 63.
6. Added ”Typical Characteristics” on page 72.
7. Updated “”Errata” on page 93.
1. Added ”Errata” on page 93 for ATxmega256A3 rev B.
1. Added ”Errata” on page 93 for ATxmega256A3 rev A.
1. Updated Featurelist in ”Memories” on page 9.
1. Updated Table 14-1 on page 25.
1. Updated ”Features” on page 1.
2. Updated ”Ordering Information” on page 2.
3. Updated ”Features” on page 9 by removing “External Memory...”.
4. Updated Figure 7-1 on page 10 and Figure 7-2 on page 11.
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37.15 8068F – 08/08
37.16 8068E – 08/08
37.17 8068D – 06/08
37.18 8068C – 06/08
37.19 8068B – 06/08
5. Updated Table 7-2 on page 14 and Table 7-3 on page 14.
6. Updated ”Features” on page 41 and ”Overview” on page 41.
7 Removed “Interrupt Vector Summary” section from datasheet.
1. Changed Figure 2-1’s title to “Block diagram and pinout.”
2. Changed Package Type to “64M2” in ”Ordering Information” on page 2 and in ”Errata” on page
93.
3. Updated Table 30-5 on page 52.
4. Inserted a correct “64A” TQFP drawing on page 61.
1. Updated ”Block Diagram” on page 5.
2. Inserted “Interrupt Vector Summary” on page 54.
1. References to External Bus Interface (EBI) removed from ”Features” on page 1.
1. Updated ”Features” on page 1.
2. Updated Figure 2-1 on page 3.
3. Updated ”Overview” on page 4.
4. Updated Table 7-2 on page 14.
5. Replaced Figure 25-1 on page 42 by a correct one.
6. Updated “Features” and ”Overview” on page 43.
7. Updated all tables in section ”Alternate Pin Functions” on page 51.
1. Updated ”Features” on page 1.
2. Updated ”” on page 2 and ”Pinout and Pin Functions” on page 49.
3. Updated ”Ordering Information” on page 2.
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37.20 8068A – 02/08
4. Updated ”Overview” on page 4, included the XMEGA A3 explanation text on page 6.
5. Added XMEGA A3 Block Diagram, Figure 3-1 on page 5.
6. Updated AVR CPU ”Overview” on page 7 and Updated Figure 6-1 on page 7.
7. Updated Event System block diagram, Figure 9-1 on page 17.
8. Updated ”PMIC - Programmable Multi-level Interrupt Controller” on page 25.
9. Updated ”AC - Analog Comparator” on page 44.
10. Updated ”I/O configuration” on page 27.
11. Inserted a new Figure 16-1 on page 32.
12. Updated ”Peripheral Module Address Map” on page 56.
13. Inserted ”Instruction Set Summary” on page 57.
14. Added Speed grades in ”Operating Voltage and Frequency” on page 65.
1. Initial revision.
i
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Table of Contents
Features ..................................................................................................... 1
Typical Applications ................................................................................ 1
1 Ordering Information ............................................................................... 2
2 Pinout/Block Diagram .............................................................................. 3
3 Overview ................................................................................................... 4
3.1Block Diagram ...........................................................................................................5
4 Resources ................................................................................................. 6
4.1Recommended reading .............................................................................................6
5 Disclaimer ................................................................................................. 6
6 AVR CPU ................................................................................................... 7
6.1Features ....................................................................................................................7
6.2Overview ...................................................................................................................7
6.3Register File ..............................................................................................................8
6.4ALU - Arithmetic Logic Unit .......................................................................................8
6.5Program Flow ............................................................................................................8
7 Memories .................................................................................................. 9
7.1Features ....................................................................................................................9
7.2Overview ...................................................................................................................9
7.3In-System Programmable Flash Program Memory .................................................10
7.4Data Memory ...........................................................................................................11
7.5Production Signature Row .......................................................................................13
7.6User Signature Row ................................................................................................13
7.7Flash and EEPROM Page Size ...............................................................................14
8 DMAC - Direct Memory Access Controller .......................................... 15
8.1Features ..................................................................................................................15
8.2Overview .................................................................................................................15
9 Event System ......................................................................................... 16
9.1Features ..................................................................................................................16
9.2Overview .................................................................................................................16
10 System Clock and Clock options ......................................................... 18
10.1Features ................................................................................................................18
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10.2Overview ...............................................................................................................18
10.3Clock Options ........................................................................................................19
11 Power Management and Sleep Modes ................................................. 21
11.1Features ................................................................................................................21
11.2Overview ...............................................................................................................21
11.3Sleep Modes .........................................................................................................21
12 System Control and Reset .................................................................... 23
12.1Features ................................................................................................................23
12.2Resetting the AVR .................................................................................................23
12.3Reset Sources .......................................................................................................23
13 WDT - Watchdog Timer ......................................................................... 24
13.1Features ................................................................................................................24
13.2Overview ...............................................................................................................24
14 PMIC - Programmable Multi-level Interrupt Controller ....................... 25
14.1Features ................................................................................................................25
14.2Overview ...............................................................................................................25
14.3Interrupt vectors ....................................................................................................25
15 I/O Ports .................................................................................................. 27
15.1Features ................................................................................................................27
15.2Overview ...............................................................................................................27
15.3I/O configuration ....................................................................................................27
15.4Input sensing .........................................................................................................30
15.5Port Interrupt .........................................................................................................30
15.6Alternate Port Functions ........................................................................................30
16 T/C - 16-bits Timer/Counter with PWM ................................................. 31
16.1Features ................................................................................................................31
16.2Overview ...............................................................................................................31
17 AWEX - Advanced Waveform Extension ............................................. 33
17.1Features ................................................................................................................33
17.2Overview ...............................................................................................................33
18 Hi-Res - High Resolution Extension ..................................................... 34
18.1Features ................................................................................................................34
18.2Overview ...............................................................................................................34
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19 RTC - Real-Time Counter ...................................................................... 35
19.1Features ................................................................................................................35
19.2Overview ...............................................................................................................35
20 TWI - Two Wire Interface ....................................................................... 36
20.1Features ................................................................................................................36
20.2Overview ...............................................................................................................36
21 SPI - Serial Peripheral Interface ............................................................ 37
21.1Features ................................................................................................................37
21.2Overview ...............................................................................................................37
22 USART ..................................................................................................... 38
22.1Features ................................................................................................................38
22.2Overview ...............................................................................................................38
23 IRCOM - IR Communication Module .................................................... 39
23.1Features ................................................................................................................39
23.2Overview ...............................................................................................................39
24 Crypto Engine ........................................................................................ 40
24.1Features ................................................................................................................40
24.2Overview ...............................................................................................................40
25 ADC - 12-bit Analog to Digital Converter ............................................. 41
25.1Features ................................................................................................................41
25.2Overview ...............................................................................................................41
26 DAC - 12-bit Digital to Analog Converter ............................................. 43
26.1Features ................................................................................................................43
26.2Overview ...............................................................................................................43
27 AC - Analog Comparator ....................................................................... 44
27.1Features ................................................................................................................44
27.2Overview ...............................................................................................................44
27.3Input Selection .......................................................................................................46
27.4Window Function ...................................................................................................46
28 OCD - On-chip Debug ............................................................................ 47
28.1Features ................................................................................................................47
28.2Overview ...............................................................................................................47
29 Program and Debug Interfaces ............................................................. 48
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29.1Features ................................................................................................................48
29.2Overview ...............................................................................................................48
29.3IEEE 1149.1 (JTAG) Boundary-scan ....................................................................48
30 Pinout and Pin Functions ...................................................................... 49
30.1Alternate Pin Function Description ........................................................................49
30.2Alternate Pin Functions .........................................................................................51
31 Peripheral Module Address Map .......................................................... 56
32 Instruction Set Summary ...................................................................... 57
33 Packaging information .......................................................................... 61
33.164A ........................................................................................................................61
33.264M2 .....................................................................................................................62
34 Electrical Characteristics ...................................................................... 63
34.1Absolute Maximum Ratings* .................................................................................63
34.2DC Characteristics ................................................................................................63
34.3Operating Voltage and Frequency ........................................................................65
34.4Flash and EEPROM Memory Characteristics .......................................................66
34.5ADC Characteristics ..............................................................................................67
34.6DAC Characteristics ..............................................................................................68
34.7Analog Comparator Characteristics .......................................................................68
34.8Bandgap Characteristics .......................................................................................68
34.9Brownout Detection Characteristics ......................................................................69
34.10PAD Characteristics ............................................................................................69
34.11POR Characteristics ............................................................................................70
34.12Reset Characteristics ..........................................................................................70
34.13Oscillator Characteristics .....................................................................................70
35 Typical Characteristics .......................................................................... 72
35.1Active Supply Current ............................................................................................72
35.2Idle Supply Current ................................................................................................75
35.3Power-down Supply Current .................................................................................79
35.4Power-save Supply Current ..................................................................................80
35.5Pin Pull-up .............................................................................................................80
35.6Pin Output Voltage vs. Sink/Source Current .........................................................82
35.7Pin Thresholds and Hysteresis ..............................................................................85
35.8Bod Thresholds .....................................................................................................87
35.9Oscillators and Wake-up Time ..............................................................................88
35.10Module current consumption ...............................................................................91
35.11Reset Pulsewidth .................................................................................................92
35.12PDI Speed ...........................................................................................................92
36 Errata ....................................................................................................... 93
36.1ATxmega256A3 .....................................................................................................93
36.2ATxmega192A3, ATxmega128A3, ATxmega64A3 .............................................110
37 Datasheet Revision History ................................................................ 124
37.18068T – 12/10 .....................................................................................................124
37.28068S – 09/10 .....................................................................................................124
37.38068R – 08/10 .....................................................................................................124
37.48068Q – 02/10 .....................................................................................................125
37.58068P – 02/10 .....................................................................................................125
37.68068O – 11/09 .....................................................................................................125
37.78068N – 10/09 .....................................................................................................125
37.88068M – 09/09 ....................................................................................................125
37.98068L – 06/09 .....................................................................................................126
37.108068K – 02/09 ...................................................................................................126
37.118068J – 12/08 ....................................................................................................126
37.128068I – 11/08 ....................................................................................................126
37.138068H – 10/08 ...................................................................................................126
37.148068G – 09/08 ...................................................................................................126
37.158068F – 08/08 ...................................................................................................127
37.168068E – 08/08 ...................................................................................................127
37.178068D – 06/08 ...................................................................................................127
37.188068C – 06/08 ...................................................................................................127
37.198068B – 06/08 ...................................................................................................127
37.208068A – 02/08 ...................................................................................................128
Table of Contents....................................................................................... i
8068T–AVR–12/10
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