SDR SDRAM
MT48LC2M32B2 – 512K x 32 x 4 Banks
Features
• PC100-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode (not available on AT devices)
• Auto refresh
– 64ms, 4096-cycle refresh
(commercial and industrial)
– 16ms, 4096-cycle refresh
(automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• Supports CAS latency (CL) of 1, 2, and 3
Options Marking
• Configuration
– 2 Meg x 32 (512K x 32 x 4 banks) 2M32B2
• Plastic package – OCPL1
– 86-pin TSOP II (400 mil) standard TG
– 86-pin TSOP II (400 mil) Pb-free P
– 90-ball VFBGA (8mm x 13mm) Pb-
free
B5
• Timing – cycle time
– 5ns (200 MHz) -5
– 5.5ns (183 MHz) -552
– 6ns (167 MHz) -62
– 6ns (167 MHz) -6A3
– 7ns (143 MHz) -72
• Operating temperature range
– Commercial (0˚C to +70˚C) None
– Industrial (–40˚C to +85˚C) IT
– Automotive (–40˚C to +105˚C) AT4
• Revision :G/:J
Notes: 1. Off-center parting line.
2. Available only on revision G.
3. Available only on revision J.
4. Contact Micron for availability.
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
Clock
Frequency (MHz) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-5 200 3-3-3 15 15 15
-55 183 3-3-3 16.5 16.5 16.5
-6 167 3-3-3 18 18 18
-6A 167 3-3-3 18 18 18
-7 143 3-3-3 20 20 21
64Mb: x32 SDRAM
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Products and specifications discussed herein are subject to change by Micron without notice.
Table 2: Address Table
Parameter 2 Meg x 32
Configuration 512K x 32 x 4 banks
Refresh count 4K
Row addressing 2K A[10:0]
Bank addressing 4 BA[1:0]
Column addressing 256 A[7:0]
Table 3: 64Mb (x32) SDR Part Numbering
Part Numbers Architecture Package
MT48LC2M32B2TG 2 Meg x 32 86-pin TSOP II
MT48LCM32B2P 2 Meg x 32 86-pin TSOP II
MT48LC2M3B2B512 Meg x 32 90-ball VFBGA
Note: 1. FBGA Device Decoder: www.micron.com/decoder.
64Mb: x32 SDRAM
Features
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Contents
General Description ......................................................................................................................................... 7
Automotive Temperature .............................................................................................................................. 7
Functional Block Diagrams ............................................................................................................................... 8
Pin and Ball Assignments and Descriptions ....................................................................................................... 9
Package Dimensions ....................................................................................................................................... 12
Temperature and Thermal Impedance ............................................................................................................ 14
Electrical Specifications .................................................................................................................................. 17
Electrical Specifications – IDD Parameters ........................................................................................................ 19
Electrical Specifications – AC Operating Conditions ......................................................................................... 21
Functional Description ................................................................................................................................... 24
Commands .................................................................................................................................................... 25
COMMAND INHIBIT .................................................................................................................................. 25
NO OPERATION (NOP) ............................................................................................................................... 26
LOAD MODE REGISTER (LMR) ................................................................................................................... 26
ACTIVE ...................................................................................................................................................... 26
READ ......................................................................................................................................................... 27
WRITE ....................................................................................................................................................... 28
PRECHARGE .............................................................................................................................................. 29
BURST TERMINATE ................................................................................................................................... 29
REFRESH ................................................................................................................................................... 30
AUTO REFRESH ..................................................................................................................................... 30
SELF REFRESH ....................................................................................................................................... 30
Truth Tables ................................................................................................................................................... 31
Initialization .................................................................................................................................................. 36
Mode Register ................................................................................................................................................ 38
Burst Length .............................................................................................................................................. 40
Burst Type .................................................................................................................................................. 40
CAS Latency ............................................................................................................................................... 42
Operating Mode ......................................................................................................................................... 42
Write Burst Mode ....................................................................................................................................... 42
Bank/Row Activation ...................................................................................................................................... 43
READ Operation ............................................................................................................................................. 44
WRITE Operation ........................................................................................................................................... 53
Burst Read/Single Write .............................................................................................................................. 60
PRECHARGE Operation .................................................................................................................................. 61
Auto Precharge ........................................................................................................................................... 61
AUTO REFRESH Operation ............................................................................................................................. 73
SELF REFRESH Operation ............................................................................................................................... 75
Power-Down .................................................................................................................................................. 77
Clock Suspend ............................................................................................................................................... 78
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List of Figures
Figure 1: 2 Meg x 32 Functional Block Diagram ................................................................................................. 8
Figure 2: 86-Pin TSOP (Top View) .................................................................................................................... 9
Figure 3: 90-Ball VFBGA (Top View) ............................................................................................................... 10
Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 12
Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5 ........................................................................... 13
Figure 6: Example: Temperature Test Point Location, 86-Pin TSOP (Top View) ................................................. 15
Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View) ................................................ 16
Figure 8: ACTIVE Command .......................................................................................................................... 26
Figure 9: READ Command ............................................................................................................................. 27
Figure 10: WRITE Command ......................................................................................................................... 28
Figure 11: PRECHARGE Command ................................................................................................................ 29
Figure 12: Initialize and Load Mode Register .................................................................................................. 37
Figure 13: Mode Register Definition ............................................................................................................... 39
Figure 14: CAS Latency .................................................................................................................................. 42
Figure 15: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 43
Figure 16: Consecutive READ Bursts .............................................................................................................. 45
Figure 17: Random READ Accesses ................................................................................................................ 46
Figure 18: READ-to-WRITE ............................................................................................................................ 47
Figure 19: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 48
Figure 20: READ-to-PRECHARGE .................................................................................................................. 48
Figure 21: Terminating a READ Burst ............................................................................................................. 49
Figure 22: Alternating Bank Read Accesses ..................................................................................................... 50
Figure 23: READ Continuous Page Burst ......................................................................................................... 51
Figure 24: READ – DQM Operation ................................................................................................................ 52
Figure 25: WRITE Burst ................................................................................................................................. 53
Figure 26: WRITE-to-WRITE .......................................................................................................................... 54
Figure 27: Random WRITE Cycles .................................................................................................................. 55
Figure 28: WRITE-to-READ ............................................................................................................................ 55
Figure 29: WRITE-to-PRECHARGE ................................................................................................................. 56
Figure 30: Terminating a WRITE Burst ............................................................................................................ 57
Figure 31: Alternating Bank Write Accesses ..................................................................................................... 58
Figure 32: WRITE – Continuous Page Burst ..................................................................................................... 59
Figure 33: WRITE – DQM Operation ............................................................................................................... 60
Figure 34: READ With Auto Precharge Interrupted by a READ ......................................................................... 62
Figure 35: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 63
Figure 36: READ With Auto Precharge ............................................................................................................ 64
Figure 37: READ Without Auto Precharge ....................................................................................................... 65
Figure 38: Single READ With Auto Precharge .................................................................................................. 66
Figure 39: Single READ Without Auto Precharge ............................................................................................. 67
Figure 40: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 68
Figure 41: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 68
Figure 42: WRITE With Auto Precharge ........................................................................................................... 69
Figure 43: WRITE Without Auto Precharge ..................................................................................................... 70
Figure 44: Single WRITE With Auto Precharge ................................................................................................. 71
Figure 45: Single WRITE Without Auto Precharge ............................................................................................ 72
Figure 46: Auto Refresh Mode ........................................................................................................................ 74
Figure 47: Self Refresh Mode .......................................................................................................................... 76
Figure 48: Power-Down Mode ........................................................................................................................ 77
Figure 49: Clock Suspend During WRITE Burst ............................................................................................... 78
Figure 50: Clock Suspend During READ Burst ................................................................................................. 79
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Figure 51: Clock Suspend Mode ..................................................................................................................... 80
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List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Address Table ..................................................................................................................................... 2
Table 3: 64Mb (x32) SDR Part Numbering ......................................................................................................... 2
Table 4: Pin and Ball Descriptions .................................................................................................................. 11
Table 5: Temperature Limits .......................................................................................................................... 14
Table 6: Thermal Impedance Simulated Values ............................................................................................... 15
Table 7: Absolute Maximum Ratings .............................................................................................................. 17
Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 17
Table 9: Capacitance ..................................................................................................................................... 18
Table 10: IDD Specifications and Conditions – Revision G ................................................................................ 19
Table 11: IDD Specifications and Conditions – Revision J ................................................................................. 20
Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 21
Table 13: AC Functional Characteristics ......................................................................................................... 22
Table 14: Truth Table – Commands and DQM Operation ................................................................................. 25
Table 15: Truth Table – Current State Bank n, Command to Bank n .................................................................. 31
Table 16: Truth Table – Current State Bank n, Command to Bank m ................................................................. 33
Table 17: Truth Table – CKE ........................................................................................................................... 35
Table 18: Burst Definition Table ..................................................................................................................... 41
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General Description
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing
67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous in-
terface (all signals are registered on the positive edge of the clock signal, CLK). Each of
the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Each
of the 16,777,216-bit banks is organized as 2048 rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the
bank; A[10:0] select the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it al-
so allows the column address to be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank while accessing one of the other
three banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran-
dom-access operation.
The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh
mode is provided, along with a power-saving, power-down mode. All inputs and out-
puts are LVTTL-compatible.
SDRAM devices offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-ad-
dress generation, the ability to interleave between internal banks to hide precharge
time, and the capability to randomly change column addresses on each clock cycle dur-
ing a burst access.
Automotive Temperature
The automotive temperature (AT) option adheres to the following specifications:
• 16ms refresh rate
• Self refresh not supported
• Ambient and case temperature cannot be less than –40°C or greater than +105°C
64Mb: x32 SDRAM
General Description
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Functional Block Diagrams
Figure 1: 2 Meg x 32 Functional Block Diagram
11
RAS#
CAS#
CLK
CS#
WE#
CKE
8
A[10:0],
BA[1:0]
DQM[3:0]
13
256
(x32)
8192
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(2048 x 256 x 32)
BANK 0
ROW-
ADDRESS
LATCH
&
DECODER
2048
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ[31:0]
32
32
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
32
BANK 1
BANK 0
BANK 2
BANK 3
11
8
2
4 4
2
REFRESH
COUNTER
11
11
MODE REGISTER
CONTROL
LOGIC
COMMAND
DECODE
ROW-
ADDRESS
MUX
ADDRESS
REGISTER
COLUMN-
ADDRESS
COUNTER/
LATCH
64Mb: x32 SDRAM
Functional Block Diagrams
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Pin and Ball Assignments and Descriptions
Figure 2: 86-Pin TSOP (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NU
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
Note: 1. Package may or may not be assembled with a location notch.
64Mb: x32 SDRAM
Pin and Ball Assignments and Descriptions
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Figure 3: 90-Ball VFBGA (Top View)
1 2 3 4 6 7 8 95
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQM1
VDDQ
VSSQ
VSSQ
DQ11
DQ13
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NU
DQ8
DQ10
DQ12
VDDQ
DQ15
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
CAS#
VDD
DQ6
DQ1
VDDQ
VDD
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
NC
RAS#
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS#
WE#
DQ7
DQ5
DQ3
VSSQ
DQ0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
64Mb: x32 SDRAM
Pin and Ball Assignments and Descriptions
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Table 4: Pin and Ball Descriptions
Symbol Type Description
CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides precharge power-down and SELF REFRESH operation (all banks idle), active
power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in pro-
gress). CKE is synchronous except after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same mode. The input buffers, in-
cluding CLK, are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command de-
coder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already
in progress will continue, and DQM operation will retain its DQ mask capability while CS# is
HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-
ered part of the command code.
CAS#, RAS#,
WE#
Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being en-
tered.
DQM[3:0] Input Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. DQM0
corresponds to DQ[7:0]; DQM1 corresponds to DQ[15:8]; DQM2 corresponds to DQ[23:16]; and
DQM3 corresponds to DQ[31:24]. DQM[3:0] are considered same state when referenced as
DQM.
BA[1:0] Input Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRE-
CHARGE command is being applied.
A[10:0] Input Address inputs: A[10:0] are sampled during the ACTIVE command (row address A[10:0]) and
READ or WRITE command (column address A[7:0] with A10 defining auto precharge) to select
one location out of the memory array in the respective bank. A10 is sampled during a PRE-
CHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selec-
ted by BA[1:0] (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
DQ[31:0] I/O Data input/output: Data bus.
VDDQ Supply DQ power supply: DQ power to the die for improved noise immunity.
VSSQ Supply DQ ground: DQ ground to the die for improved noise immunity.
VDD Supply Power supply: 3.3V ±0.3V.
VSS Supply Ground.
NC – No connect: These pins/balls should be left unconnected.
NU – Not used.
64Mb: x32 SDRAM
Pin and Ball Assignments and Descriptions
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Package Dimensions
Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P
See Detail A
2X R 1.00
2X R 0.75
0.50
TYP
0.61
10.16 ±0.08
0.50 ±0.10
11.76 ±0.20
Pin #1 ID
Detail A
22.22 ±0.08
0.20 +0.07
-0.03
0.15 +0.03
-0.02
0.10 +0.10
-0.05
1.20 MAX
0.10
0.25
Gage
plane
0.80
TYP
2X 0.10
2X 2.80
Plastic package material: Epoxy novolac
Plated lead finish:
TG (90% Sn, 10% Pb) or P (100% Sn) 0.01 ±0.005 thick per side
Package width and length do not include
mold protrusion. Allowable protrusion is
0.25 per side.
Notes: 1. All dimensions are in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
3. "2X" means the notch is present in two locations (both ends of the device).
4. Package may or may not be assembled with a location notch.
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Package Dimensions
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Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5
Ball A1 ID
1.00 MAX
Mold compound:
Epoxy novolac
Substrate material:
Plastic laminate
Solder ball material:
62% Sn, 36% Pb, 2% Ag or
96.5% Sn, 3%Ag, 0.5% Cu
13.00 ±0.10
Ball A1
Ball A9
Ball A1 ID
0.80 TYP
6.50 ±0.05
8.00 ±0.10
4.00 ±0.053.20 ±0.05
5.60 ±0.05
0.65 ±0.05
Seating plane
A
11.20 ±0.10
6.40
0.10 A
90X Ø0.45
Dimensions apply
to solder balls post
reflow. The pre-reflow
diameter is 0.42 on a
0.40 SMD ball pad.
C
L
C
L
0.80 TYP
Notes: 1. All dimensions are in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
3. Recommended pad size for PCB is 0.33mm ±0.025mm.
64Mb: x32 SDRAM
Package Dimensions
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Temperature and Thermal Impedance
It is imperative that the SDRAM device’s temperature specifications, shown in Temper-
ature Limits below, be maintained to ensure the junction temperature is in the proper
operating range to meet data sheet specifications. An important step in maintaining the
proper junction temperature is using the device’s thermal impedances correctly. The
thermal impedances are listed in Table 6 (page 15) for the applicable die revision and
packages being made available. These thermal impedance values vary according to the
density, package, and particular design used for each device.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications” prior to using the thermal impedan-
ces listed in Table 6 (page 15). To ensure the compatibility of current and future de-
signs, contact Micron Applications Engineering to confirm thermal impedance values.
The SDRAM device’s safe junction temperature range can be maintained when the TC
specification is not exceeded. In applications where the device’s ambient temperature
is too high, use of forced air and/or heat sinks may be required to satisfy the case tem-
perature specifications.
Table 5: Temperature Limits
Parameter Symbol Min Max Unit Notes
Operating case temperature Commercial TC0 80 °C 1, 2, 3, 4
Industrial –40 90
Automotive –40 105
Junction temperature Commercial TJ0 85 °C 3
Industrial –40 95
Automotive –40 110
Ambient temperature Commercial TA0 70 °C 3, 5
Industrial –40 85
Automotive –40 105
Peak reflow temperature TPEAK – 260 °C
Notes: 1. MAX operating case temperature TC is measured in the center of the package on the
top side of the device, as shown in Figure 6 (page 15) and Figure 7 (page 16).
2. Device functionality is not guaranteed if the device exceeds maximum TC during opera-
tion.
3. All temperature specifications must be satisfied.
4. The case temperature should be measured by gluing a thermocouple to the top-center
of the component. This should be done with a 1mm bead of conductive epoxy, as de-
fined by the JEDEC EIA/JESD51 standards. Take care to ensure that the thermocouple
bead is touching the case.
5. Operating ambient temperature surrounding the package.
64Mb: x32 SDRAM
Temperature and Thermal Impedance
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Table 6: Thermal Impedance Simulated Values
Die
Revision Package Substrate
ΘJA (°C/W)
Airflow =
0m/s
ΘJA (°C/W)
Airflow =
1m/s
ΘJA (°C/W)
Airflow =
2m/s ΘJB (°C/W) ΘJC (°C/W)
G 86-pin TSOP Low Con-
ductivity
95.2 75.3 69.0 66.5 12.7
High Con-
ductivity
66.6 57.7 54.6 53.6
90-ball VFBGA Low Con-
ductivity
70.6 57.6 69.5 35.7 7.95
High Con-
ductivity
54 47.3 52.7 35.2
J 86-pin TSOP Low Con-
ductivity
122.3 105.6 98.1 89.5 20.7
High Con-
ductivity
101.9 93.5 88.8 87.6
90-ball VFBGA Low Con-
ductivity
76.8 63.1 63.1 50.1 10.4
High Con-
ductivity
56.3 49.6 46.9 43.5
Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications
Engineering to confirm thermal impedance values.
2. Thermal resistance data is sampled from multiple lots, and the values should be viewed
as typical.
3. These are estimates; actual results may vary.
Figure 6: Example: Temperature Test Point Location, 86-Pin TSOP (Top View)
22.22mm
11.11mm
Test point
10.16mm
5.08mm
Note: 1. Package may or may not be assembled with a location notch.
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Temperature and Thermal Impedance
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Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View)
Test point
6.50mm
13.00mm
4.00mm
8.00mm
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Temperature and Thermal Impedance
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Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 7: Absolute Maximum Ratings
Voltage/Temperature Symbol Min Max Unit
Voltage on VDD, VDDQ supply relative to VSS VDD, VDDQ –1 4.6 V
Voltage on inputs, NC, or I/O pins relative to VSS VIN –1 4.6 V
Storage temperature (plastic) TSTG –55 150 °C
Power dissipation – – 1 W
Table 8: DC Electrical Characteristics and Operating Conditions
Notes 1–3 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V
Parameter/Condition Symbol Min Max Unit Notes
Supply voltage VDD, VDDQ 3 3.6 V
Input high voltage: Logic 1; All inputs VIH 2 VDD + 0.3 V 4
Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 4
Output high voltage: IOUT = –4mA VOH 2.4 – V
Output low voltage: IOUT = 4mA VOL – 0.4 V
Input leakage current: Any input 0V ≤ VIN ≤ VDD (All other pins
not under test = 0V)
IL–5 5 μA
Output leakage current: DQs are disabled; 0V ≤ VOUT ≤ VDDQ IOZ –5 5 μA
Operating temperature: Commercial TA0 70 °C
Industrial TA–40 85 °C
Automotive TA–40 105 °C
Notes: 1. All voltages referenced to VSS.
2. An initial pulse of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured (VDD and VDDQ must be powered
up simultaneously. VSS and VSSQ must be at same potential). The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh requirement is excee-
ded.
3. VDD,min = 3.135V for -6, -55, and -5 speed grades.
4. VIH overshoot: VIH,max = VDDQ + 1.2V for a pulse width ≤ 3ns, and the pulse width cannot
be greater than one-third of the cycle rate. VIL undershoot: VIL,min = –1.2V for a pulse
width ≤3ns, and the pulse width cannot be greater than one-third of the cycle rate.
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Electrical Specifications
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Table 9: Capacitance
Note 1 applies to all parameters and conditions
Package Parameter Min Max Unit
TSOP Package Input capacitance: CLK 2.5 4.0 pF
Input capacitance: All other input-only
balls/pins
2.5 4.0 pF
Input/output capacitance: DQ 4.0 6.5 pF
VFBGA Package Input capacitance: CLK 1.5 4.0 pF
Input capacitance: All other input-only
balls/pins
1.5 4.0 pF
Input/output capacitance: DQ 3 6.5 pF
Note: 1. This parameter is sampled. VDD, VDDQ = 3.3V; f = 1 MHz, TA = 25°C; pin under test biased
at 1.4V. AC can range from 0pF to 6pF.
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Electrical Specifications
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Electrical Specifications – IDD Parameters
Table 10: IDD Specifications and Conditions – Revision G
Notes 1–5 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V
Parameter/Condition Symbol
Max
Unit Notes-5 -55 -6 -7
Operating current: Active mode; Burst = 2; READ or WRITE; tRC ≥ tRC
(MIN); CL = 3
IDD1 200 190 150 130 mA 6, 7, 8, 9
Standby current: Power-down mode; All banks idle; CKE = LOW IDD2 2 2 2 2 mA
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks ac-
tive after tRCD met; No accesses in progress
IDD3 80 70 60 50 mA 6, 8, 9, 10
Operating current: Burst mode; Continuous burst; READ or WRITE;
All banks active; CL = 3
IDD4 280 260 180 160 mA 6, 7, 8, 9
Auto refresh current: CL = 3; CKE, CS# = HIGH tRFC = tRFC (MIN) IDD5 225 225 225 225 mA 6, 7, 8, 9,
10
Self refresh current: CKE ≤ 0.2V IDD6 2 2 2 2 mA 11
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Electrical Specifications – IDD Parameters
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Table 11: IDD Specifications and Conditions – Revision J
Notes 1–5 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V
Parameter/Condition Symbol
Max
Unit Notes-6A
Operating current: Active mode; Burst = 2; READ or WRITE; tRC ≥ tRC (MIN); CL = 3 IDD1 120 mA 6, 7, 8, 9
Standby current: Power-down mode; All banks idle; CKE = LOW IDD2 2.5 mA
Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD
met; No accesses in progress
IDD3 45 mA 6, 8, 9, 10
Operating current: Burst mode; Continuous burst; READ or WRITE; All banks active;
CL = 3
IDD4 120 mA 6, 7, 8, 9
Auto refresh current: CL = 3; CKE, CS# = HIGH tRFC = tRFC (MIN) IDD5 180 mA 6, 7, 8, 9, 10
Self refresh current: CKE ≤ 0.2V IDD6 3 mA 11
Notes: 1. All voltages referenced to VSS.
2. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh requirement is excee-
ded.
3. AC timing and IDD tests have VIL = 0.25V and VIH = 2.75V, with timing referenced to 1.5V
crossover point.
4. IDD specifications are tested after the device is properly initialized.
5. VDD = 3.135V for -6, -55, and -5 speed grades.
6. IDD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time and the outputs open.
7. The IDD current will decrease as the CL is reduced. This is due to the fact that the maxi-
mum cycle rate is slower as the CL is reduced.
8. Address transitions average one transition every two clocks.
9. tCK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5.
10. Other input signals are allowed to transition no more than once in any two-clock period
and are otherwise at valid VIH or VIL levels.
11. Enables on-chip refresh and address counters.
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Electrical Specifications – IDD Parameters
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Electrical Specifications – AC Operating Conditions
Table 12: Electrical Characteristics and Recommended AC Operating Conditions
Notes 1–5 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V
Parameter Symbol
-5 -556-66-6A7-76
Unit NotesMin Max Min Max Min Max Min Max Min Max
Access time from CLK
(positive edge)
CL = 3 tAC(3) – 4.5 – 5 – 5.5 – 5.4 – 5.5 ns
CL = 2 tAC(2) – – – – – 7.5 – 7.58– 8 ns
CL = 1 tAC(1) – – – – – 17 – 178– 17 ns
Address hold time tAH 1 – 1 – 1 – 0.8 – 1 – ns
Address setup time tAS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns
CLK high-level width tCH 2 – 2 – 2.5 – 2.5 – 2.75 – ns
CLK low-level width tCL 2 – 2 – 2.5 – 2.5 – 2.75 – ns
Clock cycle time CL = 3 tCK(3) 5 – 5.5 – 6 – 6 – 7 – ns 9
CL = 2 tCK(2) – – – – 10 – 108– 10 – ns 9
CL = 1 tCK(1) – – – – 20 – 208– 20 – ns 9
CKE hold time tCKH 1 – 1 – 1 – 0.8 – 1 – ns
CKE setup time tCKS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns
CS#, RAS#, CAS#, WE#, DQM
hold time
tCMH 1 – 1 – 1 – 0.8 – 1 – ns
CS#, RAS#, CAS#, WE#, DQM
setup time
tCMS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns
Data-in hold time tDH 1 – 1 – 1 – 0.8 – 1 – ns
Data-in setup time tDS 1.5 – 1.5 – 1.5 – 1.5 – 2 – ns
Data-out High-Z time CL = 3 tHZ(3) 4.5 – 5 – – 5.5 – 5.4 – 5.5 ns 10
CL = 2 tHZ(2) – – – – – 7.5 – 7.58– 8 ns 10
CL = 1 tHZ(1) – – – – – 17 – 178– 17 ns 10
Data-out Low-Z time tLZ 1 – 1 – 1 – 1 – 1 – ns
Data-out hold time tOH 1.5 – 2 – 2 – 3 – 2.5 – ns
ACTIVE-to-PRECHARGE com-
mand
tRAS 38.7 120k 38.7 120k 42 120k 42 120k 42 120k ns
ACTIVE-to-ACTIVE command
period
tRC 55 – 55 – 60 – 60 – 70 – ns 11
AUTO REFRESH period tRFC 60 – 60 – 60 – 60 – 70 – ns
ACTIVE-to-READ or WRITE
delay
tRCD 15 – 16.5 – 18 – 18 – 20 – ns
Refresh period (4096 rows) tREF – 64 – 64 – 64 – 64 – 64 ms
Refresh period – automotive
(4096 rows)
tREFAT – 16 – 16 – 16 – 16 – 16 ms
PRECHARGE command peri-
od
tRP 15 – 16.5 – 18 – 18 – 20 – ns
ACTIVE bank a to ACTIVE
bank b command
tRRD 10 – 11 – 12 – 12 – 14 – ns 12
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Electrical Specifications – AC Operating Conditions
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Table 12: Electrical Characteristics and Recommended AC Operating Conditions (Continued)
Notes 1–5 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3V
Parameter Symbol
-5 -556-66-6A7-76
Unit NotesMin Max Min Max Min Max Min Max Min Max
Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 0.3 1.2 0.3 1.2 ns 13
WRITE recovery time tWR 2 – 2 – 1
CLK
+
6ns
– 1
CLK
+
6ns
– 1
CLK
+
7ns
–tCK 14
12 – 12 – 14 – ns 15
Exit SELF REFRESH-to-ACTIVE
command
tXSR 55 – 55 – 70 – 67 – 70 – ns 16
Table 13: AC Functional Characteristics
Notes 2–5 apply to all parameters and conditions
Parameter Symbol -5 -55 -6/6A -7 Unit Notes
READ/WRITE command to READ/WRITE command tCCD 1 1 1 1 tCK 17
CKE to clock disable or power-down entry mode tCKED 1 1 1 1 tCK 18
CKE to clock enable or power-down exit setup mode tPED 1 1 1 1 tCK 18
DQM to input data delay tDQD 0 0 0 0 tCK 17
DQM to data mask during WRITEs tDQM 0 0 0 0 tCK 17
DQM to data High-Z during READs tDQZ 2 2 2 2 tCK 17
WRITE command to input data delay tDWD 0 0 0 0 tCK 17
Data-in to ACTIVE command CL = 3 tDAL(3) 5 5 5 5 tCK 19, 20
CL = 2 tDAL(2) – – 4 4 tCK 19, 20
CL = 1 tDAL(1) – – 3 3 tCK 19, 20
Data-in to PRECHARGE command tDPL 2 2 2 2 tCK 20, 21
Last data-in to burst STOP command tBDL 1 1 1 1 tCK 17
Last data-in to new READ/WRITE command tCDL 1 1 1 1 tCK 17
Last data-in to PRECHARGE command tRDL 2 2 2 2 tCK 20, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH
command
tMRD 2 2 2 2 tCK 22
Data-out to High-Z from PRECHARGE command CL = 3 tROH(3) 3 3 3 3 tCK 17
CL = 2 tROH(2) – – 2 2 tCK 17
CL = 1 tROH(1) – – 1 1 tCK 17
Notes: 1. Minimum specifications are used only to indicate the cycle time at which proper opera-
tion over the full temperature range is ensured:
0˚C ≤ TA ≤ +70˚C (commercial)
–40˚C ≤ TA ≤ +85˚C (industrial)
–40˚C ≤ TA ≤ +105˚C (automotive)
2. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered
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Electrical Specifications – AC Operating Conditions
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up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh requirement is excee-
ded.
3. In addition to meeting the transition rate specification, the clock and CKE must transit
between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. Outputs measured at 1.5V with equivalent load:
Q
50pF
5. AC timing and IDD tests have VIL = 0.25V and VIH = 2.75V, with timing referenced to 1.5V
crossover point.
6. Speed grade available only for Revision G.
7. Speed grade available only for Revision J.
8. Not applicable for Revision G.
9. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge states
(READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce
the data rate.
10. tHZ defines the time at which the output achieves the open circuit condition; it is not a
reference to VOH or VOL. The last valid data element will meet tOH before going High-Z.
11. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in reduction of the product lifetime.
12. JEDEC and PC100 specify three clocks.
13. AC characteristics assume tT = 1ns.
14. Auto precharge mode only.
15. Check factory for availability of specially screened devices having tWR = 10ns. tWR = 1
tCK for 100 MHz and slower (tCK = 10ns and higher) in manual precharge.
16. CLK must be toggled a minimum of two times during this period.
17. Required clocks are specified by JEDEC functionality and are not dependent on any tim-
ing parameter.
18. Timing is specified by tCKS. Clock(s) specified as a reference only at minimum cycle rate.
19. Timing is specified by tWR plus tRP. Clock(s) specified as a reference only at minimum cy-
cle rate.
20. Based on tCK = 143 MHz for -7, 166 MHz for -6, 183 MHz for -55, and 200 MHz for -5.
21. Timing is specified by tWR.
22. tCK = 7ns for -7, 6ns for -6, 5.5ns for -55, and 5ns for -5.
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Electrical Specifications – AC Operating Conditions
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Functional Description
In general, this 64Mb SDRAM device (512K x 32x 4 banks) is a quad-bank DRAM that
operates at 3.3V and include a synchronous interface. All signals are registered on the
positive edge of the clock signal, CLK. Each of the 16,777,216-bit banks is organized as
2048 rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE
command are used to select the bank and row to be accessed (BA0 and BA1 select the
bank, A[10:0] select the row). The address bits (A[7:0]) registered coincident with the
READ or WRITE command are used to select the starting column location for the burst
access.
Prior to normal operation, the device must be initialized. The following sections provide
detailed information covering device initialization, register definition, command de-
scriptions, and device operation.
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Functional Description
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Commands
The following table provides a quick reference of available commands, followed by a
written description of each command. Additional Truth Tables (Table 15 (page 31), Ta-
ble 16 (page 33), and Table 17 (page 35)) provide current state/next state informa-
tion.
Table 14: Truth Table – Commands and DQM Operation
Note 1 applies to all parameters and conditions
Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ Notes
COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (select bank and activate row) L L H H X Bank/row X 2
READ (select bank and column, and start READ burst) L H L H L/H Bank/col X 3
WRITE (select bank and column, and start WRITE burst) L H L L L/H Bank/col Valid 3
BURST TERMINATE L H H L X X Active 4
PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5
AUTO REFRESH or SELF REFRESH (enter self refresh mode) L L L H X X X 6, 7
LOAD MODE REGISTER L L L L X Op-code X 8
Write enable/output enable X X X X L X Active 9
Write inhibit/output High-Z X X X X H X High-Z 9
Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1
determine which bank is made active.
3. A[0:i] provide column address (where i = the most significant column address for a given
device configuration). A10 HIGH enables the auto precharge feature (nonpersistent),
while A10 LOW disables the auto precharge feature. BA0 and BA1 determine which
bank is being read from or written to.
4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the com-
mand could coincide with data on the bus. However, the DQ column reads a “Don’t
Care” state to illustrate that the BURST TERMINATE command can occur when there is
no data present.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks pre-
charged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” ex-
cept for CKE.
8. A[11:0] define the op-code written to the mode register.
9. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
delay).
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by
the device, regardless of whether the CLK signal is enabled. The device is effectively de-
selected. Operations already in progress are not affected.
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NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to the selected device
(CS# is LOW). This prevents unwanted commands from being registered during idle or
wait states. Operations already in progress are not affected.
LOAD MODE REGISTER (LMR)
The mode registers are loaded via inputs A[n:0] (where An is the most significant ad-
dress term), BA0, and BA1(see Mode Register (page 38)). The LOAD MODE REGISTER
command can only be issued when all banks are idle and a subsequent executable com-
mand cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The value on the BA0, BA1 inputs selects the bank, and the address provided se-
lects the row. This row remains active for accesses until a PRECHARGE command is is-
sued to that bank. A PRECHARGE command must be issued before opening a different
row in the same bank.
Figure 8: ACTIVE Command
CS#
WE#
CAS#
RAS#
CKE
CLK
Address Row address
Don’t Care
HIGH
BA0, BA1 Bank address
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READ
The READ command is used to initiate a burst read access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-
umn location. The value on input A10 determines whether auto precharge is used. If au-
to precharge is selected, the row being accessed is precharged at the end of the READ
burst; if auto precharge is not selected, the row remains open for subsequent accesses.
Read data appears on the DQ subject to the logic level on the DQM inputs two clocks
earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-
Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data.
Figure 9: READ Command
CS#
WE#
CAS#
RAS#
CKE
CLK
Column address
A101
BA0, BA1
Don’t Care
HIGH
EN AP
DIS AP
Bank address
Address
Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.
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WRITE
The WRITE command is used to initiate a burst write access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided selects the starting col-
umn location. The value on input A10 determines whether auto precharge is used. If au-
to precharge is selected, the row being accessed is precharged at the end of the write
burst; if auto precharge is not selected, the row remains open for subsequent accesses.
Input data appearing on the DQ is written to the memory array, subject to the DQM in-
put logic level appearing coincident with the data. If a given DQM signal is registered
LOW, the corresponding data is written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that
byte/column location.
Figure 10: WRITE Command
DIS AP
EN AP
CS#
WE#
CAS#
RAS#
CKE
CLK
Column address
Don’t Care
HIGH
Bank address
Address
BA0, BA1
Valid address
A101
Note: 1. EN AP = enable auto precharge, DIS AP = disable auto precharge.
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PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only one bank is
precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands are issued to that bank.
Figure 11: PRECHARGE Command
CS#
WE#
CAS#
RAS#
CKE
CLK
A10
Don’t Care
HIGH
All banks
Bank selected
Address
BA0, BA1 Bank address
Valid address
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or continu-
ous page bursts. The most recently registered READ or WRITE command prior to the
BURST TERMINATE command is truncated.
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REFRESH
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All active banks must be pre-
charged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command
should not be issued until the minimum tRP has been met after the PRECHARGE com-
mand, as shown in Bank/Row Activation (page 43).
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. Regardless of device width,
the 64Mb SDRAM requires 4096 AUTO REFRESH cycles every 64ms (commercial and
industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command
every 15.625μs (commercial and industrial) or 3.906μs (automotive) will meet the re-
fresh requirement and ensure that each row is refreshed. Alternatively, 4096 AUTO RE-
FRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once ev-
ery 64ms (commercial and industrial) or 16ms (automotive).
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered-down. When in the self refresh mode, the SDRAM retains data
without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except
CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs
to the SDRAM become a “Don’t Care” with the exception of CKE, which must remain
LOW.
After self refresh mode is engaged, the SDRAM provides its own internal clocking, caus-
ing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self re-
fresh mode for a minimum period equal to tRAS and may remain in self refresh mode
for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK
must be stable (stable clock is defined as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the
SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because
time is required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued at the
specified intervals, as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Self refresh is not supported on automotive temperature devices.
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Truth Tables
Table 15: Truth Table – Current State Bank n, Command to Bank n
Notes 1–6 apply to all parameters and conditions
Current State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X COMMAND INHIBIT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle L L H H ACTIVE (select and activate row)
L L L H AUTO REFRESH 7
L L L L LOAD MODE REGISTER 7
L L H L PRECHARGE 8
Row active L H L H READ (select column and start READ burst) 9
L H L L WRITE (select column and start WRITE burst) 9
L L H L PRECHARGE (deactivate row in bank or banks) 10
Read
(auto precharge disabled)
L H L H READ (select column and start new READ burst) 9
L H L L WRITE (select column and start WRITE burst) 9
L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 10
L H H L BURST TERMINATE 11
Write
(auto precharge disabled)
L H L H READ (select column and start READ burst) 9
L H L L WRITE (select column and start new WRITE burst) 9
L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) 10
L H H L BURST TERMINATE 11
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 17 (page 35))
and after tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted (for example, the current state is for a
specific bank and the commands shown can be issued to that bank when in that state).
Exceptions are covered below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
COMMAND INHIBIT or NOP commands, or supported commands to the other bank
should be issued on any clock edge occurring during these states. Supported commands
to any other bank are determined by the bank’s current state and the conditions descri-
bed in this and the following table.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is
met. After tRP is met, the bank will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. After tRCD is met, the bank will be in the row active state.
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Read with auto precharge enabled: Starts with registration of a READ command
with auto precharge enabled and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
Write with auto precharge enabled: Starts with registration of a WRITE command
with auto precharge enabled and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these
states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
tRFC is met. After tRFC is met, the device will be in the all banks idle state.
Accessing mode register: Starts with registration of a LOAD MODE REGISTER com-
mand and ends when tMRD has been met. After tMRD is met, the device will be in the
all banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends
when tRP is met. After tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank specific; requires that all banks are idle.
8. Does not affect the state of the bank and acts as a NOP to that bank.
9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
10. May or may not be bank specific; if all banks need to be precharged, each must be in a
valid state for precharging.
11. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, re-
gardless of bank.
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Table 16: Truth Table – Current State Bank n, Command to Bank m
Notes 1–6 apply to all parameters and conditions
Current State CS# RAS# CAS# WE# Command/Action Notes
Any H X X X COMMAND INHIBIT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle X X X X Any command otherwise supported for bank m
Row activating, active, or
precharging
L L H H ACTIVE (select and activate row)
L H L H READ (select column and start READ burst) 7
L H L L WRITE (select column and start WRITE burst) 7
L L H L PRECHARGE
Read
(auto precharge disabled)
L L H H ACTIVE (select and activate row)
L H L H READ (select column and start new READ burst) 7, 10
L H L L WRITE (select column and start WRITE burst) 7, 11
L L H L PRECHARGE 9
Write
(auto precharge disabled)
L L H H ACTIVE (select and activate row)
L H L H READ (select column and start READ burst) 7, 12
L H L L WRITE (select column and start new WRITE burst) 7, 13
L L H L PRECHARGE 9
Read
(with auto precharge)
L L H H ACTIVE (select and activate row)
L H L H READ (select column and start new READ burst) 7, 8, 14
L H L L WRITE (select column and start WRITE burst) 7, 8, 15
L L H L PRECHARGE 9
Write
(with auto precharge)
L L H H ACTIVE (select and activate row)
L H L H READ (select column and start READ burst) 7, 8, 16
L H L L WRITE (select column and start new WRITE burst) 7, 8, 17
L L H L PRECHARGE 9
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (Table 17 (page 35)), and
after tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; for example, the cur-
rent state is for bank n and the commands shown can be issued to bank m, assuming
that bank m is in such a state that the given command is supported. Exceptions are cov-
ered below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
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Read with auto precharge enabled: Starts with registration of a READ command
with auto precharge enabled and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
Write with auto precharge enabled: Starts with registration of a WRITE command
with auto precharge enabled and ends when tRP has been met. After tRP is met, the
bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands can only be is-
sued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command/Action column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disa-
bled.
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m burst.
9. The burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CAS latency (CL) later.
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM
should be used one clock prior to the WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered, with
the data-out appearing CL later. The last valid WRITE to bank n will be data-in regis-
tered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The
last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank
m.
14. For a READ with auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CL later. The PRE-
CHARGE to bank n will begin when the READ to bank m is registered.
15. For a READ with auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM
should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered.
16. For a WRITE with auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered, with
the data-out appearing CL later. The PRECHARGE to bank n will begin after tWR is met,
where tWR begins when the READ to bank m is registered. The last valid WRITE bank n
will be data-in registered one clock prior to the READ to bank m.
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The
PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE
to bank m is registered. The last valid WRITE to bank n will be data registered one clock
to the WRITE to bank m.
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Table 17: Truth Table – CKE
Notes 1–4 apply to all parameters and conditions
Current State CKEn-1 CKEnCommandnActionnNotes
Power-down L L X Maintain power-down
Self refresh X Maintain self refresh
Clock suspend X Maintain clock suspend
Power-down L H COMMAND INHIBIT or NOP Exit power-down 5
Self refresh COMMAND INHIBIT or NOP Exit self refresh 6
Clock suspend X Exit clock suspend 7
All banks idle H L COMMAND INHIBIT or NOP Power-down entry
All banks idle AUTO REFRESH Self refresh entry
Reading or writing VALID Clock suspend entry
H H See Table 16 (page 33).
Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previ-
ous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of
COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time
for clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges
occurring during the tXSR period. A minimum of two NOP commands must be provided
during the tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recog-
nize the next command at clock edge n + 1.
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Initialization
SDRAM must be powered up and initialized in a predefined manner. Operational proce-
dures other than those specified may result in undefined operation. After power is ap-
plied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified for the clock pin), the SDRAM re-
quires a 100μs delay prior to issuing any command other than a COMMAND INHIBIT or
NOP. Starting at some point during this 100μs period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP commands must be applied.
After the 100μs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH com-
mands can be issued after the LMR command.
The recommended power-up sequence for SDRAM:
1. Simultaneously apply power to VDD and VDDQ.
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-
compatible.
3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within tim-
ing constraints specified for the clock pin.
4. Wait at least 100μs prior to issuing any command other than a COMMAND INHIB-
IT or NOP.
5. Starting at some point during this 100μs period, bring CKE HIGH. Continuing at
least through the end of this period, 1 or more COMMAND INHIBIT or NOP com-
mands must be applied.
6. Perform a PRECHARGE ALL command.
7. Wait at least tRP time; during this time NOPs or DESELECT commands must be
given. All banks will complete their precharge, thereby placing the device in the all
banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT com-
mands are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT com-
mands are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode reg-
ister will power up in an unknown state, it should be loaded with desired bit values
prior to applying any operational command. Using the LMR command, program
the mode register. The mode register is programmed via the MODE REGISTER SET
command with BA1 = 0, BA0 = 0 and retains the stored information until it is pro-
grammed again or the device loses power. Not programming the mode register
upon initialization will result in default settings which may not be desired. Out-
puts are guaranteed High-Z after the LMR command is issued. Outputs should be
High-Z already before the LMR command is issued.
13. Wait at least tMRD time, during which only NOP or DESELECT commands are al-
lowed.
At this point the DRAM is ready for any valid command.
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Note:
More than two AUTO REFRESH commands can be issued in the sequence. After steps 9
and 10 are complete, repeat them until the desired number of AUTO REFRESH + tRFC
loops is achieved.
Figure 12: Initialize and Load Mode Register
tCH
tCL
tCK
CKE
CK
COMMAND
DQ
BA[1:0] BANK
tRFC tMRD
tRFC
AUTO REFRESH AUTO REFRESH Program Mode Register1,3,4
tCMH
tCMS
Precharge
all banks
(
)(
)
(
)(
)
(
)(
)
(
)(
)
tRP
(
)(
)
(
)(
)
tCKS
Power-up:
VDD and
CLK stable
T = 100µs
MIN
PRECHARGE AUTO
REFRESH
LOAD MODE
REGISTER ACTIVE
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
AUTO
REFRESH
ALL
BANKS
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
High-Z
tCKH
(
)(
)
(
)(
)
DQM/DQML,
DQMU
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)(
)(
)
(
)(
)
(
)(
)
NOP2NOP2NOP2NOP2
(
)(
)
(
)(
)
A[9:0],
A[12:11] ROW
tAH5
tAS
tAH
tAS
CODE
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
A10 ROW
CODE
(
)(
)
(
)(
)
(
)(
)
(
)(
)
ALL BANKS
SINGLE BANK
(
)(
)
(
)(
)
(
)(
)
(
)(
)
DON’T CARE
UNDEFINED
T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3
Notes: 1. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
2. If CS is HIGH at clock HIGH time, all commands applied are NOP.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at tP + 1.
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Mode Register
The mode register defines the specific mode of operation, including burst length (BL),
burst type, CAS latency (CL), operating mode, and write burst mode. The mode register
is programmed via the LOAD MODE REGISTER command and retains the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify
the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and
M10–Mn should be set to zero to ensure compatibility with future revisions. Mn + 1 and
Mn + 2 should be set to zero to select the mode register.
The mode registers must be loaded when all banks are idle, and the controller must wait
tMRD before initiating the subsequent operation. Violating either of these requirements
will result in unspecified operation.
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Mode Register
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Figure 13: Mode Register Definition
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
–
0
–
Defined
–
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst LengthCAS Latency BT
A9 A7 A6 A5 A4 A3
A8 A2 A1 A0
Mode Register (Mx)
Address Bus
76543
821 0
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8 M7
Op Mode
A10
A11
10
11
Reserved WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
Program
BA1, BA0 = “0, 0”
to ensure compatibility
with future devices.
A12
12 9
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Burst Length
Read and write accesses to the device are burst oriented, and the burst length (BL) is
programmable. The burst length determines the maximum number of column loca-
tions that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2,
4, 8, or continuous locations are available for both the sequential and the interleaved
burst types, and a continuous page burst is available for the sequential type. The con-
tinuous page burst is used in conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with fu-
ture versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst wraps within the block when a boundary is reached. The block
is uniquely selected by A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8.
The remaining (least significant) address bit(s) is (are) used to select the starting loca-
tion within the block. Continuous page bursts wrap within the page when the boundary
is reached.
Burst Type
Accesses within a given burst can be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst
type, and the starting column address.
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Table 18: Burst Definition Table
Burst Length Starting Column Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
2 A0
0 0-1 0-1
1 1-0 1-0
4 A1 A0
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8 A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Continuous
n = A0–An/9/8 (location 0–y) Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1,
Cn...
Not supported
Notes: 1. For full-page accesses: y = 2048 (x4); y = 1024 (x8); y = 512 (x16).
2. For BL = 2, A1–A9, A11 (x4); A1–A9 (x8); or A1–A8 (x16) select the block-of-two burst; A0
selects the starting column within the block.
3. For BL = 4, A2–A9, A11 (x4); A2–A9 (x8); or A2–A8 (x16) select the block-of-four burst;
A0–A1 select the starting column within the block.
4. For BL = 8, A3–A9, A11 (x4); A3–A9 (x8); or A3–A8 (x16) select the block-of-eight burst;
A0–A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0–A9, A11 (x4); A0–A9 (x8); or A0–A8
(x16) select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the fol-
lowing access wraps within the block.
7. For BL = 1, A0–A9, A11 (x4); A0–A9 (x8); or A0–A8 (x16) select the unique column to be
accessed, and mode register bit M3 is ignored.
64Mb: x32 SDRAM
Mode Register
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CAS Latency
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the
data is valid by clock edge n + m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ command is registered at T0 and
the latency is programmed to two clocks, the DQ start driving after T1 and the data is
valid by T2.
Reserved states should not be used as unknown operation or incompatibility with fu-
ture versions may result.
Figure 14: CAS Latency
CLK
DQ
T2T1 T3T0
CL = 3
tLZ
DOUT
tOH
Command NOPREAD NOP
T4
NOP
Don’t Care Undefined
CLK
DQ
T2T1 T3T0
CL = 2
tLZ
DOUT
tOH
Command NOPREAD
tAC
tAC
NOP
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use. Reserved states should not
be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M[2:0] applies to both READ and
WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
64Mb: x32 SDRAM
Mode Register
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Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a
row in that bank must be opened. This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated.
After a row is opened with the ACTIVE command, a READ or WRITE command can be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is reflected in Figure 15 (page 43), which covers
any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been precharged. The minimum time interval between
successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVE commands to different banks is defined
by tRRD.
Figure 15: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3
CLK
T2T1 T3T0
t
Command NOPACTIVE READ or
WRITE
NOP
RCD(MIN)
tCK tCK tCK
Don’t Care
64Mb: x32 SDRAM
Bank/Row Activation
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READ Operation
READ bursts are initiated with a READ command, as shown in Figure 9 (page 27). The
starting column and bank addresses are provided with the READ command, and auto
precharge is either enabled or disabled for that burst access. If auto precharge is ena-
bled, the row being accessed is precharged at the completion of the burst. In the follow-
ing figures, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address is
available following the CAS latency after the READ command. Each subsequent data-
out element will be valid by the next positive clock edge. Figure 17 (page 46) shows
general timing for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
signals will go to High-Z. A continuous page burst continues until terminated. At the
end of the page, it wraps to column 0 and continues.
Data from any READ burst can be truncated with a subsequent READ command, and
data from a fixed-length READ burst can be followed immediately by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst either follows the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ com-
mand should be issued x cycles before the clock edge at which the last desired data ele-
ment is valid, where x = CL - 1. This is shown in Figure 17 (page 46) for CL2 and CL3.
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule as-
sociated with a prefetch architecture. A READ command can be initiated on any clock
cycle following a READ command. Full-speed random read accesses can be performed
to the same bank, or each subsequent READ can be performed to a different bank.
64Mb: x32 SDRAM
READ Operation
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Figure 16: Consecutive READ Bursts
Don’t Care
CLK
DQ DOUT
n
T2T1 T4T3 T6T5T0
Command
Address
READ NOP NOP NOP NOP
Bank,
Col n
NOP
Bank,
Col b
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
DOUT
b
READ
X = 1 cycle
CL = 2
CLK
DQ DOUT
T2T1 T4T3 T6T5T0
Command
Address
READ NOP NOP NOP NOP
Bank,
Col n
NOP
Bank,
Col b
DOUT DOUT DOUT DOUT
READ NOP
T7
CL = 3 Transitioning data
X = 2 cycles
Note: 1. Each READ command can be issued to any bank. DQM is LOW.
64Mb: x32 SDRAM
READ Operation
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Figure 17: Random READ Accesses
CLK
DQ
T2T1 T4T3 T6T5T0
Command
Address
Don’t Care
DOUT DOUT DOUT DOUT
CLK
DQ
T2T1 T4T3 T5T0
Command
Address
READ NOP
Bank,
Col n
READ READ READ NOP
Bank,
Col a
Bank,
Col x
Bank,
Col m
READ NOP
Bank,
Col n
Bank,
Col a
READ READ READ NOP NOP
Bank,
Col x
Bank,
Col m
CL = 2
CL = 3
DOUT DOUT DOUT DOUT
Transitioning data
Note: 1. Each READ command can be issued to any bank. DQM is LOW.
Data from any READ burst can be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst can be followed immediately by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst can be ini-
tiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there is a possibility that the device driving the input data will go Low-Z before
the DQ go High-Z. In this case, at least a single-cycle delay should occur between the
last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figure 18 (page 47) and
Figure 19 (page 48). The DQM signal must be asserted (HIGH) at least two clocks prior
to the WRITE command (DQM latency is two clocks for output buffers) to suppress da-
ta-out from the READ. After the WRITE command is registered, the DQ will go to High-Z
(or remain High-Z), regardless of the state of the DQM signal, provided the DQM was
active on the clock just prior to the WRITE command that truncated the READ com-
mand. If not, the second WRITE will be an invalid WRITE. For example, if DQM was
LOW during T4, then the WRITEs at T5 and T7 would be valid, and the WRITE at T6
would be invalid.
64Mb: x32 SDRAM
READ Operation
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The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 18
(page 47) shows where, due to the clock cycle frequency, bus contention is avoided
without having to add a NOP cycle, while Figure 19 (page 48) shows the case where an
additional NOP cycle is required.
A fixed-length READ burst may be followed by or truncated with a PRECHARGE com-
mand to the same bank, provided that auto precharge was not activated. The PRE-
CHARGE command should be issued x cycles before the clock edge at which the last de-
sired data element is valid, where x = CL - 1. This is shown in Figure 20 (page 48) for
each possible CL; data element n + 3 is either the last of a burst of four or the last de-
sired data element of a longer burst. Following the PRECHARGE command, a subse-
quent command to the same bank cannot be issued until tRP is met. Note that part of
the row precharge time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-
mand issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvant-
age of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or continuous
page bursts.
Figure 18: READ-to-WRITE
READ NOP NOP WRITE
NOP
CLK
T2T1 T4T3T0
DQM
DQ
Command
Address
Bank,
Col b
Bank,
Col n
DS
tHZ
tCK
Don’t Care
Transitioning data
t
DOUT DIN
Note: 1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
to any bank. If a burst of one is used, DQM is not required.
64Mb: x32 SDRAM
READ Operation
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Figure 19: READ-to-WRITE With Extra Clock Cycle
Don’t Care
READ NOP NOPNOP NOP
DQM
CLK
DQ DOUT
T2T1 T4T3T0
Command
Address Bank,
Col n
WRITE
DIN
Bank,
Col b
T5
tDS
tHZ
Transitioning data
Note: 1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be
to any bank.
Figure 20: READ-to-PRECHARGE
Don’t Care
CLK
DQ
T2T1 T4T3 T6T5T0
Command
Address
READ NOP NOP NOP NOPNOP PRECHARGE ACTIVE
tRP
T7
CLK
DQ DOUT
T2T1 T4T3 T6T5T0
Command
Address
READ NOP NOP NOP NOPNOP
DOUT DOUT DOUT
PRECHARGE ACTIVE
tRP
T7
X = 1 cycle
CL = 2
CL = 3
X = 2 cycles
Bank
a
,
Col
n
Bank
a
,
Row
Bank
(
a
or all)
Bank
a
,
Col
Bank
a
,
Row
Bank
(
a
or all)
Transitioning data
DOUT DOUT DOUT DOUT
Note: 1. DQM is LOW.
64Mb: x32 SDRAM
READ Operation
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Continuous-page READ bursts can be truncated with a BURST TERMINATE command
and fixed-length READ bursts can be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 21 (page 49) for each possible CAS la-
tency; data element n + 3 is the last desired data element of a longer burst.
Figure 21: Terminating a READ Burst
CLK
DQ
T2T1 T4T3 T6T5T0
Command
Address
NOP NOP NOP NOPNOP BURST
TERMINATE NOP
T7
CLK
DQ DOUT
T2T1 T4T3 T6T5T0
Command
Address
READ NOP NOP NOPNOP
DOUT DOUT DOUT
BURST
TERMINATE NOP
X = 1 cycle
CL = 2
CL = 3
X = 2 cycles
Don’t CareTransitioning data
Bank,
Col n
READ
Bank,
Col n
DOUT DOUT DOUT DOUT
Note: 1. DQM is LOW.
64Mb: x32 SDRAM
READ Operation
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Figure 22: Alternating Bank Read Accesses
Don’t Care Undefined
Enable auto precharge
tCH
tCL
tCK
tAC
tLZ
CLK
DQ
A10
tOH
DOUT
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
Row
Row
Row
Row
tOH
DOUT
tAC
tOH
tAC
tOH
tAC
DOUT
DOUT
Command
tCMH
tCMS
NOP NOPACTIVE NOP READ NOP ACTIVE
tOH
DOUT
tAC tAC
READ
Enable auto precharge
Row
ACTIVE
Row
Bank 0 Bank 0 Bank 3 Bank 3 Bank 0
CKE
tCKH
tCKS
Column m Column b1
T0 T1 T2 T4T3 T5 T6 T7 T8
tRP - bank 0
tRAS - bank 0
tRCD - bank 0 tRCD - bank 0
CL - bank 0
tRCD - bank 3 CL - bank 3
tRC - bank 0
tRRD
BA0, BA1
DQM
Address
Note: 1. For this example, BL = 4 and CL = 2.
64Mb: x32 SDRAM
READ Operation
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Figure 23: READ Continuous Page Burst
tCH
tCL tCK
tAC
tLZ
tRCD CAS latency
CKE
CLK
DQ
A10
tOH
DOUT
tCMH
tCMS
tAH
tAS
tAH
tAS
tAC
tOH
DOUT
Row
Row
tHZ
t
AC
tOH
DOUT
tAC
tOH
DOUT
tAC
tOH
DOUT
tAC
tOH
DOUT
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
Full page completed
All locations within same row
Don’t Care
Undefined
Command
tCMH
tCMS
NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP
(
)(
)
(
)(
)
NOP
(
)(
)
(
)(
)
tAH
tAS
Bank
(
)(
)
(
)(
)
Bank
tCKH
tCKS
(
)(
)
(
)(
)
(
)(
)
(
)(
)
Column m
T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4
BA0, BA1
DQM
Address
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
Note: 1. For this example, CL = 2.
64Mb: x32 SDRAM
READ Operation
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Figure 24: READ – DQM Operation
tCH
tCL
tCK
tAC
tAC
tLZ
tRCD CL = 2
CKE
CLK
DQ
A10
tOH
DOUT
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
Row
Bank
Row
Bank
tHZ
tAC
tLZ
tOH
DOUT
tOH
DOUT
tHZ
Command
tCMH
tCMS
NOPNOPNOP NOPACTIVE NOP READ NOP NOP
Disable auto precharge
Enable auto precharge
Don’t Care
Undefined
tCKH
tCKS
Column m
T0 T1 T2 T4T3 T5 T6 T7 T8
BA0, BA1
DQM
Address
Note: 1. For this example, BL = 4 and CL = 2.
64Mb: x32 SDRAM
READ Operation
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WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 10 (page 28).
The starting column and bank addresses are provided with the WRITE command and
auto precharge is either enabled or disabled for that access. If auto precharge is ena-
bled, the row being accessed is precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following figures, auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered coincident with the
WRITE command. Subsequent data elements are registered on each successive positive
clock edge. Upon completion of a fixed-length burst, assuming no other commands
have been initiated, the DQ will remain at High-Z and any additional input data will be
ignored (see Figure 25 (page 53)). A continuous page burst continues until terminated;
at the end of the page, it wraps to column 0 and continues.
Data for any WRITE burst can be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst can be followed immediately by data for a WRITE
command. The new WRITE command can be issued on any clock following the previ-
ous WRITE command, and the data provided coincident with the new command ap-
plies to the new command (see Figure 26 (page 54)). Data n + 1 is either the last of a
burst of two or the last desired data element of a longer burst.
SDRAM devices use a pipelined architecture and therefore do not require the 2n rule as-
sociated with a prefetch architecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed random write accesses within a
page can be performed to the same bank, as shown in Figure 27 (page 55), or each
subsequent WRITE can be performed to a different bank.
Figure 25: WRITE Burst
CLK
DQ DIN
T2T1 T3T0
Command
Address
NOP NOP
Don’t Care
WRITE
DIN
NOP
Bank,
Col n
Transitioning data
Note: 1. BL = 2. DQM is LOW.
64Mb: x32 SDRAM
WRITE Operation
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Figure 26: WRITE-to-WRITE
CLK
DQ
T2T1T0
Command
Address
NOPWRITE WRITE
Bank,
Col n
Bank,
Col b
DIN DIN DIN
Don’t Care
Transitioning data
Note: 1. DQM is LOW. Each WRITE command may be issued to any bank.
Data for any WRITE burst can be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst can be followed immediately by a READ command.
After the READ command is registered, data input is ignored and WRITEs will not be
executed (see Figure 28 (page 55)). Data n + 1 is either the last of a burst of two or the
last desired data element of a longer burst.
Data for a fixed-length WRITE burst can be followed by or truncated with a PRE-
CHARGE command to the same bank, provided that auto precharge was not activated.
A continuous-page WRITE burst can be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be issued tWR after the clock edge at
which the last desired input data element is registered. The auto precharge mode re-
quires a tWR of at least one clock with time to complete, regardless of frequency.
In addition, when truncating a WRITE burst at high clock frequencies (tCK < 15ns), the
DQM signal must be used to mask input data for the clock edge prior to and the clock
edge coincident with the PRECHARGE command (see Figure 29 (page 56)). Data n + 1
is either the last of a burst of two or the last desired data element of a longer burst. Fol-
lowing the PRECHARGE command, a subsequent command to the same bank cannot
be issued until tRP is met.
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-
mand issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvant-
age of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts or continu-
ous page bursts.
64Mb: x32 SDRAM
WRITE Operation
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Figure 27: Random WRITE Cycles
Don’t Care
CLK
DQ DIN
T2T1 T3T0
Command
Address
WRITE
Bank,
Col n
DIN DIN DIN
WRITE WRITE WRITE
Bank,
Col a
Bank,
Col x
Bank,
Col m
Transitioning data
Note: 1. Each WRITE command can be issued to any bank. DQM is LOW.
Figure 28: WRITE-to-READ
Don’t Care
CLK
DQ
T2T1 T3T0
Command
Address
NOPWRITE
Bank,
Col n
DIN DIN DOUT
READ NOP NOP
Bank,
Col b
NOP
DOUT
T4 T5
Transitioning data
Note: 1. The WRITE command can be issued to any bank, and the READ command can be to any
bank. DQM is LOW. CL = 2 for illustration.
64Mb: x32 SDRAM
WRITE Operation
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Figure 29: WRITE-to-PRECHARGE
Don’t Care
DQM
CLK
DQ
T2T1 T4T3T0
Command
Address Bank a,
Col n
T5
NOPWRITE PRECHARGE NOPNOP
DIN DIN
ACTIVE
tRP
Bank
(a or all)
tWR
Bank a,
Row
DQM
DQ
Command
Address Bank a,
Col n
NOPWRITE PRECHARGE NOPNOP ACTIVE
tRP
Bank
(a or all)
tWR
Bank a,
Row
T6
NOP
NOP
tWR @ tCK < 15ns
tWR @ tCK ≥ 15ns
DIN DIN
Transitioning data
Note: 1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two.
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command is ignored. The last data written (provided that DQM is LOW at
that time) will be the input data applied one clock previous to the BURST TERMINATE
command. This is shown in Figure 30 (page 57), where data n is the last desired data
element of a longer burst.
64Mb: x32 SDRAM
WRITE Operation
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Figure 30: Terminating a WRITE Burst
Don’t Care
CLK
DQ
T2T1T0
Command
Address Bank,
Col n
WRITE BURST
TERMINATE
NEXT
COMMAND
DIN
Address
Data
Transitioning data
Note: 1. DQM is LOW.
64Mb: x32 SDRAM
WRITE Operation
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Figure 31: Alternating Bank Write Accesses
Don’t Care
Enable auto precharge
tCH
tCL
tCK
CLK
DQ
A10
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
Row
Row
Row
Row
Command
tCMH
tCMS
NOP NOPACTIVE NOP WRITE NOPNOP ACTIVEWRITE
Enable auto precharge
Row
ACTIVE
Row
Bank 0 Bank 0 Bank 1 Bank 1 Bank 0
CKE
tCKH
tCKS
Column m Column b
T0 T1 T2 T4T3 T5 T6 T7 T8 T9
tRP - bank 0
tRAS - bank 0
tRCD - bank 0 tRCD - bank 0
tWR - bank 1
tWR - bank 0
tRCD - bank 1
tRC - bank 0
tRRD
BA0, BA1
DQM
Address
DIN
tDH
tDS
DIN DIN DIN
tDH
tDS tDH
tDS tDH
tDS
DIN
tDH
tDS
DIN
tDH
tDS
DIN
tDH
tDS
DIN
tDH
tDS
Note: 1. For this example, BL = 4.
64Mb: x32 SDRAM
WRITE Operation
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Figure 32: WRITE – Continuous Page Burst
tCH
tCL tCK
tRCD
CKE
CLK
A10
tCMS
tAH
tAS
tAH
tAS
Row
Row
Full-page burst
does not self-terminate.
Use BURST TERMINATE
command to stop.1, 2
(
)(
)
(
)(
)
(
)(
)
(
)(
)
Full page completed Don’t Care
Command
tCMH
tCMS
NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP
(
)(
)
(
)(
)
(
)(
)
(
)(
)
DQ
DIN
tDH
tDS
DIN DIN DIN
tDH
tDS tDH
tDS tDH
tDS
DIN
tDH
tDS
tAH
tAS
Bank
(
)(
)
(
)(
)
Bank
tCMH
tCKH
tCKS
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
All locations within same row
Column
m
T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3
BA0, BA1
DQM
Address
Notes: 1. tWR must be satisfied prior to issuing a PRECHARGE command.
2. Page left open; no tRP.
64Mb: x32 SDRAM
WRITE Operation
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Figure 33: WRITE – DQM Operation
Don’t Care
tCH
tCL
tCK
tRCD
CKE
CLK
DQ
A10
tCMS
tAH
tAS
Row
Bank
Row
Bank
Enable auto precharge
DIN
tDH
tDS
DIN DIN
tCMH
Command NOPNOP NOP
ACTIVE NOP WRITE NOPNOP
tCMS tCMH
tDH
tDS
tDH
tDS
tAH
tAS
tAH
tAS
Disable auto precharge
tCKH
tCKS
Column m
T0 T1 T2 T3 T4 T5 T6 T7
BA0, BA1
DQM
Address
Note: 1. For this example, BL = 4.
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of the programmed burst length.
READ commands access columns according to the programmed burst length and se-
quence, just as in the normal mode of operation (M9 = 0).
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WRITE Operation
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PRECHARGE Operation
The PRECHARGE command (see Figure 11 (page 29)) is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s) will be available for a sub-
sequent row access some specified time (tRP) after the PRECHARGE command is is-
sued. Input A10 determines whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged (A10 = LOW), inputs BA0 and BA1 select
the bank. When all banks are to be precharged (A10 = HIGH), inputs BA0 and BA1 are
treated as “Don’t Care.” After a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands being issued to that bank.
Auto Precharge
Auto precharge is a feature that performs the same individual-bank PRECHARGE func-
tion described previously, without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst,
except in the continuous page burst mode where auto precharge does not apply. In the
specific case of write burst mode set to single location access with burst length set to
continuous, the burst length setting is the overriding setting and auto precharge does
not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for
each individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. Another command cannot be issued to the same bank until the precharge time
(tRP) is completed. This is determined as if an explicit PRECHARGE command was is-
sued at the earliest possible time, as described for each burst type in the Burst Type
(page 40) section.
Micron SDRAM supports concurrent auto precharge; cases of concurrent auto pre-
charge for READs and WRITEs are defined below.
READ with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a READ on bank n following the programmed CAS la-
tency. The precharge to bank n begins when the READ to bank m is registered (see Fig-
ure 34 (page 62)).
READ with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The pre-
charge to bank n begins when the WRITE to bank m is registered (see Figure 35
(page 63)).
WRITE with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out
appearing CL later. The precharge to bank n will begin after tWR is met, where tWR be-
gins when the READ to bank m is registered. The last valid WRITE to bank n will be da-
ta-in registered one clock prior to the READ to bank m (see Figure 40 (page 68)).
WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to
bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is reg-
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PRECHARGE Operation
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istered. The last valid data WRITE to bank n will be data registered one clock prior to a
WRITE to bank m (see Figure 41 (page 68)).
Figure 34: READ With Auto Precharge Interrupted by a READ
Don’t Care
CLK
DQ DOUT
T2T1 T4T3 T6T5T0
Command READ - AP
Bank n NOP NOPNOPNOP
DOUT DOUT DOUT
NOP
T7
Bank n
CL = 3 (bank m)
Bank m
Address
Idle
NOP
Bank n,
Col a
Bank m,
Col d
READ - AP
Bank m
Internal
states
t
Page active READ with burst of 4 Interrupt burst, precharge
Page active READ with burst of 4 Precharge
RP - bank n tRP - bank m
CL = 3 (bank n)
Note: 1. DQM is LOW.
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PRECHARGE Operation
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Figure 35: READ With Auto Precharge Interrupted by a WRITE
CLK
DQ DOUT
T2T1 T4T3 T6T5T0
Command NOPNOPNOPNOP
DIN
DIN DIN DIN
NOP
T7
Bank n
Bank m
Address
Idle
NOP
DQM1
Bank n,
Col a
Bank m,
Col d
WRITE - AP
Bank m
Internal
States
t
Page
active READ with burst of 4 Interrupt burst, precharge
Page active WRITE with burst of 4 Write-back
RP -
bank
n
tWR - bank m
CL = 3 (bank n)
READ - AP
Bank n
Don’t CareTransitioning data
Note: 1. DQM is HIGH at T2 to prevent DOUTa + 1 from contending with DINd at T4.
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PRECHARGE Operation
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Figure 36: READ With Auto Precharge
tCH
tCL
tCK
tAC
tLZ
tRP
tRAS
tRCD CL = 2
tRC
CKE
CLK
DQ
A10
tOH
DOUT m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
Row
Row
Bank Bank
Row
Row
Bank
tHZ
tOH
DOUT
m + 3
tAC
tOH
tAC
tOH
tAC
DOUT
m + 2
DOUT
m + 1
Command
tCMH
tCMS
NOPNOPNOP NOPACTIVE NOP READ NOP ACTIVE
Enable auto precharge
Don’t Care Undefined
tCKH
tCKS
Column m
T0 T1 T2 T4T3 T5 T6 T7 T8
BA0, BA1
DQM
Address
Note: 1. For this example, BL = 4 and CL = 2.
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PRECHARGE Operation
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Figure 37: READ Without Auto Precharge
tCH
tCL
tCK
tAC
tLZ
tRP
tRAS
tRCD CL = 2
tRC
CKE
CLK
DQ
A10
tOH
DOUT
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
Row
Row
Bank Bank(s) Bank
Row
Row
Bank
tHZ
tOH
DOUT
tAC
tOH
tAC
tOH
tAC
DOUT
DOUT
Command
tCMH
tCMS
PRECHARGENOPNOP NOPACTIVE NOP READ NOP ACTIVE
Disable auto precharge Single bank
All banks
Don’t Care Undefined
tCKH
tCKS
Column m
T0 T1 T2 T4T3 T5 T6 T7 T8
BA0, BA1
DQM
Address
Note: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRE-
CHARGE.
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PRECHARGE Operation
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Figure 38: Single READ With Auto Precharge
tCH
tCL
tCK
tAC tOH
tLZ
tRP
tRAS
tRCD CL = 2
tRC
CKE
CLK
DQ
A10
DOUT
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
Row
Row
Bank Bank
Row
Row
Bank
Command
tCMH
tCMS
NOPNOPNOP NOPACTIVE NOP READ ACTIVE
Enable auto precharge
Don’t Care Undefined
tCKH
tCKS
Column m
T0 T1 T2 T4T3 T5 T6 T7
BA0, BA1
DQM
Address
Note: 1. For this example, BL = 1 and CL = 2.
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PRECHARGE Operation
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Figure 39: Single READ Without Auto Precharge
All banks
tCH
tCL
tCK
tAC
tLZ
tRP
tRAS
tRCD CL = 2
tRC
CKE
CLK
DQ
A10
tOH
DOUT
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
Row
Row
Bank Bank(s) Bank
Row
Row
Bank
tHZ
Command
tCMH
tCMS
NOPNOPNOP PRECHARGE
ACTIVE NOP READ ACTIVE NOP
Disable auto precharge Single bank
Don’t Care
Undefined
tCKH
tCKS
Column m
T0 T1 T2 T4T3 T5 T6 T7 T8
BA0, BA1
DQM
Address
Note: 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRE-
CHARGE.
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PRECHARGE Operation
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Figure 40: WRITE With Auto Precharge Interrupted by a READ
Don’t Care
CLK
DQ
T2T1 T4T3 T6T5T0
Command WRITE - AP
Bank n NOPNOPNOPNOP
DIN
DIN
NOP NOP
T7
Bank n
Bank m
Address Bank n,
Col a
Bank m,
Col d
READ - AP
Bank m
Internal
States
t
Page active WRITE with burst of 4 Interrupt burst, write-back Precharge
Page active READ with burst of 4
t
tRP - bank m
DOUT DOUT
CL = 3 (bank m)
RP - bank n
WR - bank n
Note: 1. DQM is LOW.
Figure 41: WRITE With Auto Precharge Interrupted by a WRITE
Don’t Care
CLK
DQ
T2T1 T4T3 T6T5T0
Command WRITE - AP
Bank n NOPNOPNOPNOP
DIN
DIN
DIN DIN
DIN DIN DIN
NOP
T7
Bank n
Bank m
Address
NOP
Bank n,
Col a
Bank m,
Col d
WRITE - AP
Bank m
Internal
States
t
Page active WRITE with burst of 4 Interrupt burst, write-back Precharge
Page active WRITE with burst of 4 Write-back
WR - bank n tRP - bank n
tWR - bank m
Note: 1. DQM is LOW.
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PRECHARGE Operation
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Figure 42: WRITE With Auto Precharge
Enable auto precharge
tCH
tCL
tCK
tRP
tRAS
tRCD
tRC
CKE
CLK
DQ
A10
tCMH
tCMS
tAH
tAS
Row
Bank
Row
Bank
tWR
Don’t Care
DIN
tDH
tDS
DIN DIN DIN
Command
t
CMH
t
CMS
NOPNOP NOPACTIVE NOP WRITE NOPNOP NOP
Row
Bank
Row
tAH
tAS
tAH
tAS
tDH
tDS tDH
tDS tDH
tDS
tCKH
tCKS
Column m
T0 T1 T2 T4T3 T5 T6 T7 T8 T9
DQM
BA0, BA1
Address
ACTIVE
Note: 1. For this example, BL = 4.
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PRECHARGE Operation
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Figure 43: WRITE Without Auto Precharge
Disable auto precharge
All banks
tCH
tCL
tCK
tRP
tRAS
tRCD
tRC
CKE
CLK
DQ
A10
tCMH
tCMS
tAH
tAS
Row
Bank Bank
Row
Bank
tWR
Don’t Care
DIN
tDH
tDS
DIN DIN DIN
Command
t
CMH
t
CMS
NOPNOP NOPACTIVE NOP WRITE PRECHARGENOP NOP
Row
Bank
Row
tAH
tAS
tAH
tAS
tDH
tDS tDH
tDS tDH
tDS
Single bank
tCKH
tCKS
Column m
T0 T1 T2 T4T3 T5 T6 T7 T8 T9
DQM
BA0, BA1
Address
ACTIVE
Note: 1. For this example, BL = 4 and the WRITE burst is followed by a manual PRECHARGE.
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PRECHARGE Operation
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Figure 44: Single WRITE With Auto Precharge
Enable auto precharge
tCH
tCL
tCK
tRP
tRAS
tRCD
tRC
CKE
CLK
DQ
A10
tCMH
tCMS
tAH
tAS
Row
Bank
Row
Bank
tWR
Don’t Care
DIN
tDH
tDS
Command
t
CMH
t
CMS
NOPNOP NOPACTIVE NOP WRITE NOP NOP
Row
Bank
Row
tAH
tAS
tAH
tAS
tCKH
tCKS
Column m
T0 T1 T2 T4T3 T5 T6 T7 T8
DQM
BA0, BA1
Address
ACTIVE
Note: 1. For this example, BL = 1.
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PRECHARGE Operation
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Figure 45: Single WRITE Without Auto Precharge
tCH
tCL
tCK
tRP
tRAS
tRCD tWR
tRC
CKE
CLK
DQ
A10
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
Row
Bank Bank Bank
Row
Row
Bank
Command
tCMH
tCMS
NOPNOPNOP PRECHARGEACTIVE NOP WRITE ACTIVE NOP
Disable auto precharge
Don’t Care
tCKH
tCKS
Column m
T0 T1 T2 T4T3 T5 T6 T7 T8
BA0, BA1
DQM
Address
DIN
tDH
tDS
All banks
Single bank
Note: 1. For this example, BL = 1 and the WRITE burst is followed by a manual PRECHARGE.
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PRECHARGE Operation
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AUTO REFRESH Operation
The AUTO REFRESH command is used during normal operation of the device to refresh
the contents of the array. This command is nonpersistent, so it must be issued each
time a refresh is required. All active banks must be precharged prior to issuing an AUTO
REFRESH command. The AUTO REFRESH command should not be issued until the
minimum tRP is met following the PRECHARGE command. Addressing is generated by
the internal refresh controller. This makes the address bits “Don’t Care” during an AU-
TO REFRESH command.
After the AUTO REFRESH command is initiated, it must not be interrupted by any exe-
cutable command until tRFC has been met. During tRFC time, COMMAND INHIBIT or
NOP commands must be issued on each positive edge of the clock. The SDRAM re-
quires that every row be refreshed each tREF period. Providing a distributed AUTO RE-
FRESH command—calculated by dividing the refresh period (tREF) by the number of
rows to be refreshed—meets the timing requirement and ensures that each row is re-
freshed. Alternatively, to satisfy the refresh requirement a burst refresh can be employed
after every tREF period by issuing consecutive AUTO REFRESH commands for the num-
ber of rows to be refreshed at the minimum cycle rate (tRFC).
64Mb: x32 SDRAM
AUTO REFRESH Operation
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Figure 46: Auto Refresh Mode
All banks
Don’t Care
tCH
tCL
tCK
CKE
CLK
DQ
tRFC
(
)(
)
(
)(
)
tRP
(
)(
)
(
)(
)
Command
tCMH
tCMS
NOPNOP
(
)(
)
(
)(
)
Bank
ACTIVE
AUTO
REFRESH
(
)(
)
(
)(
)
NOPNOPPRECHARGE
Precharge all
active banks
AUTO
REFRESH
tRFC
High-Z
Bank(s)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
tAH
tAS
tCKH
tCKS
NOP
(
)(
)
(
)(
)
(
)(
)
(
)(
)
Row
(
)(
)
(
)(
)
Single bank
A10
Row
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
T0 T1 T2 Tn + 1 To + 1
BA0, BA1
Address
DQM
(
)(
)(
)(
)
(
)(
)(
)(
)
Note: 1. Back-to-back AUTO REFRESH commands are not required.
64Mb: x32 SDRAM
AUTO REFRESH Operation
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SELF REFRESH Operation
The self refresh mode can be used to retain data in the device, even when the rest of the
system is powered down. When in self refresh mode, the device retains data without ex-
ternal clocking. The SELF REFRESH command is initiated like an AUTO REFRESH com-
mand, except CKE is disabled (LOW). After the SELF REFRESH command is registered,
all the inputs to the device become “Don’t Care” with the exception of CKE, which must
remain LOW.
After self refresh mode is engaged, the device provides its own internal clocking, ena-
bling it to perform its own AUTO REFRESH cycles. The device must remain in self re-
fresh mode for a minimum period equal to tRAS and remains in self refresh mode for an
indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK
must be stable prior to CKE going back HIGH. (Stable clock is defined as a signal cycling
within timing constraints specified for the clock ball.) After CKE is HIGH, the device
must have NOP commands issued for a minimum of two clocks for tXSR because time is
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued accord-
ing to the distributed refresh rate (tREF/refresh row count) as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.
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SELF REFRESH Operation
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Figure 47: Self Refresh Mode
All banks
tCH
tCL
t
CK
tRP
CKE
CLK
DQ
Enter self refresh mode
Precharge all
active banks
tXSR
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
(
)(
)(
)(
)
(
)(
)
Don’t Care
Command
tCMH
tCMS
AUTO
REFRESH
PRECHARGE NOP NOP
Bank(s)
High-Z
tCKS
tAH
tAS
AUTO
REFRESH
tCKH
tCKS
A10
T0 T1 T2 Tn + 1 To + 1 To + 2
BA0, BA1
DQM
Address
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
(
)(
)
Single bank
Note: 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are
not required.
64Mb: x32 SDRAM
SELF REFRESH Operation
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Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-
HIBIT when no accesses are in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-
down deactivates the input and output buffers, excluding CKE, for maximum power
savings while in standby. The device cannot remain in the power-down state longer
than the refresh period (64ms) because no REFRESH operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE
HIGH at the desired clock edge (meeting tCKS).
Figure 48: Power-Down Mode
All banks
tCH
tCL
tCK
Two clock cycles
CKE
CLK
DQ
All banks idle, enter
power-down mode
Precharge all
active banks
Input buffers gated off
while in power-down mode
Exit power-down mode
(
)(
)
Don’t Care
tCKS tCKS
Command
tCMH
tCMS
PRECHARGE NOP NOP ACTIVENOP
(
)(
)
(
)(
)
All banks idle
BA0, BA1 Bank
Bank(s)
(
)(
)
(
)(
)
High-Z
tAH
tAS
tCKH
tCKS
DQM
(
)(
)
(
)(
)
(
)(
)
(
)(
)
Address Row
(
)(
)
(
)(
)
Single bank
A10 Row
(
)(
)
(
)(
)
T0 T1 T2 Tn + 1 Tn + 2
(
)(
)
Note: 1. Violating refresh requirements during power-down may result in a loss of data.
64Mb: x32 SDRAM
Power-Down
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Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls when an in-
ternal clock edge is suspended will be ignored; any data present on the DQ balls re-
mains driven; and burst counters are not incremented, as long as the clock is suspen-
ded.
Exit clock suspend mode by registering CKE HIGH; the internal clock and related opera-
tion will resume on the subsequent positive clock edge.
Figure 49: Clock Suspend During WRITE Burst
Don’t Care
DIN
Command
Address
WRITE
Bank,
Col n
DIN
NOPNOP
CLK
T2T1 T4T3 T5T0
CKE
Internal
clock
NOP
DIN DIN
Note: 1. For this example, BL = 4 or greater, and DQM is LOW.
64Mb: x32 SDRAM
Clock Suspend
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Figure 50: Clock Suspend During READ Burst
Don’t Care
CLK
DQ DOUT
T2T1 T4T3 T6T5T0
Command
Address
READ NOP NOP NOP
Bank,
Col n
NOP
DOUT DOUT DOUT
CKE
Internal
clock
NOP
Note: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
64Mb: x32 SDRAM
Clock Suspend
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Figure 51: Clock Suspend Mode
tCH
tCL
tCK
tAC
tLZ
DQM
CLK
DQ
A10
tOH
DOUT
tAH
tAS
tAH
tAS
tAH
tAS
Bank
tDH
DIN
tAC
tHZ
DOUT
Command
tCMH
tCMS
NOPNOP NOP NOPNOPREAD WRITE
Don’t Care Undefined
CKE
tCKS tCKH
Bank
Column m
tDS
DIN
NOP
tCKH
tCKS
tCMH
tCMS
Column e
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
BA0, BA1
Address
Note: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
64Mb: x32 SDRAM
Clock Suspend
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© 1999 Micron Technology, Inc. All rights reserved.
