FUJITSU SEMICONDUCTOR DATA SHEET DS05-50219-1E Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS 32 M (x x8/x x16) FLASH MEMORY & 4 M (x x8/x x16) STATIC RAM MB84VD2218XEA/2218XEH-70/85/90 MB84VD2219XEA/2218XEH-70/85/90 FEATURES * Power Supply Voltage of 2.7 V to 3.3 V * High Performance 70 ns/85 ns/90 ns maximum access time (Flash) 70 ns/85 ns maximum access time (SRAM) * Operating Temperature -25 C to +85 C * Package 71-ball BGA (Continued) PRODUCT LINE UP Flash Memory -70 -85 VCCf* = 3.0 V Power Supply Voltage (V) SRAM -90 +0.3 V -0.3 V -70 -85/-90 +0.3 V VCCs* = 3.0 V -0.3 V Max Address Access Time (ns) 70 85 90 70 85 Max CE Access Time (ns) 70 85 90 70 85 Max OE Access Time (ns) 30 35 40 35 45 PACKAGE 71-ball plastic BGA (BGA-71P-M02) MB84VD2218XEA/H/2219XEA/H-70/85/90 (Continued) - FLASH MEMORY * Simultaneous Read/Write Operations (dual bank) Multiple devices available with different bank sizes (Refer to PIN DESCRIPTION) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program * Minimum 100,000 Write/Erase Cycles * Sector Erase Architecture Eight 4 K words and sixty three 32 K words. Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture MB84VD2218X : Top sector MB84VD2219X : Bottom sector * Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready-Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCC Write Inhibit 2.5 V * Hidden ROM (Hi-ROM) Region 64 K byte of Hi-ROM, accessible through a new "Hi-ROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC Input Pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status (MB84VD2218XEA/H : SA69, SA70 MB84VD2219XEA/H : SA0, SA1) At VIH, allows removal of boot sector protection At VACC, program time will reduce by 40%. * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device * Please refer to "MBM29DL32XTE/BE" Datasheet in Detailed Function - SRAM * Power Dissipation Operating : 40 mA Max Standby : 7 A Max * Power Down Features Using CE1s and CE2s * Data Retention Supply Voltage : 1.5 V to 3.3 V * CE1s and CE2s Chip Select * Byte Data Control : LBs (DQ0-DQ7) , UBs (DQ8-DQ15) *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MB84VD2218XEA/H/2219XEA/H-70/85/90 PIN ASSIGNMENT (Top View) Marking side A8 B8 D8 E8 F8 G8 H8 J8 L8 M8 N.C. N.C. A15 N.C. N.C. A16 CIOf VSS N.C. N.C. A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 L7 M7 N.C. N.C. A11 A12 A13 A14 SA DQ15/ A-1 DQ7 DQ14 N.C. N.C. C6 D6 E6 F6 G6 H6 J6 K6 A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5 C5 D5 E5 H5 J5 K5 WE CE2s A20 DQ4 VCCs CIOs C4 D4 E4 H4 J4 K4 DQ3 VCCf DQ11 WP/ RESET RY/BY ACC C3 D3 E3 F3 G3 H3 J3 K3 LBs UBs A18 A17 DQ1 DQ9 DQ10 DQ2 A2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N.C. A7 A6 A5 A4 VSS OE DQ0 DQ8 N.C. N.C. A1 B1 D1 E1 F1 G1 H1 J1 L1 M1 N.C. N.C. A3 A2 A1 A0 CEf CE1s N.C. N.C. (BGA-71P-M02) 3 MB84VD2218XEA/H/2219XEA/H-70/85/90 PIN DESCRIPTION Pin A17 to A0 Input/Output Address Inputs (Common) I A20 to A18, A-1 Address Input (Flash) I SA Address Input (SRAM) I DQ15 to DQ0 Data Inputs/Outputs (Common) I/O CEf Chip Enable (Flash) I CE1s Chip Enable (SRAM) I CE2s Chip Enable (SRAM) I OE Output Enable (Common) I WE Write Enable (Common) I Ready/Busy Outputs (Flash) Open Drain Output O UBs Upper Byte Control (SRAM) I LBs Lower Byte Control (SRAM) I CIOf I/O Configuration (Flash) CIOf = Vccf is Word mode (x16) , CIOf = Vss Byte mode (x8) I CIOs I/O Configuration (SRAM) CIOs = Vccs is Word mode (x16) , CIOs = Vss is Byte mode (x8) I Hardware Reset Pin/Sector Protection Unlock (Flash) I Write Protect/Acceleration (Flash) I RY/BY RESET WP/ACC 4 Function N.C. No Internal Connection VSS Device Ground (Common) Power VCCf Device Power Supply (Flash) Power VCCs Device Power Supply (SRAM) Power MB84VD2218XEA/H/2219XEA/H-70/85/90 BLOCK DIAGRAM VCCf VSS A0 to A20 RY/BY A20 to A0 A-1 WP/ACC RESET CEf CIOf 32 M bit Flash Memory DQ15/A-1 to DQ0 DQ15/A-1 to DQ0 VCCs VSS A0 to A17 SA LBs UBs WE OE CE1s CE2s CIOs 4 M bit Static RAM DQ15 to DQ0 5 MB84VD2218XEA/H/2219XEA/H-70/85/90 DEVICE BUS OPERATION User Bus Operations Table (Flash = Word mode; CIOf = Vccf, SRAM = Word mode; CIOs = Vccs) Operation *1, *3 Full Standby CEf CE1s CE2s OE H H Output Disable L Read from Flash *2 L Write to Flash L Read from SRAM Write to SRAM H H Temporary Sector Group Unprotection *4 X Flash Hardware Reset X Boot Block Sector Write Protection X H X X L L H H X X L H X X L H X X L L L H H X X H X X L X X WE WP/ SA LBs UBs DQ0 to DQ7 DQ8 to DQ15 RESET ACC 6 * *5 X X X X X High-Z High-Z H H X X X High-Z High-Z X X X H H High-Z High-Z H H X X X High-Z High-Z L H X X X DOUT H L X X X L L X H L X X H X H X DOUT H X DIN DIN H X L DOUT DOUT H L High-Z DOUT H X L H DOUT High-Z L L DIN DIN H L High-Z DIN H X L H DIN High-Z X X X X X X X VID X X X X X X High-Z High-Z L X X X X X X X X X L Legend : L = VIL, H = VIH, X = VIL or VIH. See " DC CHARACTERISTICS" for voltage levels. *1: Other operations not indicated in this column are prohibited. *2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. *4: Also used for the extended sector group protections. *5: WP/ACC = VIL; protection of boot sectors. WP/ACC = VIH; removal of boot sectors protection. WP/ACC = VACC (9 V) ; Program time will be reduced by 40%. *6: SA : Don't care or Open. 6 MB84VD2218XEA/H/2219XEA/H-70/85/90 User Bus Operations Table (Flash = Word mode; CIOf = Vccf, SRAM = Byte mode; CIOs = Vss) Operation *1, *3 Full Standby CEf CE1s CE2s OE H H Output Disable L H X X L L H H X X L H X X L H X X L WP/ LBs UBs DQ0 to DQ7 DQ8 to DQ15 RESET ACC 6 6 * * *5 WE SA X X X X X High-Z High-Z H H X X X High-Z High-Z X X X H H High-Z High-Z H H X X X High-Z High-Z L H X X X DOUT H L X X X H X H X DOUT H X DIN DIN H X Read from Flash *2 L Write to Flash L Read from SRAM H L H L H SA X X DOUT High-Z H X Write to SRAM H L H X L SA X X DIN High-Z H X Temporary Sector Group Unprotection *4 X X X X X X X X X X VID X Flash Hardware Reset X H X X L X X X X X High-Z High-Z L X Boot Block Sector Write Protection X X X X X X X X X X X L Legend : L = VIL, H = VIH, X = VIL or VIH. See " DC CHARACTERISTICS" for voltage levels. *1: Other operations not indicated in this column are prohibited. *2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. *4: Also used for the extended sector group protections. *5: WP/ACC = VIL; protection of boot sectors. WP/ACC = VIH; removal of boot sectors protection. WP/ACC = VACC (9 V) ; Program time will be reduced by 40%. *6: LBS , UBS : Don't care or Open. 7 MB84VD2218XEA/H/2219XEA/H-70/85/90 User Bus Operations Table (Flash = Byte mode; CIOf = Vss, SRAM = Byte mode; CIOs = Vss) Operation *1, *3 Full Standby CEf CE1s CE2s DQ15/A-1 OE WE SA H H Output Disable L H X X L L H H X X L H X X L H X X L LBs UBs *6 *6 DQ0 to DQ7 DQ8 to DQ14 X X X X X X High-Z High-Z X H H X X X High-Z High-Z X X X X H H High-Z High-Z A-1 H H X X X High-Z High-Z A-1 L H X X X DOUT A-1 H L X X X H X H X X H X DIN X H X Read from Flash *2 L Write to Flash L Read from SRAM H L H X L H SA X X DOUT High-Z H X Write to SRAM H L H X X L SA X X DIN High-Z H X Temporary Sector Group Unprotection *4 X X X X X X X X X X X VID X Flash Hardware Reset X H X X L X X X X X X High-Z High-Z L X Boot Block Sector Write Protection X X X X X X X X X X X X L Legend : L = VIL, H = VIH, X = VIL or VIH. See " DC CHARACTERISTICS" for voltage levels. *1: Other operations not indicated in this column are prohibited. *2: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. *4: Also used for the extended sector group protections. *5: WP/ACC = VIL ; protection of boot sectors. WP/ACC = VIH ; removal of boot sectors protection. WP/ACC = VACC (9 V) ; Program time will be reduced by 40%. *6: LBS , UBS : Don't care or Open. 8 WP/ RESET ACC *5 MB84VD2218XEA/H/2219XEA/H-70/85/90 FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY * Eight 4 K words, and sixty three 32 K words. * Individual-sector, multiple-sector, or bulk-erase capability. Bank 1 MB84VD22182EA/H Bank 1 MB84VD22183EA/H Bank 1 MB84VD22184EA/H Bank 2 MB84VD22182EA/H Bank 2 MB84VD22183EA/H Bank 2 MB84VD22184EA/H SA70 : 8 KB (4 KW) SA69 : 8 KB (4 KW) SA68 : 8 KB (4 KW) SA67 : 8 KB (4 KW) SA66 : 8 KB (4 KW) SA65 : 8 KB (4 KW) SA64 : 8 KB (4 KW) SA63 : 8 KB (4 KW) SA62 : 64 KB (32 KW) SA61 : 64 KB (32 KW) SA60 : 64 KB (32 KW) SA59 : 64 KB (32 KW) SA58 : 64 KB (32 KW) SA57 : 64 KB (32 KW) SA56 : 64 KB (32 KW) SA55 : 64 KB (32 KW) SA54 : 64 KB (32 KW) SA53 : 64 KB (32 KW) SA52 : 64 KB (32 KW) SA51 : 64 KB (32 KW) SA50 : 64 KB (32 KW) SA49 : 64 KB (32 KW) SA48 : 64 KB (32 KW) SA47 : 64 KB (32 KW) SA46 : 64 KB (32 KW) SA45 : 64 KB (32 KW) SA44 : 64 KB (32 KW) SA43 : 64 KB (32 KW) SA42 : 64 KB (32 KW) SA41 : 64 KB (32 KW) SA40 : 64 KB (32 KW) SA39 : 64 KB (32 KW) SA38 : 64 KB (32 KW) SA37 : 64 KB (32 KW) SA36 : 64 KB (32 KW) SA35 : 64 KB (32 KW) SA34 : 64 KB (32 KW) SA33 : 64 KB (32 KW) SA32 : 64 KB (32 KW) SA31 : 64 KB (32 KW) SA30 : 64 KB (32 KW) SA29 : 64 KB (32 KW) SA28 : 64 KB (32 KW) SA27 : 64 KB (32 KW) SA26 : 64 KB (32 KW) SA25 : 64 KB (32 KW) SA24 : 64 KB (32 KW) SA23 : 64 KB (32 KW) SA22 : 64 KB (32 KW) SA21 : 64 KB (32 KW) SA20 : 64 KB (32 KW) SA19 : 64 KB (32 KW) SA18 : 64 KB (32 KW) SA17 : 64 KB (32 KW) SA16 : 64 KB (32 KW) SA15 : 64 KB (32 KW) SA14 : 64 KB (32 KW) SA13 : 64 KB (32 KW) SA12 : 64 KB (32 KW) SA11 : 64 KB (32 KW) SA10 : 64 KB (32 KW) SA9 : 64 KB (32 KW) SA8 : 64 KB (32 KW) SA7 : 64 KB (32 KW) SA6 : 64 KB (32 KW) SA5 : 64 KB (32 KW) SA4 : 64 KB (32 KW) SA3 : 64 KB (32 KW) SA2 : 64 KB (32 KW) SA1 : 64 KB (32 KW) SA0 : 64 KB (32 KW) Word Mode Byte Mode 1FFFFFh 3FFFFFh 1FF000h 3FE000h 1FE000h 3FC000h 1FD000h 3FA000h 1FC000h 3F8000h 1FB000h 3F6000h 1FA000h 3F4000h 1F9000h 3F2000h 1F8000h 3F0000h 1F0000h 3E0000h 1E8000h 3D0000h 1E0000h 3C0000h 1D8000h 3B0000h 1D0000h 3A0000h 1C8000h 390000h 1C0000h 380000h 1B8000h 370000h 1B0000h 360000h 1A8000h 350000h 1A0000h 340000h 198000h 330000h 190000h 320000h 188000h 310000h 180000h 300000h 178000h 2F0000h 170000h 2E0000h 168000h 2D0000h 160000h 2C0000h 158000h 2B0000h 150000h 2A0000h 148000h 290000h 140000h 280000h 138000h 270000h 130000h 260000h 128000h 250000h 120000h 240000h 118000h 230000h 110000h 220000h 108000h 210000h 100000h 200000h 0F8000h 1F0000h 0F0000h 1E0000h 0E8000h 1D0000h 0E0000h 1C0000h 0D8000h 1B0000h 0D0000h 1A0000h 0C8000h 190000h 0C0000h 180000h 0B8000h 170000h 0B0000h 160000h 0A8000h 150000h 0A0000h 140000h 098000h 130000h 090000h 120000h 088000h 110000h 080000h 100000h 078000h 0F0000h 070000h 0E0000h 068000h 0D0000h 060000h 0C0000h 058000h 0B0000h 050000h 0A0000h 048000h 090000h 040000h 080000h 038000h 070000h 030000h 060000h 028000h 050000h 020000h 040000h 018000h 030000h 010000h 020000h 008000h 010000h 000000h 000000h MB84VD2218XEA/H Sector Architecture (Top Boot Block) (Continued) 9 MB84VD2218XEA/H/2219XEA/H-70/85/90 (Continued) Bank 2 MB84VD22194EA/H Bank 2 MB84VD22193EA/H Bank 2 MB84VD22192EA/H Bank 1 MB84VD22194EA/H Bank 1 MB84VD22193EA/H Bank 1 MB84VD22192EA/H SA70 : 64 KB (32 KW) SA69 : 64 KB (32 KW) SA68 : 64 KB (32 KW) SA67 : 64 KB (32 KW) SA66 : 64 KB (32 KW) SA65 : 64 KB (32 KW) SA64 : 64 KB (32 KW) SA63 : 64 KB (32 KW) SA62 : 64 KB (32 KW) SA61 : 64 KB (32 KW) SA60 : 64 KB (32 KW) SA59 : 64 KB (32 KW) SA58 : 64 KB (32 KW) SA57 : 64 KB (32 KW) SA56 : 64 KB (32 KW) SA55 : 64 KB (32 KW) SA54 : 64 KB (32 KW) SA53 : 64 KB (32 KW) SA52 : 64 KB (32 KW) SA51 : 64 KB (32 KW) SA50 : 64 KB (32 KW) SA49 : 64 KB (32 KW) SA48 : 64 KB (32 KW) SA47 : 64 KB (32 KW) SA46 : 64 KB (32 KW) SA45 : 64 KB (32 KW) SA44 : 64 KB (32 KW) SA43 : 64 KB (32 KW) SA42 : 64 KB (32 KW) SA41 : 64 KB (32 KW) SA40 : 64 KB (32 KW) SA39 : 64 KB (32 KW) SA38 : 64 KB (32 KW) SA37 : 64 KB (32 KW) SA36 : 64 KB (32 KW) SA35 : 64 KB (32 KW) SA34 : 64 KB (32 KW) SA33 : 64 KB (32 KW) SA32 : 64 KB (32 KW) SA31 : 64 KB (32 KW) SA30 : 64 KB (32 KW) SA29 : 64 KB (32 KW) SA28 : 64 KB (32 KW) SA27 : 64 KB (32 KW) SA26 : 64 KB (32 KW) SA25 : 64 KB (32 KW) SA24 : 64 KB (32 KW) SA23 : 64 KB (32 KW) SA22 : 64 KB (32 KW) SA21 : 64 KB (32 KW) SA20 : 64 KB (32 KW) SA19 : 64 KB (32 KW) SA18 : 64 KB (32 KW) SA17 : 64 KB (32 KW) SA16 : 64 KB (32 KW) SA15 : 64 KB (32 KW) SA14 : 64 KB (32 KW) SA13 : 64 KB (32 KW) SA12 : 64 KB (32 KW) SA11 : 64 KB (32 KW) SA10 : 64 KB (32 KW) SA9 : 64 KB (32 KW) SA8 : 64 KB (32 KW) SA7 : 8 KB (4 KW) SA6 : 8 KB (4 KW) SA5 : 8 KB (4 KW) SA4 : 8 KB (4 KW) SA3 : 8 KB (4 KW) SA2 : 8 KB (4 KW) SA1 : 8 KB (4 KW) SA0 : 8 KB (4 KW) Word Mode Byte Mode 1FFFFFh 3FFFFFh 1F8000h 3F0000h 1F0000h 3E0000h 1E8000h 3D0000h 1E0000h 3C0000h 1D8000h 3B0000h 1D0000h 3A0000h 1C8000h 390000h 1C0000h 380000h 1B8000h 370000h 1B0000h 360000h 1A8000h 350000h 1A0000h 340000h 198000h 330000h 190000h 320000h 188000h 310000h 180000h 300000h 178000h 2F0000h 170000h 2E0000h 168000h 2D0000h 160000h 2C0000h 158000h 2B0000h 150000h 2A0000h 148000h 290000h 140000h 280000h 138000h 270000h 130000h 260000h 128000h 250000h 120000h 240000h 118000h 230000h 110000h 220000h 108000h 210000h 100000h 200000h 0F8000h 1F0000h 0F0000h 1E0000h 0E8000h 1D0000h 0E0000h 1C0000h 0D8000h 1B0000h 0D0000h 1A0000h 0C8000h 190000h 0C0000h 180000h 0B8000h 170000h 0B0000h 160000h 0A8000h 150000h 0A0000h 140000h 098000h 130000h 090000h 120000h 088000h 110000h 080000h 100000h 078000h 0F0000h 070000h 0E0000h 068000h 0D0000h 060000h 0C0000h 058000h 0B0000h 050000h 0A0000h 048000h 090000h 040000h 080000h 038000h 070000h 030000h 060000h 028000h 050000h 020000h 040000h 018000h 030000h 010000h 020000h 008000h 010000h 007000h 00E000h 006000h 00C000h 005000h 00A000h 004000h 008000h 003000h 006000h 002000h 004000h 001000h 002000h 000000h 000000h MB84VD2219XEA/H Sector Architecture (Bottom Boot Block) 10 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Table (MB84VD22182EA/H) Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 SA0 0 0 0 0 0 0 X X X X 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 0 1 X X X X 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 0 1 0 X X X X 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 0 1 1 X X X X 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 0 1 0 0 X X X X 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 0 1 0 1 X X X X 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 0 1 1 0 X X X X 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 0 1 1 1 X X X X 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 0 1 0 0 0 X X X X 080000h to 08FFFFh 040000h to 047FFFh SA9 0 0 1 0 0 1 X X X X 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 0 1 0 1 0 X X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 0 1 0 1 1 X X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 0 1 1 0 0 X X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 0 1 1 0 1 X X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 0 1 1 1 0 X X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 0 1 1 1 1 X X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 0 1 0 0 0 0 X X X X 100000h to 10FFFFh 080000h to 087FFFh SA17 0 1 0 0 0 1 X X X X 110000h to 11FFFFh 088000h to 08FFFFh SA18 0 1 0 0 1 0 X X X X 120000h to 12FFFFh 090000h to 097FFFh SA19 0 1 0 0 1 1 X X X X 130000h to 13FFFFh 098000h to 09FFFFh SA20 0 1 0 1 0 0 X X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 0 1 0 1 0 1 X X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 0 1 0 1 1 0 X X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 0 1 0 1 1 1 X X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 0 1 1 0 0 0 X X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 0 1 1 0 0 1 X X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 0 1 1 0 1 0 X X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 0 1 1 0 1 1 X X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 0 1 1 1 0 0 X X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 0 1 1 1 0 1 X X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 0 1 1 1 1 0 X X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA31 0 1 1 1 1 1 X X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh (Continued) BA : Bank Address 11 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 Bank 1 SA32 1 0 0 0 0 0 X X X X 200000h to 20FFFFh 100000h to 107FFFh SA33 1 0 0 0 0 1 X X X X 210000h to 21FFFFh 108000h to 10FFFFh SA34 1 0 0 0 1 0 X X X X 220000h to 22FFFFh 110000h to 117FFFh SA35 1 0 0 0 1 1 X X X X 230000h to 23FFFFh 118000h to 11FFFFh SA36 1 0 0 1 0 0 X X X X 240000h to 24FFFFh 120000h to 127FFFh SA37 1 0 0 1 0 1 X X X X 250000h to 25FFFFh 128000h to 12FFFFh SA38 1 0 0 1 1 0 X X X X 260000h to 26FFFFh 130000h to 137FFFh SA39 1 0 0 1 1 1 X X X X 270000h to 27FFFFh 138000h to 13FFFFh SA40 1 0 1 0 0 0 X X X X 280000h to 28FFFFh 140000h to 147FFFh SA41 1 0 1 0 0 1 X X X X 290000h to 29FFFFh 148000h to 14FFFFh SA42 1 0 1 0 1 0 X X X X 2A0000h to 2AFFFFh 150000h to 157FFFh SA43 1 0 1 0 1 1 X X X X 2B0000h to 2BFFFFh 158000h to 15FFFFh SA44 1 0 1 1 0 0 X X X X 2C0000h to 2CFFFFh 160000h to 167FFFh SA45 1 0 1 1 0 1 X X X X 2D0000h to 2DFFFFh 168000h to 16FFFFh SA46 1 0 1 1 1 0 X X X X 2E0000h to 2EFFFFh 170000h to 177FFFh SA47 1 0 1 1 1 1 X X X X 2F0000h to 2FFFFFh 178000h to 17FFFFh SA48 1 1 0 0 0 0 X X X X 300000h to 30FFFFh 180000h to 187FFFh SA49 1 1 0 0 0 1 X X X X 310000h to 31FFFFh 188000h to 18FFFFh SA50 1 1 0 0 1 0 X X X X 320000h to 32FFFFh 190000h to 197FFFh SA51 1 1 0 0 1 1 X X X X 330000h to 33FFFFh 198000h to 19FFFFh SA52 1 1 0 1 0 0 X X X X 340000h to 34FFFFh 1A0000h to 1A7FFFh SA53 1 1 0 1 0 1 X X X X 350000h to 35FFFFh 1A8000h to 1AFFFFh SA54 1 1 0 1 1 0 X X X X 360000h to 36FFFFh 1B0000h to 1B7FFFh SA55 1 1 0 1 1 1 X X X X 370000h to 37FFFFh 1B8000h to 1BFFFFh SA56 1 1 1 0 0 0 X X X X 380000h to 38FFFFh 1C0000h to 1C7FFFh SA57 1 1 1 0 0 1 X X X X 390000h to 39FFFFh 1C8000h to 1CFFFFh SA58 1 1 1 0 1 0 X X X X 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh SA59 1 1 1 0 1 1 X X X X 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA60 1 1 1 1 0 0 X X X X 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA61 1 1 1 1 0 1 X X X X 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA62 1 1 1 1 1 0 X X X X 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA63 1 1 1 1 1 1 0 0 0 X 3F0000h to 3F1FFFh 1F8000h to 1F8FFFh SA64 1 1 1 1 1 1 0 0 1 X 3F2000h to 3F3FFFh 1F9000h to 1F9FFFh SA65 1 1 1 1 1 1 0 1 0 X 3F4000h to 3F5FFFh 1FA000h to 1FAFFFh (Continued) 12 MB84VD2218XEA/H/2219XEA/H-70/85/90 (Continued) Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 1 SA66 1 1 1 1 1 1 0 1 1 X 3F6000h to 3F7FFFh 1FB000h to 1FBFFFh SA67 1 1 1 1 1 1 1 0 0 X 3F8000h to 3F9FFFh 1FC000h to 1FCFFFh SA68 1 1 1 1 1 1 1 0 1 X 3FA000h to 3FAFFFh 1FD000h to 1FDFFFh SA69 1 1 1 1 1 1 1 1 0 X 3FC000h to 3FCFFFh 1FE000h to 1FEFFFh SA70 1 1 1 1 1 1 1 1 1 X 3FE000h to 3FFFFFh 1FF000h to 1FFFFFh 13 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Table (MB84VD22192EA/H) Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 1 Bank 2 SA0 0 0 0 0 0 0 0 0 0 X 000000h to 001FFFh 000000h to 000FFFh SA1 0 0 0 0 0 0 0 0 1 X 002000h to 003FFFh 001000h to 001FFFh SA2 0 0 0 0 0 0 0 1 0 X 004000h to 005FFFh 002000h to 002FFFh SA3 0 0 0 0 0 0 0 1 1 X 006000h to 007FFFh 003000h to 003FFFh SA4 0 0 0 0 0 0 1 0 0 X 008000h to 009FFFh 004000h to 004FFFh SA5 0 0 0 0 0 0 1 0 1 X 00A000h to 00BFFFh 005000h to 005FFFh SA6 0 0 0 0 0 0 1 1 0 X 00C000h to 00DFFFh 006000h to 006FFFh SA7 0 0 0 0 0 0 1 1 1 X 00E000h to 00FFFFh 007000h to 007FFFh SA8 0 0 0 0 0 1 X X X X 010000h to 01FFFFh 008000h to 00FFFFh SA9 0 0 0 0 1 0 X X X X 020000h to 02FFFFh 010000h to 017FFFh SA10 0 0 0 0 1 1 X X X X 030000h to 03FFFFh 018000h to 01FFFFh SA11 0 0 0 1 0 0 X X X X 040000h to 04FFFFh 020000h to 027FFFh SA12 0 0 0 1 0 1 X X X X 050000h to 05FFFFh 028000h to 02FFFFh SA13 0 0 0 1 1 0 X X X X 060000h to 06FFFFh 030000h to 037FFFh SA14 0 0 0 1 1 1 X X X X 070000h to 07FFFFh 038000h to 03FFFFh SA15 0 0 1 0 0 0 X X X X 080000h to 08FFFFh 040000h to 047FFFh SA16 0 0 1 0 0 1 X X X X 090000h to 09FFFFh 048000h to 04FFFFh SA17 0 0 1 0 1 0 X X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA18 0 0 1 0 1 1 X X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA19 0 0 1 1 0 0 X X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA20 0 0 1 1 0 1 X X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA21 0 0 1 1 1 0 X X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA22 0 0 1 1 1 1 X X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA23 0 1 0 0 0 0 X X X X 100000h to 10FFFFh 080000h to 087FFFh SA24 0 1 0 0 0 1 X X X X 110000h to 11FFFFh 088000h to 08FFFFh SA25 0 1 0 0 1 0 X X X X 120000h to 12FFFFh 090000h to 097FFFh SA26 0 1 0 0 1 1 X X X X 130000h to 13FFFFh 098000h to 09FFFFh SA27 0 1 0 1 0 0 X X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA28 0 1 0 1 0 1 X X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA29 0 1 0 1 1 0 X X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA30 0 1 0 1 1 1 X X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA31 0 1 1 0 0 0 X X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh (Continued) 14 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) 0C8000h to 0CFFFFh A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 SA32 0 1 1 0 0 1 X X X X 190000h to 19FFFFh SA33 0 1 1 0 1 0 X X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA34 0 1 1 0 1 1 X X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA35 0 1 1 1 0 0 X X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA36 0 1 1 1 0 1 X X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA37 0 1 1 1 1 0 X X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA38 0 1 1 1 1 1 X X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh SA39 1 0 0 0 0 0 X X X X 200000h to 20FFFFh 100000h to 107FFFh SA40 1 0 0 0 0 1 X X X X 210000h to 21FFFFh 108000h to 10FFFFh SA41 1 0 0 0 1 0 X X X X 220000h to 22FFFFh 110000h to 117FFFh SA42 1 0 0 0 1 1 X X X X 230000h to 23FFFFh 118000h to 11FFFFh SA43 1 0 0 1 0 0 X X X X 240000h to 24FFFFh 120000h to 127FFFh SA44 1 0 0 1 0 1 X X X X 250000h to 25FFFFh 128000h to 12FFFFh SA45 1 0 0 1 1 0 X X X X 260000h to 26FFFFh 130000h to 137FFFh SA46 1 0 0 1 1 1 X X X X 270000h to 27FFFFh 138000h to 13FFFFh SA47 1 0 1 0 0 0 X X X X 280000h to 28FFFFh 140000h to 147FFFh SA48 1 0 1 0 0 1 X X X X 290000h to 29FFFFh 148000h to 14FFFFh SA49 1 0 1 0 1 0 X X X X 2A0000h to 2AFFFFh 150000h to 157FFFh SA50 1 0 1 0 1 1 X X X X 2B0000h to 2BFFFFh 158000h to 15FFFFh SA51 1 0 1 1 0 0 X X X X 2C0000h to 2CFFFFh 160000h to 167FFFh SA52 1 0 1 1 0 1 X X X X 2D0000h to 2DFFFFh 168000h to 16FFFFh SA53 1 0 1 1 1 0 X X X X 2E0000h to 2EFFFFh 170000h to 177FFFh SA54 1 0 1 1 1 1 X X X X 2F0000h to 2FFFFFh 178000h to 17FFFFh SA55 1 1 0 0 0 0 X X X X 300000h to 30FFFFh 180000h to 187FFFh SA56 1 1 0 0 0 1 X X X X 310000h to 31FFFFh 188000h to 18FFFFh SA57 1 1 0 0 1 0 X X X X 320000h to 32FFFFh 190000h to 197FFFh SA58 1 1 0 0 1 1 X X X X 330000h to 33FFFFh 198000h to 19FFFFh SA59 1 1 0 1 0 0 X X X X 340000h to 34FFFFh 1A0000h to 1A7FFFh SA60 1 1 0 1 0 1 X X X X 350000h to 35FFFFh 1A8000h to 1AFFFFh SA61 1 1 0 1 1 0 X X X X 360000h to 36FFFFh 1B0000h to 1B7FFFh SA62 1 1 0 1 1 1 X X X X 370000h to 37FFFFh 1B8000h to 1BFFFFh SA63 1 1 1 0 0 0 X X X X 380000h to 38FFFFh 1C0000h to 1C7FFFh SA64 1 1 1 0 0 1 X X X X 390000h to 39FFFFh 1C8000h to 1CFFFFh SA65 1 1 1 0 1 0 X X X X 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh (Continued) 15 MB84VD2218XEA/H/2219XEA/H-70/85/90 (Continued) Sector Address Bank Sector Address Range (BYTE mode) Bank Address Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 SA66 1 1 1 0 1 1 X X X X 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA67 1 1 1 1 0 0 X X X X 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA68 1 1 1 1 0 1 X X X X 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA69 1 1 1 1 1 0 X X X X 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA70 1 1 1 1 1 1 X X X X 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh BA : Bank Address 16 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Table (MB84VD22183EA/H) Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 SA0 0 0 0 0 0 0 X X X X 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 0 1 X X X X 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 0 1 0 X X X X 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 0 1 1 X X X X 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 0 1 0 0 X X X X 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 0 1 0 1 X X X X 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 0 1 1 0 X X X X 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 0 1 1 1 X X X X 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 0 1 0 0 0 X X X X 080000h to 08FFFFh 040000h to 047FFFh SA9 0 0 1 0 0 1 X X X X 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 0 1 0 1 0 X X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 0 1 0 1 1 X X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 0 1 1 0 0 X X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 0 1 1 0 1 X X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 0 1 1 1 0 X X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 0 1 1 1 1 X X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 0 1 0 0 0 0 X X X X 100000h to 10FFFFh 080000h to 087FFFh SA17 0 1 0 0 0 1 X X X X 110000h to 11FFFFh 088000h to 08FFFFh SA18 0 1 0 0 1 0 X X X X 120000h to 12FFFFh 090000h to 097FFFh SA19 0 1 0 0 1 1 X X X X 130000h to 13FFFFh 098000h to 09FFFFh SA20 0 1 0 1 0 0 X X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 0 1 0 1 0 1 X X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 0 1 0 1 1 0 X X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 0 1 0 1 1 1 X X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 0 1 1 0 0 0 X X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 0 1 1 0 0 1 X X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 0 1 1 0 1 0 X X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 0 1 1 0 1 1 X X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 0 1 1 1 0 0 X X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 0 1 1 1 0 1 X X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 0 1 1 1 1 0 X X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA31 0 1 1 1 1 1 X X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh (Continued) BA : Bank Address 17 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 Bank 1 SA32 1 0 0 0 0 0 X X X X 200000h to 20FFFFh 100000h to 107FFFh SA33 1 0 0 0 0 1 X X X X 210000h to 21FFFFh 108000h to 10FFFFh SA34 1 0 0 0 1 0 X X X X 220000h to 22FFFFh 110000h to 117FFFh SA35 1 0 0 0 1 1 X X X X 230000h to 23FFFFh 118000h to 11FFFFh SA36 1 0 0 1 0 0 X X X X 240000h to 24FFFFh 120000h to 127FFFh SA37 1 0 0 1 0 1 X X X X 250000h to 25FFFFh 128000h to 12FFFFh SA38 1 0 0 1 1 0 X X X X 260000h to 26FFFFh 130000h to 137FFFh SA39 1 0 0 1 1 1 X X X X 270000h to 27FFFFh 138000h to 13FFFFh SA40 1 0 1 0 0 0 X X X X 280000h to 28FFFFh 140000h to 147FFFh SA41 1 0 1 0 0 1 X X X X 290000h to 29FFFFh 148000h to 14FFFFh SA42 1 0 1 0 1 0 X X X X 2A0000h to 2AFFFFh 150000h to 157FFFh SA43 1 0 1 0 1 1 X X X X 2B0000h to 2BFFFFh 158000h to 15FFFFh SA44 1 0 1 1 0 0 X X X X 2C0000h to 2CFFFFh 160000h to 167FFFh SA45 1 0 1 1 0 1 X X X X 2D0000h to 2DFFFFh 168000h to 16FFFFh SA46 1 0 1 1 1 0 X X X X 2E0000h to 2EFFFFh 170000h to 177FFFh SA47 1 0 1 1 1 1 X X X X 2F0000h to 2FFFFFh 178000h to 17FFFFh SA48 1 1 0 0 0 0 X X X X 300000h to 30FFFFh 180000h to 187FFFh SA49 1 1 0 0 0 1 X X X X 310000h to 31FFFFh 188000h to 18FFFFh SA50 1 1 0 0 1 0 X X X X 320000h to 32FFFFh 190000h to 197FFFh SA51 1 1 0 0 1 1 X X X X 330000h to 33FFFFh 198000h to 19FFFFh SA52 1 1 0 1 0 0 X X X X 340000h to 34FFFFh 1A0000h to 1A7FFFh SA53 1 1 0 1 0 1 X X X X 350000h to 35FFFFh 1A8000h to 1AFFFFh SA54 1 1 0 1 1 0 X X X X 360000h to 36FFFFh 1B0000h to 1B7FFFh SA55 1 1 0 1 1 1 X X X X 370000h to 37FFFFh 1B8000h to 1BFFFFh SA56 1 1 1 0 0 0 X X X X 380000h to 38FFFFh 1C0000h to 1C7FFFh SA57 1 1 1 0 0 1 X X X X 390000h to 39FFFFh 1C8000h to 1CFFFFh SA58 1 1 1 0 1 0 X X X X 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh SA59 1 1 1 0 1 1 X X X X 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA60 1 1 1 1 0 0 X X X X 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA61 1 1 1 1 0 1 X X X X 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA62 1 1 1 1 1 0 X X X X 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA63 1 1 1 1 1 1 0 0 0 X 3F0000h to 3F1FFFh 1F8000h to 1F8FFFh SA64 1 1 1 1 1 1 0 0 1 X 3F2000h to 3F3FFFh 1F9000h to 1F9FFFh SA65 1 1 1 1 1 1 0 1 0 X 3F4000h to 3F5FFFh 1FA000h to 1FAFFFh (Continued) 18 MB84VD2218XEA/H/2219XEA/H-70/85/90 (Continued) Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 1 SA66 1 1 1 1 1 1 0 1 1 X 3F6000h to 3F7FFFh 1FB000h to 1FBFFFh SA67 1 1 1 1 1 1 1 0 0 X 3F8000h to 3F9FFFh 1FC000h to 1FCFFFh SA68 1 1 1 1 1 1 1 0 1 X 3FA000h to 3FAFFFh 1FD000h to 1FDFFFh SA69 1 1 1 1 1 1 1 1 0 X 3FC000h to 3FCFFFh 1FE000h to 1FEFFFh SA70 1 1 1 1 1 1 1 1 1 X 3FE000h to 3FFFFFh 1FF000h to 1FFFFFh 19 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Table (MB84VD22193EA/H) Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 1 Bank 2 SA0 0 0 0 0 0 0 0 0 0 X 000000h to 001FFFh 000000h to 000FFFh SA1 0 0 0 0 0 0 0 0 1 X 002000h to 003FFFh 001000h to 001FFFh SA2 0 0 0 0 0 0 0 1 0 X 004000h to 005FFFh 002000h to 002FFFh SA3 0 0 0 0 0 0 0 1 1 X 006000h to 007FFFh 003000h to 003FFFh SA4 0 0 0 0 0 0 1 0 0 X 008000h to 009FFFh 004000h to 004FFFh SA5 0 0 0 0 0 0 1 0 1 X 00A000h to 00BFFFh 005000h to 005FFFh SA6 0 0 0 0 0 0 1 1 0 X 00C000h to 00DFFFh 006000h to 006FFFh SA7 0 0 0 0 0 0 1 1 1 X 00E000h to 00FFFFh 007000h to 007FFFh SA8 0 0 0 0 0 1 X X X X 010000h to 01FFFFh 008000h to 00FFFFh SA9 0 0 0 0 1 0 X X X X 020000h to 02FFFFh 010000h to 017FFFh SA10 0 0 0 0 1 1 X X X X 030000h to 03FFFFh 018000h to 01FFFFh SA11 0 0 0 1 0 0 X X X X 040000h to 04FFFFh 020000h to 027FFFh SA12 0 0 0 1 0 1 X X X X 050000h to 05FFFFh 028000h to 02FFFFh SA13 0 0 0 1 1 0 X X X X 060000h to 06FFFFh 030000h to 037FFFh SA14 0 0 0 1 1 1 X X X X 070000h to 07FFFFh 038000h to 03FFFFh SA15 0 0 1 0 0 0 X X X X 080000h to 08FFFFh 040000h to 047FFFh SA16 0 0 1 0 0 1 X X X X 090000h to 09FFFFh 048000h to 04FFFFh SA17 0 0 1 0 1 0 X X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA18 0 0 1 0 1 1 X X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA19 0 0 1 1 0 0 X X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA20 0 0 1 1 0 1 X X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA21 0 0 1 1 1 0 X X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA22 0 0 1 1 1 1 X X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA23 0 1 0 0 0 0 X X X X 100000h to 10FFFFh 080000h to 087FFFh SA24 0 1 0 0 0 1 X X X X 110000h to 11FFFFh 088000h to 08FFFFh SA25 0 1 0 0 1 0 X X X X 120000h to 12FFFFh 090000h to 097FFFh SA26 0 1 0 0 1 1 X X X X 130000h to 13FFFFh 098000h to 09FFFFh SA27 0 1 0 1 0 0 X X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA28 0 1 0 1 0 1 X X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA29 0 1 0 1 1 0 X X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA30 0 1 0 1 1 1 X X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA31 0 1 1 0 0 0 X X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh (Continued) 20 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) 0C8000h to 0CFFFFh A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 SA32 0 1 1 0 0 1 X X X X 190000h to 19FFFFh SA33 0 1 1 0 1 0 X X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA34 0 1 1 0 1 1 X X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA35 0 1 1 1 0 0 X X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA36 0 1 1 1 0 1 X X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA37 0 1 1 1 1 0 X X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA38 0 1 1 1 1 1 X X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh SA39 1 0 0 0 0 0 X X X X 200000h to 20FFFFh 100000h to 107FFFh SA40 1 0 0 0 0 1 X X X X 210000h to 21FFFFh 108000h to 10FFFFh SA41 1 0 0 0 1 0 X X X X 220000h to 22FFFFh 110000h to 117FFFh SA42 1 0 0 0 1 1 X X X X 230000h to 23FFFFh 118000h to 11FFFFh SA43 1 0 0 1 0 0 X X X X 240000h to 24FFFFh 120000h to 127FFFh SA44 1 0 0 1 0 1 X X X X 250000h to 25FFFFh 128000h to 12FFFFh SA45 1 0 0 1 1 0 X X X X 260000h to 26FFFFh 130000h to 137FFFh SA46 1 0 0 1 1 1 X X X X 270000h to 27FFFFh 138000h to 13FFFFh SA47 1 0 1 0 0 0 X X X X 280000h to 28FFFFh 140000h to 147FFFh SA48 1 0 1 0 0 1 X X X X 290000h to 29FFFFh 148000h to 14FFFFh SA49 1 0 1 0 1 0 X X X X 2A0000h to 2AFFFFh 150000h to 157FFFh SA50 1 0 1 0 1 1 X X X X 2B0000h to 2BFFFFh 158000h to 15FFFFh SA51 1 0 1 1 0 0 X X X X 2C0000h to 2CFFFFh 160000h to 167FFFh SA52 1 0 1 1 0 1 X X X X 2D0000h to 2DFFFFh 168000h to 16FFFFh SA53 1 0 1 1 1 0 X X X X 2E0000h to 2EFFFFh 170000h to 177FFFh SA54 1 0 1 1 1 1 X X X X 2F0000h to 2FFFFFh 178000h to 17FFFFh SA55 1 1 0 0 0 0 X X X X 300000h to 30FFFFh 180000h to 187FFFh SA56 1 1 0 0 0 1 X X X X 310000h to 31FFFFh 188000h to 18FFFFh SA57 1 1 0 0 1 0 X X X X 320000h to 32FFFFh 190000h to 197FFFh SA58 1 1 0 0 1 1 X X X X 330000h to 33FFFFh 198000h to 19FFFFh SA59 1 1 0 1 0 0 X X X X 340000h to 34FFFFh 1A0000h to 1A7FFFh SA60 1 1 0 1 0 1 X X X X 350000h to 35FFFFh 1A8000h to 1AFFFFh SA61 1 1 0 1 1 0 X X X X 360000h to 36FFFFh 1B0000h to 1B7FFFh SA62 1 1 0 1 1 1 X X X X 370000h to 37FFFFh 1B8000h to 1BFFFFh SA63 1 1 1 0 0 0 X X X X 380000h to 38FFFFh 1C0000h to 1C7FFFh SA64 1 1 1 0 0 1 X X X X 390000h to 39FFFFh 1C8000h to 1CFFFFh SA65 1 1 1 0 1 0 X X X X 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh (Continued) 21 MB84VD2218XEA/H/2219XEA/H-70/85/90 (Continued) Sector Address Bank Sector Address Range (BYTE mode) Bank Address Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 SA66 1 1 1 0 1 1 X X X X 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA67 1 1 1 1 0 0 X X X X 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA68 1 1 1 1 0 1 X X X X 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA69 1 1 1 1 1 0 X X X X 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA70 1 1 1 1 1 1 X X X X 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh BA : Bank Address 22 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Table (MB84VD22184EA/E) Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 SA0 0 0 0 0 0 0 X X X X 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 0 1 X X X X 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 0 1 0 X X X X 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 0 1 1 X X X X 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 0 1 0 0 X X X X 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 0 1 0 1 X X X X 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 0 1 1 0 X X X X 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 0 1 1 1 X X X X 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 0 1 0 0 0 X X X X 080000h to 08FFFFh 040000h to 047FFFh SA9 0 0 1 0 0 1 X X X X 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 0 1 0 1 0 X X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA11 0 0 1 0 1 1 X X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 0 1 1 0 0 X X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA13 0 0 1 1 0 1 X X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 0 1 1 1 0 X X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA15 0 0 1 1 1 1 X X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 0 1 0 0 0 0 X X X X 100000h to 10FFFFh 080000h to 087FFFh SA17 0 1 0 0 0 1 X X X X 110000h to 11FFFFh 088000h to 08FFFFh SA18 0 1 0 0 1 0 X X X X 120000h to 12FFFFh 090000h to 097FFFh SA19 0 1 0 0 1 1 X X X X 130000h to 13FFFFh 098000h to 09FFFFh SA20 0 1 0 1 0 0 X X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 0 1 0 1 0 1 X X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA22 0 1 0 1 1 0 X X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA23 0 1 0 1 1 1 X X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA24 0 1 1 0 0 0 X X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 0 1 1 0 0 1 X X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 0 1 1 0 1 0 X X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 0 1 1 0 1 1 X X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 0 1 1 1 0 0 X X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 0 1 1 1 0 1 X X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 0 1 1 1 1 0 X X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA31 0 1 1 1 1 1 X X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh (Continued) BA : Bank Address 23 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 1 SA32 1 0 0 0 0 0 X X X X 200000h to 20FFFFh 100000h to 107FFFh SA33 1 0 0 0 0 1 X X X X 210000h to 21FFFFh 108000h to 10FFFFh SA34 1 0 0 0 1 0 X X X X 220000h to 22FFFFh 110000h to 117FFFh SA35 1 0 0 0 1 1 X X X X 230000h to 23FFFFh 118000h to 11FFFFh SA36 1 0 0 1 0 0 X X X X 240000h to 24FFFFh 120000h to 127FFFh SA37 1 0 0 1 0 1 X X X X 250000h to 25FFFFh 128000h to 12FFFFh SA38 1 0 0 1 1 0 X X X X 260000h to 26FFFFh 130000h to 137FFFh SA39 1 0 0 1 1 1 X X X X 270000h to 27FFFFh 138000h to 13FFFFh SA40 1 0 1 0 0 0 X X X X 280000h to 28FFFFh 140000h to 147FFFh SA41 1 0 1 0 0 1 X X X X 290000h to 29FFFFh 148000h to 14FFFFh SA42 1 0 1 0 1 0 X X X X 2A0000h to 2AFFFFh 150000h to 157FFFh SA43 1 0 1 0 1 1 X X X X 2B0000h to 2BFFFFh 158000h to 15FFFFh SA44 1 0 1 1 0 0 X X X X 2C0000h to 2CFFFFh 160000h to 167FFFh SA45 1 0 1 1 0 1 X X X X 2D0000h to 2DFFFFh 168000h to 16FFFFh SA46 1 0 1 1 1 0 X X X X 2E0000h to 2EFFFFh 170000h to 177FFFh SA47 1 0 1 1 1 1 X X X X 2F0000h to 2FFFFFh 178000h to 17FFFFh SA48 1 1 0 0 0 0 X X X X 300000h to 30FFFFh 180000h to 187FFFh SA49 1 1 0 0 0 1 X X X X 310000h to 31FFFFh 188000h to 18FFFFh SA50 1 1 0 0 1 0 X X X X 320000h to 32FFFFh 190000h to 197FFFh SA51 1 1 0 0 1 1 X X X X 330000h to 33FFFFh 198000h to 19FFFFh SA52 1 1 0 1 0 0 X X X X 340000h to 34FFFFh 1A0000h to 1A7FFFh SA53 1 1 0 1 0 1 X X X X 350000h to 35FFFFh 1A8000h to 1AFFFFh SA54 1 1 0 1 1 0 X X X X 360000h to 36FFFFh 1B0000h to 1B7FFFh SA55 1 1 0 1 1 1 X X X X 370000h to 37FFFFh 1B8000h to 1BFFFFh SA56 1 1 1 0 0 0 X X X X 380000h to 38FFFFh 1C0000h to 1C7FFFh SA57 1 1 1 0 0 1 X X X X 390000h to 39FFFFh 1C8000h to 1CFFFFh SA58 1 1 1 0 1 0 X X X X 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh SA59 1 1 1 0 1 1 X X X X 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA60 1 1 1 1 0 0 X X X X 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA61 1 1 1 1 0 1 X X X X 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA62 1 1 1 1 1 0 X X X X 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA63 1 1 1 1 1 1 0 0 0 X 3F0000h to 3F1FFFh 1F8000h to 1F8FFFh SA64 1 1 1 1 1 1 0 0 1 X 3F2000h to 3F3FFFh 1F9000h to 1F9FFFh SA65 1 1 1 1 1 1 0 1 0 X 3F4000h to 3F5FFFh 1FA000h to 1FAFFFh (Continued) 24 MB84VD2218XEA/H/2219XEA/H-70/85/90 (Continued) Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 1 SA66 1 1 1 1 1 1 0 1 1 X 3F6000h to 3F7FFFh 1FB000h to 1FBFFFh SA67 1 1 1 1 1 1 1 0 0 X 3F8000h to 3F9FFFh 1FC000h to 1FCFFFh SA68 1 1 1 1 1 1 1 0 1 X 3FA000h to 3FAFFFh 1FD000h to 1FDFFFh SA69 1 1 1 1 1 1 1 1 0 X 3FC000h to 3FCFFFh 1FE000h to 1FEFFFh SA70 1 1 1 1 1 1 1 1 1 X 3FE000h to 3FFFFFh 1FF000h to 1FFFFFh 25 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Table (MB84VD22194EA/H) Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 1 SA0 0 0 0 0 0 0 0 0 0 X 000000h to 001FFFh 000000h to 000FFFh SA1 0 0 0 0 0 0 0 0 1 X 002000h to 003FFFh 001000h to 001FFFh SA2 0 0 0 0 0 0 0 1 0 X 004000h to 005FFFh 002000h to 002FFFh SA3 0 0 0 0 0 0 0 1 1 X 006000h to 007FFFh 003000h to 003FFFh SA4 0 0 0 0 0 0 1 0 0 X 008000h to 009FFFh 004000h to 004FFFh SA5 0 0 0 0 0 0 1 0 1 X 00A000h to 00BFFFh 005000h to 005FFFh SA6 0 0 0 0 0 0 1 1 0 X 00C000h to 00DFFFh 006000h to 006FFFh SA7 0 0 0 0 0 0 1 1 1 X 00E000h to 00FFFFh 007000h to 007FFFh SA8 0 0 0 0 0 1 X X X X 010000h to 01FFFFh 008000h to 00FFFFh SA9 0 0 0 0 1 0 X X X X 020000h to 02FFFFh 010000h to 017FFFh SA10 0 0 0 0 1 1 X X X X 030000h to 03FFFFh 018000h to 01FFFFh SA11 0 0 0 1 0 0 X X X X 040000h to 04FFFFh 020000h to 027FFFh SA12 0 0 0 1 0 1 X X X X 050000h to 05FFFFh 028000h to 02FFFFh SA13 0 0 0 1 1 0 X X X X 060000h to 06FFFFh 030000h to 037FFFh SA14 0 0 0 1 1 1 X X X X 070000h to 07FFFFh 038000h to 03FFFFh SA15 0 0 1 0 0 0 X X X X 080000h to 08FFFFh 040000h to 047FFFh SA16 0 0 1 0 0 1 X X X X 090000h to 09FFFFh 048000h to 04FFFFh SA17 0 0 1 0 1 0 X X X X 0A0000h to 0AFFFFh 050000h to 057FFFh SA18 0 0 1 0 1 1 X X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh SA19 0 0 1 1 0 0 X X X X 0C0000h to 0CFFFFh 060000h to 067FFFh SA20 0 0 1 1 0 1 X X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh SA21 0 0 1 1 1 0 X X X X 0E0000h to 0EFFFFh 070000h to 077FFFh SA22 0 0 1 1 1 1 X X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh SA23 0 1 0 0 0 0 X X X X 100000h to 10FFFFh 080000h to 087FFFh SA24 0 1 0 0 0 1 X X X X 110000h to 11FFFFh 088000h to 08FFFFh SA25 0 1 0 0 1 0 X X X X 120000h to 12FFFFh 090000h to 097FFFh SA26 0 1 0 0 1 1 X X X X 130000h to 13FFFFh 098000h to 09FFFFh SA27 0 1 0 1 0 0 X X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh SA28 0 1 0 1 0 1 X X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh SA29 0 1 0 1 1 0 X X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh SA30 0 1 0 1 1 1 X X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh SA31 0 1 1 0 0 0 X X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh (Continued) 26 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Address Bank Sector Bank Address Address Range (BYTE mode) Address Range (WORD mode) 0C8000h to 0CFFFFh A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 1 Bank 2 SA32 0 1 1 0 0 1 X X X X 190000h to 19FFFFh SA33 0 1 1 0 1 0 X X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA34 0 1 1 0 1 1 X X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA35 0 1 1 1 0 0 X X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA36 0 1 1 1 0 1 X X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA37 0 1 1 1 1 0 X X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA38 0 1 1 1 1 1 X X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh SA39 1 0 0 0 0 0 X X X X 200000h to 20FFFFh 100000h to 107FFFh SA40 1 0 0 0 0 1 X X X X 210000h to 21FFFFh 108000h to 10FFFFh SA41 1 0 0 0 1 0 X X X X 220000h to 22FFFFh 110000h to 117FFFh SA42 1 0 0 0 1 1 X X X X 230000h to 23FFFFh 118000h to 11FFFFh SA43 1 0 0 1 0 0 X X X X 240000h to 24FFFFh 120000h to 127FFFh SA44 1 0 0 1 0 1 X X X X 250000h to 25FFFFh 128000h to 12FFFFh SA45 1 0 0 1 1 0 X X X X 260000h to 26FFFFh 130000h to 137FFFh SA46 1 0 0 1 1 1 X X X X 270000h to 27FFFFh 138000h to 13FFFFh SA47 1 0 1 0 0 0 X X X X 280000h to 28FFFFh 140000h to 147FFFh SA48 1 0 1 0 0 1 X X X X 290000h to 29FFFFh 148000h to 14FFFFh SA49 1 0 1 0 1 0 X X X X 2A0000h to 2AFFFFh 150000h to 157FFFh SA50 1 0 1 0 1 1 X X X X 2B0000h to 2BFFFFh 158000h to 15FFFFh SA51 1 0 1 1 0 0 X X X X 2C0000h to 2CFFFFh 160000h to 167FFFh SA52 1 0 1 1 0 1 X X X X 2D0000h to 2DFFFFh 168000h to 16FFFFh SA53 1 0 1 1 1 0 X X X X 2E0000h to 2EFFFFh 170000h to 177FFFh SA54 1 0 1 1 1 1 X X X X 2F0000h to 2FFFFFh 178000h to 17FFFFh SA55 1 1 0 0 0 0 X X X X 300000h to 30FFFFh 180000h to 187FFFh SA56 1 1 0 0 0 1 X X X X 310000h to 31FFFFh 188000h to 18FFFFh SA57 1 1 0 0 1 0 X X X X 320000h to 32FFFFh 190000h to 197FFFh SA58 1 1 0 0 1 1 X X X X 330000h to 33FFFFh 198000h to 19FFFFh SA59 1 1 0 1 0 0 X X X X 340000h to 34FFFFh 1A0000h to 1A7FFFh SA60 1 1 0 1 0 1 X X X X 350000h to 35FFFFh 1A8000h to 1AFFFFh SA61 1 1 0 1 1 0 X X X X 360000h to 36FFFFh 1B0000h to 1B7FFFh SA62 1 1 0 1 1 1 X X X X 370000h to 37FFFFh 1B8000h to 1BFFFFh SA63 1 1 1 0 0 0 X X X X 380000h to 38FFFFh 1C0000h to 1C7FFFh SA64 1 1 1 0 0 1 X X X X 390000h to 39FFFFh 1C8000h to 1CFFFFh SA65 1 1 1 0 1 0 X X X X 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh (Continued) 27 MB84VD2218XEA/H/2219XEA/H-70/85/90 (Continued) Sector Address Bank Sector Address Range (BYTE mode) Bank Address Address Range (WORD mode) A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Bank 2 SA66 1 1 1 0 1 1 X X X X 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA67 1 1 1 1 0 0 X X X X 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA68 1 1 1 1 0 1 X X X X 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA69 1 1 1 1 1 0 X X X X 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA70 1 1 1 1 1 1 X X X X 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh BA : Bank Address 28 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Group Addresses Table (MB84VD2218XEA/H) (Top Boot Block) Sector Group A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 0 X X X SA0 0 1 1 0 X X X SA1 to SA3 1 1 SGA1 0 0 0 0 SGA2 0 0 0 1 X X X X X SA4 to SA7 SGA3 0 0 1 0 X X X X X SA8 to SA11 SGA4 0 0 1 1 X X X X X SA12 to SA15 SGA5 0 1 0 0 X X X X X SA16 to SA19 SGA6 0 1 0 1 X X X X X SA20 to SA23 SGA7 0 1 1 0 X X X X X SA24 to SA27 SGA8 0 1 1 1 X X X X X SA28 to SA31 SGA9 1 0 0 0 X X X X X SA32 to SA35 SGA10 1 0 0 1 X X X X X SA36 to SA39 SGA11 1 0 1 0 X X X X X SA40 to SA43 SGA12 1 0 1 1 X X X X X SA44 to SA47 SGA13 1 1 0 0 X X X X X SA48 to SA51 SGA14 1 1 0 1 X X X X X SA52 to SA55 SGA15 1 1 1 0 X X X X X SA56 to SA59 0 0 0 1 X X X SA60 to SA62 1 0 SGA16 1 1 1 1 SGA17 1 1 1 1 1 1 0 0 0 SA63 SGA18 1 1 1 1 1 1 0 0 1 SA64 SGA19 1 1 1 1 1 1 0 1 0 SA65 SGA20 1 1 1 1 1 1 0 1 1 SA66 SGA21 1 1 1 1 1 1 1 0 0 SA67 SGA22 1 1 1 1 1 1 1 0 1 SA68 SGA23 1 1 1 1 1 1 1 1 0 SA69 SGA24 1 1 1 1 1 1 1 1 1 SA70 29 MB84VD2218XEA/H/2219XEA/H-70/85/90 Sector Group Addresses Table (MB84VD2219XEA/H) (Bottom Boot Block) Sector Group A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 0 0 0 0 SA0 SGA1 0 0 0 0 0 0 0 0 1 SA1 SGA2 0 0 0 0 0 0 0 1 0 SA2 SGA3 0 0 0 0 0 0 0 1 1 SA3 SGA4 0 0 0 0 0 0 1 0 0 SA4 SGA5 0 0 0 0 0 0 1 0 1 SA5 SGA6 0 0 0 0 0 0 1 1 0 SA6 SGA7 0 0 0 0 0 0 1 1 1 SA7 0 1 1 0 X X X SA8 to SA10 1 1 SGA8 0 0 0 SGA9 0 0 0 1 X X X X X SA11 to SA14 SGA10 0 0 1 0 X X X X X SA15 to SA18 SGA11 0 0 1 1 X X X X X SA19 to SA22 SGA12 0 1 0 0 X X X X X SA23 to SA26 SGA13 0 1 0 1 X X X X X SA27 to SA30 SGA14 0 1 1 0 X X X X X SA31 to SA34 SGA15 0 1 1 1 X X X X X SA35 to SA38 SGA16 1 0 0 0 X X X X X SA39 to SA42 SGA17 1 0 0 1 X X X X X SA43 to SA46 SGA18 1 0 1 0 X X X X X SA47 to SA50 SGA19 1 0 1 1 X X X X X SA51 to SA54 SGA20 1 1 0 0 X X X X X SA55 to SA58 SGA21 1 1 0 1 X X X X X SA59 to SA62 SGA22 1 1 1 0 X X X X X SA63 to SA66 0 0 0 1 X X X SA67 to SA69 1 0 1 1 X X X SA70 SGA23 SGA24 30 0 1 1 1 1 1 1 1 1 MB84VD2218XEA/H/2219XEA/H-70/85/90 Flash Memory Autoselect Codes Table Type Manufacturer's Code MB84VD22182EA MB84VD22182EH MB84VD22192EA MB84VD22192EH Device Code MB84VD22183EA MB84VD22183EH MB84VD22193EA MB84VD22193EH MB84VD22184EA MB84VD22184EH MB84VD22194EA MB84VD22194EH Sector Group protect Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word A12 to A19 A6 A1 A0 A-1*1 Code (HEX) X VIL VIL VIL VIL 04h X VIL VIL VIH VIL 55h X 2255h X VIL VIL VIH VIL 56h X 2256h X VIL VIL VIH VIL 50h X 2250h X VIL VIL VIH VIL 53h X 2253h X VIL VIL VIH VIL 5Ch X 225Ch X VIL VIL VIH VIL 5Fh X 225Fh Sector Group Address VIL VIH VIL VIL 01h*2 *1 : A-1 is for Byte mode. *2 : Output 01h at protected sector address and output 00h at unprotected sector address. 31 MB84VD2218XEA/H/2219XEA/H-70/85/90 Flash Memory Command Definitions Table Bus Second Fourth Bus First Bus Third Bus Fifth Bus Sixth Bus Write Bus Read/Write Write Cycle Write Cycle Write Cycle Write Cycle CyWrite Cycle Cycle cles Req'd Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Command Sequence Read/Reset *1 Read/Reset *1 1 Word Byte 3 Word Autoselect Chip Erase Sector Erase 555h AAAh 3 Word Byte Word Byte Word Byte AAh 555h Byte Program XXXh F0h 6 6 2AAh 555h AAh 555h AAAh 555h AAAh 555h AAAh 55h 2AAh AAAh 4 55h 555h AAh AAh AAh 2AAh 555h 2AAh 555h 2AAh 555h 55h 55h 55h 555h AAAh (BA) 555h (BA) AAAh 555h AAAh 555h AAAh 555h AAAh F0h RA RD 90h A0h PA PD 80h 80h 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 555h AAAh 10h 55h SA 30h Sector Erase Suspend 1 BA B0h Sector Erase Resume 1 BA 30h 20h Set to Fast Mode Word Fast Program *2 Word Reset from Fast Mode *2 Word Extended Sector Group Protection *3 Word Byte Byte Byte Byte 3 2 2 4 Word Query *4 1 Byte Hi-ROM Entry Hi-ROM Program *5 Word Byte Word Byte 3 4 555h AAAh AAh XXXh A0h BA (BA) AAh 555h AAAh 555h AAAh 555h 98h AAh AAh 55h 555h AAAh PD F0h *6 SPA 60h SPA 40h SPA SD 88h A0h PA PD PA 90h XXXh XXXh 60h (BA) 55h 2AAh 2AAh 555h 2AAh 555h 55h 55h 555h AAAh 555h AAAh (Continued) 32 MB84VD2218XEA/H/2219XEA/H-70/85/90 (Continued) Bus Second Fourth Bus First Bus Third Bus Fifth Bus Sixth Bus Write Bus Read/Write Write Cycle Write Cycle Write Cycle Write Cycle CyWrite Cycle Cycle cles Req'd Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Command Sequence Hi-ROM Erase Word *5 Byte 6 Word Hi-ROM Exit *5 555h AAAh AAh 555h 4 Byte 2AAh 555h 55h AAAh 55h 555h AAAh 80h 555h AAAh AAh 2AAh 555h 55h HRA 30h (HRBA) 2AAh AAh 555h 555h 90h XXXh 00h (HRBA) AAAh *1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. *2: This command is valid during Fast Mode. *3: This command is valid while RESET = VID. *4: Valid Address is A6 to A0. *5: This command is valid during Hi-ROM mode. *6: The data "00h" is also acceptable. Note : The command combinations not described in Command Definitions are illegal. Address bits A20 to A11 = X = "H" or "L" for all address commands except for Program Address (PA) , Sector Address (SA) , and Bank Address (BA) . Bus operations are defined in DEVICE BUS OPERATION "User Bus Operations" Table. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank address (A20 to A15) SPA = Sector group address to be protected. Set sector group address (SPA) and (A6, A1, A0) = (0, 1, 0) . HRA = Address of the Hidden-ROM area. MB84VD2218XEA/H (Top Boot Type) Word mode : 1F8000h to 1FFFFFh Byte mode : 3F0000h to 3FFFFFh MB84VD2219XEA/H (Bottom Boot Type) Word mode : 000000h to 007FFFh Byte mode : 000000h to 00FFFFh HRBA = Bank address of the Hidden-ROM area MB84VD2218XEA/H (Top Boot Type) : A20 = A19 = A18 = A17 = A16 = A15 = 1 MB84VD2219XEA/H (Bottom Boot Type) : A20 = A19 = A18 = A17 = A16 = A15 = 0 RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotectedsector addresses. The system should generate the following address patterns : Word mode : 555h or 2AAh to addresses A10 to A0 Byte mode : AAAh or 555h to addresses A10 to A0 and A-1 33 MB84VD2218XEA/H/2219XEA/H-70/85/90 ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET and WP/ACC*2 VCCf/VCCs Supply*1 1, 3 RESET* * 1, 4 WP/ACC* * Symbol Rating Unit Min Max Tstg -55 +125 C TA -25 +85 C VIN, VOUT -0.3 VCCf + 0.3 V VCCs + 0.4 V VCCf, VCCs -0.3 +4.0 V VIN -0.5 +13.0 V VACC -0.5 +10.5 V *1 : Voltage is defined on the basis of VSS = GND = 0 V. *2 : Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCs + 0.4 V. During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCs + 2.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions, RESET pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V. Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *4 : Minimum DC input voltage on WP/ACC pin is -0.5 V.During voltage transitions, WP/ACC pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS Parameter Ambient Temperature VCCf/VCCs Supply Voltages Symbol Value Unit Min Max TA -25 +85 C VCCf, VCCs +2.7 +3.3 V Notes : * Voltage is defined on the basis of VSS = GND = 0 V. * Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 34 MB84VD2218XEA/H/2219XEA/H-70/85/90 DC CHARACTERISTICS Parameter Symbol Value Test Conditions Min Typ Max Unit Input Leakage Current ILI VIN = VSS to VCC -1.0 +1.0 A Output Leakage Current ILO VOUT = VSS to VCC -1.0 +1.0 A RESET Inputs Leakage Current ILIT VCC = VCC Max, RESET = 12.5 V 35 A ACC Input Leakage Current ILIA VCC = VCC Max, WP/ACC = VACC Max 20 mA tCYCLE = 5 MHz Byte 16 tCYCLE = 5 MHz Word 18 tCYCLE = 1 MHz Byte 7 tCYCLE = 1 MHz Word 7 35 Byte 51 Word 53 Byte 51 Word 53 35 mA Flash VCC Active Current (Read) *1 ICC1f CEf = VIL, OE = VIH mA mA Flash VCC Active Current (Program/Erase) *2 ICC2f CEf = VIL, OE = VIH Flash VCC Active Current (Read-While-Program) *5 ICC3f CEf = VIL, OE = VIH Flash VCC Active Current (Read-While-Erase) *5 ICC4f CEf = VIL, OE = VIH Flash VCC Active Current (Erase-Suspend-Program) ICC5f CEf = VIL, OE = VIH SRAM VCC Active Current ICC1s VCCs = VCC Max, CE1s = VIL, CE2s = VIH tCYCLE = 10 MHz 40 mA 40 mA ICC2s CE1s = 0.2 V, tCYCLE = 10 MHz CE2s = VCCs - 0.2 V, tCYCLE = 1 MHz SRAM VCC Active Current 8 mA Flash VCC Standby Current ISB1f VCCf = VCC Max, CEf = VCCf 0.3 V RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V 1 5 A Flash VCC Standby Current (RESET) ISB2f VCCf = VCC Max, RESET = VSS 0.3 V, WP/ACC = VCCf 0.3 V 1 5 A Flash VCC Current (Automatic Sleep Mode) *3 ISB3f VCCf = VCC Max, CEf = VSS 0.3 V RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V VIN = VCCf 0.3 V or VSS 0.3 V 1 5 A SRAM VCC Standby Current ISB1s CE1s VCCs - 0.2 V, CE2s VCCs - 0.2 V 7 A SRAM VCC Standby Current ISB2s CE2s 0.2 V 7 A mA mA mA (Continued) 35 MB84VD2218XEA/H/2219XEA/H-70/85/90 (Continued) Parameter Symbol Test Conditions Input Low Level VIL Input High Level Value Typ Max -0.3 0.5 V VIH 2.4 V * + 0.3 V Voltage for Sector Protection, and Temporary Sector Unprotection (RESET) *4 VID 11.5 12.5 V Voltage for Program Acceleration (WP/ACC) *4 VACC 8.5 9.0 9.5 V Output Low Voltage Level VOL VCCf = VCCs = VCC Min, IOL = 1.0 mA 0.4 V Output High Voltage Level VOH VCCf = VCCs = VCC Min, IOH = -0.5 mA 2.4 V Flash Low VCC Lock-Out Voltage VLKO 2.3 2.5 V CC 6 *1: The ICC current listed includes both the DC operating current and the frequency dependent component. *2: ICC active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when addresses remain stable for 150 ns. *4: Applicable for only VCC applying. *5: Embedded Algorithm (program or erase) is in progress. (@5 MHz) *6: VCC indicates the lower voltage of VCCf or VCCS. 36 Unit Min MB84VD2218XEA/H/2219XEA/H-70/85/90 AC CHARACTERISTICS * CE Timing Parameter CE Recover Time Symbol JEDEC Standard tCCR Test Setup Value Min 0 Unit ns * Timing Diagram for alternating SRAM to Flash CEf tCCR tCCR tCCR tCCR CE1s CE2s 37 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Read Only Operations Characteristics (Flash) Symbol Parameter Value Test Setup JEDEC Standard 85 90 Unit Min Max Min Max Min Max Read Cycle Time tAVAV tRC 70 85 90 ns Address to Output Delay tAVQV tACC CEf = VIL OE = VIL 70 85 90 ns Chip Enable to Output Delay tELQV tCE OE = VIL 70 85 90 ns Output Enable to Output Delay tGLQV tOE 30 35 40 ns Chip Enable to Output High-Z tEHQZ tDF 25 30 30 ns Output Enable to Output High-Z tGHQZ tDF 25 30 30 ns Output Hold Time From Addresses, CEf or OE, Whichever Occurs First tAXQX tOH 0 0 0 ns tREADY 20 20 20 s RESET Pin Low to Read Mode Test Conditions: Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or 3.0 V Timing measurement reference level Input : 0.5 x VCCf Output : 0.5 x VCCf 38 70 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Read Cycle (Flash) tRC Address Stable Address tACC CEf tDF tOE OE tOEH WE tCE High-Z DQ High-Z Output Valid * Hardware Reset/Read Operation Timing Diagram (Flash) tRC Address Address Stable tACC tRH CEf tRP tRH tCE RESET tOH High-Z DQ Output Valid 39 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Erase/Program Operations (Flash) Symbol Parameter Value Value Value 70 85 90 Unit JEDEC Standard Min Typ Max Min Typ Max Min Typ Max Write Cycle Time tAVAV tWC 70 85 90 ns Address Setup Time (WE to Addr.) tAVWL tAS 0 0 0 ns Address Setup Time to CEf Low During Toggle Bit Polling tASO 12 15 15 ns Address Hold Time (WE to Addr.) tWLAX tAH 45 45 45 ns Address Hold Time from CEf or OE High During Toggle Bit Polling tAHT 0 0 0 ns Data Setup Time tDVWH tDS 30 35 35 ns Data Hold Time tWHDX tDH 0 0 0 ns tOES 0 0 0 ns 0 0 0 ns 10 10 10 ns Output Enable Setup Time Output Enable Hold Time Read tOEH CEf High During Toggle Bit Polling tCEPH 20 20 20 ns OE High During Toggle Bit Polling tOEPH 20 20 20 ns Read Recover Time Before Write (OE to CEf) tGHEL tGHEL 0 0 0 ns Read Recover Time Before Write (OE to WE) tGHWL tGHWL 0 0 0 ns WE Setup Time (CEf to WE) tWLEL tWS 0 0 0 ns CEf Setup Time (WE to CEf) tELWL tCS 0 0 0 ns WE Hold Time (CEf to WE) tEHWH tWH 0 0 0 ns CEf Hold Time (WE to CEf) tWHEH tCH 0 0 0 ns Write Pulse Width tWLWH tWP 35 35 35 ns CEf Pulse Width tELEH tCP 35 35 35 ns Write Pulse Width High tWHWL tWPH 25 30 25 ns CEf Pulse Width High tEHEL tCPH 25 30 25 ns tWHWH1 tWHWH1 8 8 8 s 12 16 16 s tWHWH2 tWHWH2 0.2 1 1 s Toggle and Data Polling Byte Programming Operation Word Programming Operation Sector Erase Operation * 1 (Continued) 40 MB84VD2218XEA/H/2219XEA/H-70/85/90 (Continued) Parameter Value Symbol Parameter 70 85 90 Unit JEDEC Standard Min Typ Max Min Typ Max Min Typ Max tVCS 50 50 50 s tVLHT 4 4 4 s Rise Time to VID *2 tVIDR 500 500 500 ns Rise Time to VACC tVACCR 500 500 500 ns Recover Time from RY/BY tRB 0 0 0 ns RESET Pulse Width tRP 500 500 500 ns Delay Time from Embedded Output Enable tEOE 70 85 90 ns RESET Hold Time Before Read tRH 200 200 200 ns Program/Erase Valid to RY/BY Delay tBUSY 90 90 90 ns Erase Time-out Time *3 tTOW 50 50 50 s Erase Suspend Transition Time *4 tSPD 20 20 20 s VCCf Setup Time Voltage Transition Time * 2 *1: This does not include the preprogramming time. *2: This timing is for Sector Protection Operation. *3: The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will start. A time-out or "tTOW" from the rising edge of last CEf or WE whichever happens first will initiate the execution of the Sector Erase command (s) . *4: When the Erase Suspend command is written during the Sector Erase operation, the device will take maximum of "tSPD" to suspend the erase operation. 41 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Write Cycle (WE control) (Flash) 3rd Bus Cycle Address Data Polling 555H tWC PA tAS PA tRC tAH CEf tCS tCH tCE OE tGHWL tWP tOE tWHWH1 tWPH WE tDS tOH tDF tDH Data A0h PD DQ7 DOUT Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at byte address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence. * These waveforms are for the x16 mode (the addresses differ from x8 mode.) 42 DOUT MB84VD2218XEA/H/2219XEA/H-70/85/90 * Write Cycle (CEf control) (Flash) 3rd Bus Cycle Address Data Polling 555h tWC PA tAS PA tAH WE tWS tWH OE tGHEL tCP tWHWH1 tCPH CEf tDS tDH Data A0h PD DQ7 DOUT Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at word address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence. 43 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Write Cycle (CEf control) (Flash) 3rd Bus Cycle Address Data Polling 555H tWC PA tAS PA tAH WE tWS tWH OE tGHEL tCP tWHWH1 tCPH CEf tDS tDH Data A0h PD DQ7 DOUT Notes : * PA is address of the memory location to be programmed. * PD is data to be programmed at byte address. * DQ7 is the output of the complement of the data written to the device. * DOUT is the output of the data written to the device. * Figure indicates the last two bus cycles out of four bus cycle sequence. * These waveforms are for the x16 mode (the addresses differ from x8 mode.) 44 MB84VD2218XEA/H/2219XEA/H-70/85/90 * AC Waveforms Chip/Sector Erase Operations (Flash) Address 555h tWC 2AAh tAS 555h 555h SA* 2AAh tAH CEf tCS tCH OE tGHWL tWP tWPH WE tDS tDH AAh 30h for Sector Erase 55h 80h AAh 55h DQ 10h/ 30h tVCS VCCf * : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase. Note : These waveform are for the x16 mode (the addresses differ from x8 mode.) 45 MB84VD2218XEA/H/2219XEA/H-70/85/90 * AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash) CEf tCH tDF tOE OE tOEH WE tCE * DQ7 Data DQ7 = Valid Data DQ7 High-Z tWHWH1 or 2 DQ6 to DQ0 Data DQ0 to DQ6 = Output Flag tBUSY tEOE RY/BY * : DQ7 = Valid Data (the device has completed the Embedded operation.) 46 DQ0 to DQ6 Valid Data High-Z MB84VD2218XEA/H/2219XEA/H-70/85/90 * AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash) Address tAHT tASO tAHT tAS CEf tCEPH WE tOEH tOEPH tOEH OE tDH DQ6/DQ2 tOE tCE * Toggle Data Data Toggle Data Toggle Data Stop Toggling Output Valid tBUSY RY/BY * : DQ6 stops toggling (the device has completed the Embedded operation) . 47 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Bank-to-Bank Read/Write Timing Diagram (Flash) Address Read tRC Command tWC Read tRC Command tWC Read tRC Read tRC BA1 BA2 (555h) BA1 BA2 (PA) BA1 BA2 (PA) tAS tACC tAH tAS tAHT tCE CEf tOE tCEPH OE tGHWL tDF tOEH tWP WE tDS DQ Valid Output Valid Intput (A0h) tDH tDF Valid Output Valid Intput Valid Output Status (PD) Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1. BA2 : Address corresponding to Bank 2. 48 MB84VD2218XEA/H/2219XEA/H-70/85/90 * RY/BY Timing Diagram during Write/Erase Operations (Flash) CEf Rising edge of the last write pulse WE Entire programming or erase operations RY/BY tBUSY * RESET, RY/BY Timing Diagram (Flash) WE RESET tRP tRB RY/BY tREADY 49 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Temporary Sector Group Unprotection (Flash) VCCf tVIDR tVLHT tVCS VID VIH RESET CEf WE tVLHT tVLHT Program or Erase Command Sequence RY/BY Unprotection Period 50 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Extended Sector Group Protection (Flash) VCCf tVCS RESET tVLHT tVIDR tWC tWC SPAX Address SPAX SPAY A6, A0 A1 CEf OE TIME - OUT tWP WE Data 60h 60h 40h 01h 60h tOE SPAX : Sector Group Address to be protected SPAY : Next Group Sector Address to be protected TIME-OUT : Time-Out window = 250 s (Min) 51 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Accelerated Program (Flash) VCCf tVACCR tVLHT tVCS VACC VIH WP/ACC CEf WE tVLHT tVLHT Program Command Sequence RY/BY Acceleration period 52 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Read Cycle (SRAM) Value Parameter Symbol 70 85 90 Unit Min Max Min Max Min Max Read Cycle Time tRC 70 85 85 ns Address Access Time tAA 70 85 85 ns Chip Enable (CE1s) Access Time tCO1 70 85 85 ns Chip Enable (CE2s) Access Time tCO2 70 85 85 ns Output Enable Access Time tOE 35 45 45 ns LBs, UBs to Output Valid tBA 70 85 85 ns Chip Enable (CE1s Low and CE2s High) to Output Active tCOE 5 5 5 ns Output Enable Low to Output Active tOEE 0 0 0 ns UBs, LBs Enable Low to Output Active tBE 0 0 0 ns Chip Enable (CE1s High or CE2s Low) to Output High-Z tOD 25 35 35 ns Output Enable High to Output High-Z tODO 25 35 35 ns UBs, LBs Output Enable to Output High-Z tBD 25 35 35 ns Output Data Hold Time tOH 10 10 10 ns Test Conditions - Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or VCCs Timing measurement reference level Input : 0.5 x VCCs Output : 0.5 x VCCs 53 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Read Cycle (SRAM) tRC Address tAA tOH tCO1 CE1s tCOE tCO2 tOD CE2s tOD tOE OE tODO tOEE LBS, UBS tBA tBD tBE tCOE DQ Note : WE remains "H" during the read cycle. 54 Valid Data Out MB84VD2218XEA/H/2219XEA/H-70/85/90 * Write Cycle (SRAM) Value Parameter Symbol 70 85 90 Unit Min Max Min Max Min Max Write Cycle Time tWC 70 85 85 ns Write Pulse Width tWP 55 60 60 ns Chip Enable to End of Write tCW 60 70 70 ns Address valid to End of Write tAW 60 70 70 ns UBs, LBs to End of Write tBW 60 70 70 ns Address Setup Time tAS 0 0 0 ns Write Recovery Time tWR 0 0 0 ns WE Low to Output High-Z tODW 25 35 35 ns WE High to Output Active tOEW 0 0 0 ns Data Setup Time tDS 30 35 35 ns Data Hold Time tDH 0 0 0 ns 55 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Write Cycle *1 (WE control) (SRAM) tWC Address tAS tWP tWR WE tAW tCW CE1s CE2s tCW tBW LBS, UBS tODW DOUT tOEW *2 *3 tDS DIN *4 tDH Valid Data In *4 *1: If OE is "H" during the write cycle, the outputs will remain at High-Z. *2: If CE1s goes "L" (or CE2s goes "H") coincident with or after WE goes "L", the output will remain at High-Z. *3: If CE1s goes "H" (or CE2s goes "L") coincident with or before WE goes "H", the output will remain at High-Z. *4: Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 56 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Write Cycle *1 (CE1s control) (SRAM) tWC Address tAS tWR tWP WE tAW tCW CE1s CE2s tCW tBW LB, UB tBE tCOE tODW DOUT tDS DIN *2 tDH Valid Data In *1: If OE is "H" during the write cycle, the outputs will remain at High-Z. *2: Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 57 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Write Cycle *1 (CE2s Control) (SRAM) tWC Adrress tAS tWP tWR WE tCW CE1s tAW CE2s tCW tBW LBS, UBS tBE tCOE tODW DOUT tDS DIN *2 tDH Valid Data In *1: If OE is "H" during the write cycle, the outputs will remain at High-Z. *2: Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 58 MB84VD2218XEA/H/2219XEA/H-70/85/90 * Write Cycle *1 (LBs, UBs Control) (SRAM) tWC Address tWP tWR WE tCW CE1s tCW CE2s tAW tAS tBW LBS, UBS tBE tCOE tODW DOUT tDS DIN *2 tDH Valid Data In *1: If OE is "H" during the write cycle, the outputs will remain at High-Z. *2: Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 59 MB84VD2218XEA/H/2219XEA/H-70/85/90 ERASE AND PROGRAMMING PERFORMANCE (Flash) Limits Parameter Unit Comment Min Typ Max Sector Erase Time 1 10 s Excludes programming time prior to erasure Byte Programming Time 8 300 s Excludes system-level overhead Word Programming Time 16 360 s Excludes system-level overhead Chip Programming Time 100 s Excludes system-level overhead 100,000 cycle Erase/Program Cycle DATA RETENTION CHARACTERISTICS (SRAM) Parameter Symbol Data Retention Supply Voltage VDH = 3.0 V Standby Current Chip Deselect to Data Retention Mode Time Recovery Time Value Unit Min Typ Max VDH 1.5 3.3 V IDDS2 1.5 7 A tCDR 0 ns tR tRC ns Note : tRC : Read cycle time * CE1s Controlled Data Retention Mode *1 VCCs DATA RETENTION MODE 2.7 V *2 VIH VDH CE1s tCDR *2 VCCS - 0.2 V tR GND *1: In CE1s controlled data retention mode, input level of CE2s should be fixed VCCs to VCCs - 0.2 V or VSS to 0.2 V during data retention mode. Other input and input/output pins can be used between -0.3 V to VCCs + 0.3 V. *2: When CE1s is operating at the VIH Min level, the standby current is given by ISB1s during the transition of VCCs from 3.3 V to VIH Min level. 60 MB84VD2218XEA/H/2219XEA/H-70/85/90 * CE2s Controlled Data Retention Mode VCCs DATA RETENTION MODE 2.7 V VDH VIH CE2s tCDR tR VIL 0.2 V GND Note: In CE2s controlled data retention mode, input and input/output pins can be used between -0.3 V to VCCs + 0.3 V. PACKAGE PIN CAPACITANCE Parameter Symbol Test Setup Value Typ Max Unit Input Capacitance CIN VIN = 0 11 14 pF Output Capacitance COUT VOUT = 0 12 16 pF Control Pin Capacitance CIN2 VIN = 0 14 16 pF WP/ACC Pin Capacitance CIN3 VIN = 0 21.5 26 pF Note : Test conditions TA = +25C, f = 1.0 MHz HANDLING OF PACKAGE Please handle this package carefully since the sides of package are created with acute angles. CAUTION * The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when autoselect and sector group protection function are used, then the high voltage (VID) can be applied to RESET. * Without the high voltage (VID) , Sector group protection can be achieved by using "Extended Sector Group Protection" command. 61 MB84VD2218XEA/H/2219XEA/H-70/85/90 ORDERING INFORMATION MB84VD2218 X EA -85 PBS PACKAGE TYPE PBS = 71-ball BGA SPEED OPTION Device Revision (Valid Combination) EA EH Bank Size 2 = 4 Mbit / 3 = 8 Mbit / 4 = 16 Mbit / 28 Mbit 24 Mbit 16 Mbit DEVICE NUMBER/DESCRIPTION 32 Mega-bit (4 M x 8-bit or 2 M x 16-bit) Dual Operation Flash Memory 3.0 V-only Read, Program, and Erase 4 Mega-bit (512 K x 8-bit or 256 K x 16-bit) SRAM BOOT CODE SECTOR ARCHITECTURE 84VD2218 = Top sector 84VD2219 = Bottom sector 62 MB84VD2218XEA/H/2219XEA/H-70/85/90 PACKAGE DIMENSION 71-ball plastic BGA (BGA-71P-M02) 8.80(.346) +0.15 11.000.10(.433.004) 1.05 0.10 +.006 .041 -.004 (Mounting height) 0.380.10 (Stand off) (.015.004) 7.000.10 (.276.004) 7.20(.283) 5.60(.220)REF 0.80 (.031) 8 7 6 5 4 3 2 1 5.60(.220) REF 0.80 (.031) M L K J H G F E D C B A INDEX-MARK AREA +0.10 71-O0.45 -0.05 +.004 71-O.018 -.002 0.08(.003) M 0.10(.004) C 2000 FUJITSU LIMITED B71002S-1c-1 DImensions in mm (inches). 63 MB84VD2218XEA/H/2219XEA/H-70/85/90 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0204 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.