74ALVCH16501DGG,11 - NXP Semiconductors

1. General description

The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus

compatible outputs in both send and receive directions. Data flow in each direction is

controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock

(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent

mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a

HIGH or LOW logic level. If LEAB is LOW, the A-bus dat a is stored in the latch/flip-flop on

the LOW-to HIGH tran sition of CPAB. When OEAB is HIGH, the output s are active. When

OEAB is LOW, the outputs are in the high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The

output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW.

To ensure the high-impedance state during power-up or power-down, OEBA should be

tied to VCC through a pull-up resistor and OEAB should be tied to GND through a

pull-down resistor; the minimum value of the resistor is determined by the

current-sinking/current-sourcing capability of the driver.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic

level.

2. Features and benefits

Wide supply voltage range from 1.2 V to 3.6 V

Complies with JEDEC standard JESD8-B

CMOS low power consumption

Direct interface with TTL levels

Current drive 24 mA at VCC = 3.0 V

Universal bus transceiver with D-type latches and D-type flip-flops capable of

operating in tran sparent , latc he d or clock ed mo de

All inputs have bus hold circuitry

Output drive capability 50  transmission lines at 85 C

3-state non-inverting outputs for bus-oriented applications

74ALVCH16501

18-bit universal bus transceiver; 3-state

Rev. 5 — 10 July 2012 Product data sheet

Product data sheet Rev. 5 — 10 July 2012 2 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

3. Ordering information

4. Functional diagram

Table 1. Ordering information

Type number Package

Tem perature range Name Description Version

74ALVCH16501DGG 40 C to +85 CTSSOP56 plastic thin shrink small outline package;

56 leads; body width 6.1 mm SOT364-1

74ALVCH16501DL 40 C to +85 CSSOP56 plastic shrink small outline package; 56 leads;

body wid th 7.5 mm SOT371-1

Fig 1. Logic symbol Fig 2. IEC logic symbol

001aal718

354

552

651

849

948

10 47

12 45

13 44

14 43

15 42

A10

16 41

B10

A11

17 40

B11

A12

19 38

B12

A13

20 37

B13

A14

21 36

B14

A15

23 34

B15

A16

24 33

B16

A17

26 31

B17

OEAB

127

OEBA

LEAB

228

LEBA

CPAB

55 30

CPBA

001aal717

OEAB

OEBA

CPAB 2

LEAB

CPBA 28

LEBA

A0 3D 1 1

416D

54 B0

A1 52 B1

A2 51 B2

A3 49 B3

A4 48 B4

A5 47 B5

A6 45 B6

A7 44 B7

A8 43 B8

A9 42 B9

A10 41 B10

A11 40 B11

A12 38 B12

A13 37 B13

A14 36 B14

A15 34 B15

A16 33 B16

A17 31 B17

EN1

EN4

2C3

5C6

Product data sheet Rev. 5 — 10 July 2012 3 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

Fig 3. Bus hold circuit

001aal733

VCC

to internal circuitdata input

Fig 4. Logic diag ram

001aal719

OEAB

CPBA

LEBA

CPAB

LEAB

OEBA

A1 B1

18 IDENTICAL CHANNELS

Product data sheet Rev. 5 — 10 July 2012 4 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 5. Pin configuratio n

74ALVCH16501

OEAB GND

LEAB CPAB

A0 B0

GND GND

A1 B1

A2 B2

VCC VCC

A3 B3

A4 B4

A5 B5

GND GND

A6 B6

A7 B7

A8 B8

A9 B9

A10 B10

A11 B11

GND GND

A12 B12

A13 B13

A14 B14

VCC VCC

A15 B15

A16 B16

GND GND

A17 B17

OEBA CPBA

LEBA GND

001aal716

Table 2. Pin description

Symbol Pin Description

OEAB 1output enable A-to-B input

LEAB 2latch enable A-to-B input

A0 to A17 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 data inputs or outputs

GND 4, 11 , 18, 25, 29, 32, 39, 46, 53, 56 ground (0 V)

VCC 7, 22, 35, 50 positive supply voltage

OEBA 27 output enable B-to-A

LEBA 28 latch enable B-to-A

Product data sheet Rev. 5 — 10 July 2012 5 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

6. Functional description

6.1 Function table

[1] A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CPBA.

H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the enable or clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the enable or clock transition;

X = don’t care;

Z = high-impedance OFF-state;

 = HIGH-to-LOW clock transition;

 = LOW-to-HIGH clock transition.

7. Limiting values

CPBA 30 clock input B-to-A

B0 to B17 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 data inputs or outputs

CPAB 55 clock input A-to-B

Table 2. Pin description …continued

Symbol Pin Description

Table 3. Function table[1]

Inputs Output Operating mode

OEAB LEAB CPAB An Bn

L X X X Z disabled

HHXHH transparent

H H X L L

HX h H latch data and display

HX l L

H L h H clock data and display

H L l L

H L H or L X H hold data and display

H L H or L X L

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +4.6 V

IIK input clamping current VI < 0 V 50 -mA

VIinput voltage control inputs [1] 0.5 +4.6 V

data inputs [1] 0.5 VCC + 0.5 V

IOK output clamping current VO > VCC or VO < 0 V - 50 mA

VOoutput voltage [1] 0.5 VCC + 0.5 V

IOoutput curren t VO = 0 V to VCC -50 mA

ICC supply current -100 mA

Product data sheet Rev. 5 — 10 July 2012 6 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Above 55 C the value of Ptot derates linearly with 11.3 mW/K.

[3] Above 55 C the value of Ptot derates linearly with 8 mW/K.

8. Recommended operating conditions

IGND ground current 100 -mA

Tstg storage temperature 65 +150 C

Ptot total power dissipation Tamb = 40 C to +125 C

SSOP package [2] -850 mW

TSSOP package [3] -600 mW

Table 4. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage maximum speed performance

CL = 30 pF 2.3 -2.7 V

CL = 50 pF 3.0 -3.6 V

low-voltage applications 1.2 -3.6 V

VIinput voltage 0 - VCC V

VOoutput voltage 0 - VCC V

Tamb ambient temperature in free air 40 -+85 C

t/Vinput transition rise and fall

rate VCC = 2.3 V to 3.0 V 0 - 20 ns/V

VCC = 3.0 V to 3.6 V 0 - 10 ns/V

Product data sheet Rev. 5 — 10 July 2012 7 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

9. Static characteristics

[1] All typical values are measured at Tamb = 25 C.

[2] Valid for data inputs of bus hold parts only.

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ[1] Max Unit

Tamb = 40 C to +85 C

VIH HIGH-level input voltage VCC = 2.3 V to 2.7 V 1.7 1.2 - V

VCC = 2.7 V to 3.6 V 2.0 1.5 - V

VIL LOW-level input voltage VCC = 2.3 V to 2.7 V -1.2 0.7 V

VCC = 2.7 V to 3.6 V -1.5 0.8 V

VOH HIGH-level output voltage VI = VIH or VIL

IO = 100 A;

VCC = 2.3 V to 3.6 V VCC  0.2 VCC - V

IO = 6 mA; VCC = 2.3 V VCC  0.3 VCC  0.08 - V

IO = 12 mA; VCC = 2.3 V VCC  0.6 VCC  0.26 - V

IO = 12 mA; VCC = 2.7 V VCC  0.5 VCC  0.14 - V

IO = 12 mA; VCC = 3.0 V VCC  0.6 VCC  0.09 - V

IO = 24 mA; VCC = 3.0 V VCC  1.0 VCC  0.28 - V

VOL LOW-level output voltage VI = VIH or VIL

IO = 100 A;

VCC = 2.3 V to 3.6 V -GND 0.20 V

IO = 6 mA; VCC = 2.3 V -0.07 0.40 V

IO = 12 mA; VCC = 2.3 V -0.15 0.70 V

IO = 12 mA; VCC = 2.7 V -0.14 0.40 V

IO = 24 mA; VCC = 3.0 V -0.27 0.55 V

IIinput leakage current VI = VCC or GND;

VCC = 2.3 V to 3.6 V -0.1 5A

IOZ OFF-st ate output current VI = VIH or VIL;

VO = VCC or GND;

VCC = 2.7 V to 3.6 V

-0.1 10 A

ICC supply current VCC = 2.3 V to 3.6 V;

VI = VCC or GND; IO = 0 A -0.2 40 A

ICC additional supply current per data I/O pin; VCC = 2.3 V

to 3.6 V; VI = VCC  0.6 V;

IO = 0 A

-150 750 A

IBHL bus hold LOW curre nt VCC = 2.3 V; VI = 0.7 V [2] 45 - - A

VCC = 3.0 V; VI = 0.8 V [2] 75 150 -A

IBHH bus hold HIGH current VCC = 2.3 V; VI = 1.7 V [2] 45 - - A

VCC = 3.0 V; VI = 2.0 V [2] 75 175 -A

IBHLO bus hold LOW ov erd ri v e curre n t VCC = 3.6 V [2] 500 - - A

IBHHO bus hold HIGH overdrive current VCC = 3.6 V [2] 500 - - A

CIinput capacitance -4.0 -pF

CI/O input/output capacitance -8.0 -pF

Product data sheet Rev. 5 — 10 July 2012 8 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

10. Dynamic characteristics

Table 7. Dynamic characteristics

At recommended operating conditions. Volt ages are referenced to GND (ground = 0 V); test circuit Figure 10.

Symbol Parameter Conditions Min Typ[1] Max Unit

Tamb = 40 C to +85 C

fmax maximum frequency see Figure 8

VCC = 2.3 V to 2.7 V [2] 150 333 -MHz

VCC = 3.0 V to 3.6 V [3] 150 340 -MHz

VCC = 2.7 V 150 333 -MHz

tpd propagation delay An to Bn; Bn to An; see Figure 6 [4]

VCC = 2.3 V to 2.7 V [2] 1.0 2.8 5.1 ns

VCC = 3.0 V to 3.6 V [3] 1.0 3.0 4.2 ns

VCC = 2.7 V -3.0 4.6 ns

LEAB, LEBA to Bn, An; see Figure 8

VCC = 2.3 V to 2.7 V [2] 1.1 3.5 6.1 ns

VCC = 3.0 V to 3.6 V [3] 1.3 3.4 4.8 ns

VCC = 2.7 V -3.6 5.3 ns

CPAB, CPBA to Bn, An; see Figure 8

VCC = 2.3 V to 2.7 V [2] 1.0 3.3 6.1 ns

VCC = 3.0 V to 3.6 V [3] 1.4 3.3 4.9 ns

VCC = 2.7 V -3.4 5.6 ns

ten enable time OEBA to An; see Figure 7 [4]

VCC = 2.3 V to 2.7 V [2] 1.3 2.8 6.3 ns

VCC = 3.0 V to 3.6 V [3] 1.1 2.5 5.0 ns

VCC = 2.7 V -3.3 6.0 ns

OEAB to Bn; see Figure 7

VCC = 2.3 V to 2.7 V [2] 1.0 2.5 5.8 ns

VCC = 3.0 V to 3.6 V [3] 1.0 2.4 4.6 ns

VCC = 2.7 V -2.7 5.3 ns

tdis disable time OEBA to An; see Figure 7 [4]

VCC = 2.3 V to 2.7 V [2] 1.3 2.5 5.3 ns

VCC = 3.0 V to 3.6 V [3] 1.3 3.1 4.2 ns

VCC = 2.7 V -3.3 4.6 ns

OEAB to Bn; see Figure 7

VCC = 2.3 V to 2.7 V [2] 1.5 2.5 6.2 ns

VCC = 3.0 V to 3.6 V [3] 1.4 2.9 5.0 ns

VCC = 2.7 V -3.6 5.7 ns

Product data sheet Rev. 5 — 10 July 2012 9 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

[1] All typical values are measured at Tamb = 25 C.

[2] Typical values are measured at VCC = 2.5 V.

[3] Typical values are measured at VCC = 3.3 V.

[4] tpd is the same as tPLH and tPHL.

ten is the same as tPZL and tPZH.

tdis is the same as tPLZ and tPHZ.

[5] CPD is used to determine the dynamic power dissipation (PD in W).

PD = CPD  VCC2  fi  N +  (CL  VCC2  fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

 (CL  VCC2  fo) = sum of outputs.

tWpulse width LEAB, LEBA HIGH; see Figure 8

VCC = 2.3 V to 2.7 V [2] 3.3 0.8 -ns

VCC = 3.0 V to 3.6 V [3] 3.3 0.9 -ns

VCC = 2.7 V 3.3 0.7 -ns

CPAB, CPBA HIGH or LOW; see Figure 8

VCC = 2.3 V to 2.7 V [2] 3.3 2.0 -ns

VCC = 3.0 V to 3.6 V [3] 3.3 1.1 -ns

VCC = 2.7 V 3.3 1.4 -ns

tsu set-up time An, Bn to CPAB, CPBA; see Figure 9

VCC = 2.3 V to 2.7 V [2] 1.7 0.1 -ns

VCC = 3.0 V to 3.6 V [3] 1.3 0.3 -ns

VCC = 2.7 V 1.4 0.1 -ns

An, Bn to LEAB, LEBA; see Figure 9

VCC = 2.3 V to 2.7 V [2] 1.1 0.1 -ns

VCC = 3.0 V to 3.6 V [3] 1.0 0.3 -ns

VCC = 2.7 V 1.0 0.2 -ns

thhold time An, Bn to CPAB, CPBA; see Figure 9

VCC = 2.3 V to 2.7 V [2] 1.7 0.3 -ns

VCC = 3.0 V to 3.6 V [3] 1.3 0.4 -ns

VCC = 2.7 V 1.6 0.3 -ns

An, Bn to LEAB, LEBA; see Figure 9

VCC = 2.3 V to 2.7 V [2] 1.6 0.3 -ns

VCC = 3.0 V to 3.6 V [3] 1.2 0.1 -ns

VCC = 2.7 V 1.5 0.1 -ns

CPD power dissipation

capacitance per buffer; VI = GND to VCC [5]

outputs enabled -21 -pF

outputs disabled - 3 - pF

Table 7. Dynamic characteristics …continued

At recommended operating conditions. Volt ages are referenced to GND (ground = 0 V); test circuit Figure 10.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 5 — 10 July 2012 10 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

11. Waveforms

Measurement points are given in Table 8.

VOL and VOH are typical output levels that occur with the output load.

Fig 6. Propagation delay, data input (An, Bn) to data output (Bn, An)

001aal734

An, Bn

input

Bn, An

output

tPHL tPLH

GND

VOH

VOL

Measurement points are given in Table 8.

VOL and VOH are typical output levels that occur with the output load.

Fig 7. 3-state output enable and disable times

001aal721

PLZ

PHZ

outputs

disabled outputs

enabled

outputs

enabled

An, Bn output

LOW-to-OFF

OFF-to-LOW

An, Bn output

HIGH-to-OFF

OFF-to-HIGH

OEAB, OEBA

input

GND

PZL

PZH

Product data sheet Rev. 5 — 10 July 2012 11 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

Measurement points are given in Table 8.

VOL and VOH are typical output levels that occur with the output load.

Fig 8. Propagation delay, latch enable input (LEAB , LEBA) and clock pulse in put (CPAB , CPBA) to data output,

and pulse width

001aal720

PHL

PLH

1 / f

max

LExx

input

CPxx

input

An, Bn

output

GND

Measurement points are given in Table 8.

Fig 9. Data set-up and hold times (An, Bn inputs to LEAB, LEBA, CPAB and CPBA inputs)

001aal722

GND

An, Bn

input

CPxx, LExx

input V

Table 8. Measur emen t points

Supply voltage Input Output

VCC VIVMVMVXVY

2.3 V to 2.7 V and < 2.3 V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V

2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0. 3 V

3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0. 3 V

Product data sheet Rev. 5 — 10 July 2012 12 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

12. Test information

Test data is given in Table 9.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance includes jig and probe capacitance.

RT = Termination resistance should be equal to Zo of pulse generator.

VEXT = External voltage for measuring switching times.

Fig 10. Load circuit for meas urin g sw itc h ing times

VEXT

VCC

VIVO

mna616

DUT

Table 9. Test data

Supply voltage Input Load VEXT

VCC VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH

2.3 V to 2.7 V VCC  2.0 ns 30 pF 500 open 2  VCC GND

2.7 V 2.7 V 2.5 ns 50 pF 500 open 2  VCC GND

3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 2  VCC GND

Product data sheet Rev. 5 — 10 July 2012 13 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

13. Package outline

Fig 11. Package outline SOT364-1 (TSSOP56)

UNIT A1A2A3bpcD

(1) E(2) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.2

0.1 8

0.1

DIMENSIONS (mm are the original dimensions).

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

SOT364-1 99-12-27

03-02-19

detail X

(A )

0.25

128

56 29

pin 1 index

1.05

0.85 0.28

0.17 0.2

0.1 14.1

13.9 6.2

6.0 0.5 1

8.3

7.9 0.50

0.35 0.5

0.1

0.080.25

0.8

0.4

EvMA

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1

max.

1.2

2.5

5 mm

scale

MO-153

Product data sheet Rev. 5 — 10 July 2012 14 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

Fig 12. Package outline SOT371-1 (SSOP56)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.4

0.2 2.35

2.20 0.25 0.3

0.2 0.22

0.13 18.55

18.30 7.6

7.4 0.635 10.4

10.1 1.0

0.6 1.2

1.0 0.85

0.40 8

0.180.251.4 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT371-1 99-12-27

03-02-18

(1)

vMA

56 29

MO-118

detail X

(A )

pin 1 index

0 5 10 mm

scale

SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1

max.

2.8

Product data sheet Rev. 5 — 10 July 2012 15 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

14. Abbreviations

15. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

DUT Device Under Test

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Order numbe r Supersedes

74ALVCH16501 v.5 20120710 Product data sheet - - 74ALVCH16501 v.4

Modifications: •Table 8 corrected (errata).

74ALVCH16501 v.4 20111117 Product data sheet - - 74ALVCH16501 v.3

Modifications: •Legal pages updated.

74ALVCH16501 v.3 20100402 Product data sheet - - 74ALVCH16501 v.2

74ALVCH16501 v.2 19980929 Product specification - - 74ALVCH16501 v.1

74ALVCH16501 v.1 19980929 Product specification - - -

Product data sheet Rev. 5 — 10 July 2012 16 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) d escribed i n this docume nt may have changed si nce this docum ent was pub lished and may dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

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internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

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with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

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data sheet shall define the specification of the product as agreed between

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customer have explicitly agreed otherwise in writing. In no event however,

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deemed to off er functions and qualities beyon d those described in the

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damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environment al

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semicondu ctors products , and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the appl ication or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress rating s only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are so ld subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the term s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document cont ains the product specification.

Product data sheet Rev. 5 — 10 July 2012 17 of 18

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automo tive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specificatio ns, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product cl aims resulting f rom customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74ALVCH16501

18-bit universal bus transceiver; 3-state

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 July 2012

Document identi fier: 74ALVCH 16501

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

6.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Recommended operating conditions. . . . . . . . 6

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

12 Test information. . . . . . . . . . . . . . . . . . . . . . . . 12

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

17 Contact information. . . . . . . . . . . . . . . . . . . . . 17

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18