DM74LS163AM - National Semiconductor

TL/F/6397

54LS161A/DM54LS161A/DM74LS161A, 54LS163A/DM54LS163A/DM74LS163A Synchronous

4-Bit Binary Counters

May 1992

54LS161A/DM54LS161A/DM74LS161A,

54LS163A/DM54LS163A/DM74LS163A

Synchronous 4-Bit Binary Counters

General Description

These synchronous, presettable counters feature an inter-

nal carry look-ahead for application in high-speed counting

designs. The LS161A and LS163A are 4-bit binary counters.

The carry output is decoded by means of a NOR gate, thus

preventing spikes during the normal counting mode of oper-

ation. Synchronous operation is provided by having all flip-

flops clocked simultaneously so that the outputs change co-

incident with each other when so instructed by the count-

enable inputs and internal gating. This mode of operation

eliminates the output counting spikes which are normally

associated with asynchronous (ripple clock) counters. A

buffered clock input triggers the four flip-flops on the rising

(positive-going) edge of the clock input waveform.

These counters are fully programmable; that is, the outputs

may be preset to either level. As presetting is synchronous,

setting up a low level at the load input disables the counter

and causes the outputs to agree with the setup data after

the next clock pulse, regardless of the levels of the enable

input. The clear function for the LS161A is asynchronous;

and a low level at the clear input sets all four of the flip-flop

outputs low, regardless of the levels of clock, load, or en-

able inputs. The clear function for the LS163A is synchro-

nous; and a low level at the clear inputs sets all four of the

flip-flop outputs low after the next clock pulse, regardless of

the levels of the enable inputs. This synchronous clear al-

lows the count length to be modified easily, as decoding the

maximum count desired can be accomplished with one ex-

ternal NAND gate. The gate output is connected to the clear

input to synchronously clear the counter to all low outputs.

The carry look-ahead circuitry provides for cascading coun-

ters for n-bit synchronous applications without additional

gating. Instrumental in accomplishing this function are two

count-enable inputs and a ripple carry output.

Both count-enable inputs (P and T) must be high to count,

and input T is fed forward to enable the ripple carry output.

The ripple carry output thus enabled will produce a high-lev-

el output pulse with a duration approximately equal to the

high-level portion of the QAoutput. This high-level overflow

ripple carry pulse can be used to enable successive cascad-

ed stages. High-to-low level transitions at the enable P or T

inputs may occur, regardless of the logic level of the clock.

These counters feature a fully independent clock circuit.

Changes made to control inputs (enable P or T or load) that

will modify the operating mode have no effect until clocking

occurs. The function of the counter (whether enabled, dis-

abled, loading, or counting) will be dictated solely by the

conditions meeting the stable set-up and hold times.

Features

YSynchronously programmable

YInternal look-ahead for fast counting

YCarry output for n-bit cascading

YSynchronous counting

YLoad control line

YDiode-clamped inputs

YTypical propagation time, clock to Q output 14 ns

YTypical clock frequency 32 MHz

YTypical power dissipation 93 mW

YAlternate Military/Aerospace device (54LS161,

54LS163) is available. Contact a National Semiconduc-

tor Sales Office/Distributor for specificaitons.

Connection Diagram

Dual-In-Line Package

TL/F/6397–1

Order Numbers 54LS161ADMQB, 54LS161AFMQB,

54LS161ALMQB, 54LS163ADMQB, 54LS163AFMQB,

54LS163ALMQB, DM54LS161AJ, DM54LS161AW,

DM54LS163AJ, DM54LS163AW, DM74LS161AM,

DM74LS161AN, DM74LS163AM or DM74LS163AN

See NS Package Number E20A, J16A,

M16A, N16E or W16A

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range

DM54LS and 54LS b55§Ctoa

125§C

DM74LS 0§Ctoa

70§C

Storage Temperature Range b65§Ctoa

150§C

Note:

The ‘‘Absolute Maximum Ratings’’ are those values

beyond which the safety of the device cannot be guaran-

teed. The device should not be operated at these limits. The

parametric values defined in the ‘‘Electrical Characteristics’’

table are not guaranteed at the absolute maximum ratings.

The ‘‘Recommended Operating Conditions’’ table will define

the conditions for actual device operation.

Recommended Operating Conditions

Symbol Parameter DM54LS161A DM74LS161A Units

Min Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.7 0.8 V

IOH High Level Output Current b0.4 b0.4 mA

IOL Low Level Output Current 4 8 mA

fCLK Clock Frequency (Note 1) 0 25 0 25 MHz

Clock Frequency (Note 2) 0 20 0 20 MHz

tWPulse Width Clock 20 6 20 6 ns

(Note 1) Clear 20 9 20 9

Pulse Width Clock 25 25 ns

(Note 2) Clear 25 25

tSU Setup Time Data 20 8 20 8

(Note 1) Enable P 25 17 25 17 ns

Load 25 15 25 15

Setup Time Data 20 20

(Note 2) Enable P 30 30 ns

Load 30 30

tHHold Time Data 0 b30

3ns

(Note 1) Others 0 b30

Hold Time Data 5 5 ns

(Note 2) Others 5 5

tREL Clear Release Time (Note 1) 20 20 ns

Clear Release Time (Note 2) 25 25 ns

TAFree Air Operating Temperature b55 125 0 70 §C

Note 1: CLe15 pF, RLe2kX,T

Ae25§C and VCC e5.5V.

Note 2: CLe50 pF, RLe2kX,T

Ae25§C and VCC e5.5V.

’LS161 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

VIInput Clamp Voltage VCC eMin, IIeb

18 mA b1.5 V

VOH High Level Output VCC eMin, IOH eMax DM54 2.5 3.4 V

Voltage VIL eMax, VIH eMin DM74 2.7 3.4

VOL Low Level Output VCC eMin, IOL eMax DM54 0.25 0.4

Voltage VIL eMax, VIH eMin DM74 0.35 0.5 V

IOL e4 mA, VCC eMin DM74 0.25 0.4

IIInput Current @Max VCC eMax Enable T 0.2

Input Voltage VIe7V Clock 0.2 mA

Load 0.2

Others 0.1

IIH High Level Input VCC eMax Enable T 40

Current VIe2.7V Clock 40 mA

Load 40

Others 20

IIL Low Level Input VCC eMax Enable T b0.8

Current VIe0.4V Clock b0.8 mA

Load b0.8

Others b0.4

IOS Short Circuit VCC eMax DM54 b20 b100 mA

Output Current (Note 2) DM74 b20 b100

ICCH Supply Current with VCC eMax 18 31 mA

Outputs High (Note 3)

ICCL Supply Current with VCC eMax 19 32 mA

Outputs Low (Note 4)

Note 1: All typicals are at VCC e5V, TAe25§C.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open.

Note 4: ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open.

’LS161 Switching Characteristics

at VCC e5V and TAe25§C (See Section 1 for Test Waveforms and Output Load)

From (Input) RLe2kX

Symbol Parameter To (Output) CLe15 pF CLe50 pF Units

Min Max Min Max

fMAX Maximum Clock Frequency 25 20 MHz

tPLH Propagation Delay Time Clock to 25 30 ns

Low to High Level Output Ripple Carry

tPHL Propagation Delay Time Clock to 30 38 ns

High to Low Level Output Ripple Carry

tPLH Propagation Delay Time Clock to Any Q 22 27 ns

Low to High Level Output (Load High)

tPHL Propagation Delay Time Clock to Any Q 27 38 ns

High to Low Level Output (Load High)

’LS161 Switching Characteristics

at VCC e5V and TAe25§C (See Section 1 for Test Waveforms and Output Load) (Continued)

From (Input) RLe2kX

Symbol Parameter To (Output) CLe15 pF CLe50 pF Units

Min Max Min Max

tPLH Propagation Delay Time Clock to Any Q 24 30 ns

Low to High Level Output (Load Low)

tPHL Propagation Delay Time Clock to Any Q 27 38 ns

High to Low Level Output (Load Low)

tPLH Propagation Delay Time Enable T to 14 27 ns

Low to High Level Output Ripple Carry

tPHL Propagation Delay Time Enable T to 15 27 ns

High to Low Level Output Ripple Carry

tPHL Propagation Delay Time Clear to 28 45 ns

High to Low Level Output Any Q

Recommended Operating Conditions

Symbol Parameter DM54LS163A DM74LS163A Units

Min Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.7 0.8 V

IOH High Level Output Current b0.4 b0.4 mA

IOL Low Level Output Current 4 8 mA

fCLK Clock Frequency (Note 1) 0 25 0 25 MHz

Clock Frequency (Note 2) 0 20 0 20 MHz

tWPulse Width Clock 20 6 20 6 ns

(Note 1) Clear 20 9 20 9

Pulse Width Clock 25 25 ns

(Note 2) Clear 25 25

tSU Setup Time Data 20 8 20 8

(Note 1) Enable P 25 17 25 17 ns

Load 25 15 25 15

Setup Time Data 20 20

(Note 2) Enable P 30 30 ns

Load 30 30

tHHold Time Data 0 b30

3ns

(Note 1) Others 0 b30

Hold Time Data 5 5 ns

(Note 2) Others 5 5

tREL Clear Release Time (Note 1) 20 20 ns

Clear Release Time (Note 2) 25 25 ns

TAFree Air Operating Temperature b55 125 0 70 §C

Note 1: CLe15 pF, RLe2kX,T

Ae25§C and VCC e5V.

Note 2: CLe50 pF, RLe2kX,T

Ae25§C and VCC e5V.

’LS163 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

VIInput Clamp Voltage VCC eMin, IIeb

18 mA b1.5 V

VOH High Level Output VCC eMin, IOH eMax DM54 2.5 3.4 V

Voltage VIL eMax, VIH eMin DM74 2.7 3.4

VOL Low Level Output VCC eMin, IOL eMax DM54 0.25 0.4

Voltage VIL eMax, VIH eMin DM74 0.35 0.5 V

IOL e4 mA, VCC eMin DM74 0.25 0.4

IIInput Current @Max VCC eMax Enable T 0.2

Input Voltage VIe7V Clock, Clear 0.2 mA

Load 0.2

Others 0.1

IIH High Level Input VCC eMax Enable T 40

Current VIe2.7V Load 40 mA

Clock, Clear 40

Others 20

IIL Low Level Input VCC eMax Enable T b0.8

Current VIe0.4V Clock, Clear b0.8 mA

Load b0.8

Others b0.4

IOS Short Circuit VCC eMax DM54 b20 b100 mA

Output Current (Note 2) DM74 b20 b100

ICCH Supply Current with VCC eMax 18 31 mA

Outputs High (Note 3)

ICCL Supply Current with VCC eMax 18 32 mA

Outputs Low (Note 4)

Note 1: All typicals are at VCC e5V, TAe25§C.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 3: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open.

Note 4: ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open.

’LS163 Switching Characteristics

at VCC e5V and TAe25§C (See Section 1 for Test Waveforms and Output Load)

From (Input) RLe2kX

Symbol Parameter To (Output) CLe15 pF CLe50 pF Units

Min Max Min Max

fMAX Maximum Clock Frequency 25 20 MHz

tPLH Propagation Delay Time Clock to 25 30 ns

Low to High Level Output Ripple Carry

tPHL Propagation Delay Time Clock to 30 38 ns

High to Low Level Output Ripple Carry

tPLH Propagation Delay Time Clock to Any Q 22 27 ns

Low to High Level Output (Load High)

tPHL Propagation Delay Time Clock to Any Q 27 38 ns

High to Low Level Output (Load High)

’LS163 Switching Characteristics

at VCC e5V and TAe25§C (See Section 1 for Test Waveforms and Output Load) (Continued)

From (Input) RLe2kX

Symbol Parameter To (Output) CLe15 pF CLe50 pF Units

Min Max Min Max

tPLH Propagation Delay Time Clock to Any Q 24 30 ns

Low to High Level Output (Load Low)

tPHL Propagation Delay Time Clock to Any Q 27 38 ns

High to Low Level Output (Load Low)

tPLH Propagation Delay Time Enable T to 14 27 ns

Low to High Level Output Ripple Carry

tPHL Propagation Delay Time Enable T to 15 27 ns

High to Low Level Output Ripple Carry

tPHL Propagation Delay Time Clear to Any Q 28 45 ns

High to Low Level Output (Note 1)

Note 1: The propagation delay clear to output is measured from the clock input transition.

Logic Diagram

LS163A

TL/F/6397–2

The LS161A is similar, however, the clear buffer is connected directly to the flip flops.

Parameter Measurement Information

Switching Time Waveforms

TL/F/6397–3

Note A: The input pulses are supplied by generators having the following characteristics: PRR s1 MHz, duty cycle s50%, ZOUT &50X,t

rs10 ns, tfs10 ns.

Vary PRR to measure fMAX.

Note B: Outputs QDand carry are tested at tna16 where tnis the bit time when all outputs are low.

Note C: VREF e1.5V.

Switching Time Waveforms

TL/F/6397–4

Note A: The input pulses are supplied by generators having the following characteristics: PRR s1 MHz, duty cycle s50%, ZOUT &50X,t

rs6 ns, tfs6 ns. Vary

PRR to measure fMAX.

Note B: Enable P and enable T setup times are measured at tna0.

Note C: VREF e1.3V.

Timing Diagram

LS161A, LS163A Synchronous Binary Counters

Typical Clear, Preset, Count and Inhibit Sequences

TL/F/6397–5

Sequence:

(1) Clear outputs to zero

(2) Preset to binary twelve

(3) Count to thirteen, fourteen, fifteen, zero, one, and two

(4) Inhibit

Physical Dimensions inches (millimeters)

Ceramic Leadless Chip Carrier Package (E)

Order Numbers 54LS161ALMQB or 54LS163ALMQB

NS Package Number E20A

16-Lead Ceramic Dual-In-Line Package (J)

Order Numbers 54LS161ADMQB, 54LS163ADMQB, DM54LS161AJ or DM54LS163AJ

NS Package Number J16A

Physical Dimensions inches (millimeters) (Continued)

16-Lead Small Outline Molded Package (M)

Order Number DM74LS161AM or DM74LS163AM

NS Package Number M16A

16-Lead Molded Dual-In-Line Package (N)

Order Numbers DM74LS161AN, DM74LS163AN

NS Package Number N16E

54LS161A/DM54LS161A/DM74LS161A, 54LS163A/DM54LS163A/DM74LS163A Synchronous

4-Bit Binary Counters

Physical Dimensions inches (millimeters) (Continued)

16-Lead Ceramic Flat Package (W)

Order Numbers 54LS161AFMQB, 54LS163AFMQB,

DM54LS161AN or DM54LS163AW

NS Package Number W16A

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