54LS161A/DM54LS161A/DM74LS161A, 54LS163A/DM54LS163A/DM74LS163A Synchronous 4-Bit Binary Counters General Description These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The LS161A and LS163A are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input. The clear function for the LS161A is asynchronous; and a low level at the clear input sets all four of the flip-flop outputs low, regardless of the levels of clock, load, or enable inputs. The clear function for the LS163A is synchronous; and a low level at the clear inputs sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all low outputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs may occur, regardless of the logic level of the clock. These counters feature a fully independent clock circuit. Changes made to control inputs (enable P or T or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable set-up and hold times. Features Y Y Y Y Y Y Y Y Y Y Synchronously programmable Internal look-ahead for fast counting Carry output for n-bit cascading Synchronous counting Load control line Diode-clamped inputs Typical propagation time, clock to Q output 14 ns Typical clock frequency 32 MHz Typical power dissipation 93 mW Alternate Military/Aerospace device (54LS161, 54LS163) is available. Contact a National Semiconductor Sales Office/Distributor for specificaitons. Connection Diagram Dual-In-Line Package Order Numbers 54LS161ADMQB, 54LS161AFMQB, 54LS161ALMQB, 54LS163ADMQB, 54LS163AFMQB, 54LS163ALMQB, DM54LS161AJ, DM54LS161AW, DM54LS163AJ, DM54LS163AW, DM74LS161AM, DM74LS161AN, DM74LS163AM or DM74LS163AN See NS Package Number E20A, J16A, M16A, N16E or W16A TL/F/6397 - 1 C1995 National Semiconductor Corporation TL/F/6397 RRD-B30M105/Printed in U. S. A. 54LS161A/DM54LS161A/DM74LS161A, 54LS163A/DM54LS163A/DM74LS163A Synchronous 4-Bit Binary Counters May 1992 Absolute Maximum Ratings (Note) Note: The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings. The ``Recommended Operating Conditions'' table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55 C to a 125 C DM54LS and 54LS DM74LS 0 C to a 70 C Storage Temperature Range b 65 C to a 150 C Recommended Operating Conditions Symbol VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 1) tW tSU TA Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 2 2 0.7 0.8 V b 0.4 b 0.4 mA 4 0 25 20 0 0 20 6 20 6 Clear 20 9 20 9 Pulse Width (Note 2) Clock 25 25 Clear 25 25 Hold Time (Note 1) V V Clock Setup Time (Note 1) Units Nom Pulse Width (Note 1) Hold Time (Note 2) tREL DM74LS161A Min Clock Frequency (Note 2) Setup Time (Note 2) tH DM54LS161A Parameter 0 Data 20 8 20 8 25 17 25 17 Load 25 15 25 15 Data 20 20 30 30 Load 30 30 mA MHz 20 MHz ns ns Enable P Enable P 8 25 ns ns Data 0 b3 0 b3 Others 0 b3 0 b3 ns Data 5 5 Others 5 5 Clear Release Time (Note 1) 20 20 ns Clear Release Time (Note 2) 25 25 ns Free Air Operating Temperature b 55 125 Note 1: CL e 15 pF, RL e 2 kX, TA e 25 C and VCC e 5.5V. Note 2: CL e 50 pF, RL e 2 kX, TA e 25 C and VCC e 5.5V. 2 0 ns 70 C 'LS161 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Min Typ (Note 1) DM54 2.5 3.4 DM74 2.7 3.4 Conditions Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min DM54 0.25 DM74 0.35 0.5 IOL e 4 mA, VCC e Min DM74 0.25 0.4 VCC e Max VI e 7V Enable T 0.2 Clock 0.2 Load 0.2 Others 0.1 Enable T 40 VOL II IIH Input Current @ Max Input Voltage High Level Input Current VCC e Max VI e 2.7V V 0.4 Clock 40 Load 40 Others IIL Low Level Input Current VCC e Max VI e 0.4V IOS Short Circuit Output Current ICCH Supply Current with Outputs High VCC e Max (Note 3) ICCL Supply Current with Outputs Low VCC e Max (Note 4) (Note 2) mA mA 20 Enable T b 0.8 Clock b 0.8 Load b 0.8 Others VCC e Max V mA b 0.4 DM54 b 20 b 100 DM74 b 20 b 100 18 31 19 32 mA mA mA Note 1: All typicals are at VCC e 5V, TA e 25 C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open. Note 4: ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open. 'LS161 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter From (Input) To (Output) RL e 2 kX CL e 15 pF Min Max 25 CL e 50 pF Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Ripple Carry 25 30 ns tPHL Propagation Delay Time High to Low Level Output Clock to Ripple Carry 30 38 ns tPLH Propagation Delay Time Low to High Level Output Clock to Any Q (Load High) 22 27 ns tPHL Propagation Delay Time High to Low Level Output Clock to Any Q (Load High) 27 38 ns 3 20 MHz 'LS161 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) (Continued) Symbol RL e 2 kX From (Input) To (Output) Parameter CL e 15 pF Min CL e 50 pF Max Min Units Max tPLH Propagation Delay Time Low to High Level Output Clock to Any Q (Load Low) 24 30 ns tPHL Propagation Delay Time High to Low Level Output Clock to Any Q (Load Low) 27 38 ns tPLH Propagation Delay Time Low to High Level Output Enable T to Ripple Carry 14 27 ns tPHL Propagation Delay Time High to Low Level Output Enable T to Ripple Carry 15 27 ns tPHL Propagation Delay Time High to Low Level Output Clear to Any Q 28 45 ns Recommended Operating Conditions Symbol DM54LS163A Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage DM74LS163A Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 2 2 V b 0.4 mA 8 mA 25 MHz 20 MHz High Level Output Current IOL Low Level Output Current 4 fCLK Clock Frequency (Note 1) tSU TA 20 0 0 Pulse Width (Note 1) Clock 20 6 20 6 Clear 20 9 20 9 Pulse Width (Note 2) Clock 25 25 Clear 25 25 Setup Time (Note 1) Data 20 8 0 20 8 Enable P 25 17 25 17 Load 25 15 25 15 Data 20 20 30 30 Load 30 Data 0 b3 0 b3 Others 0 b3 0 b3 Data 5 5 Others 5 5 Clear Release Time (Note 1) 20 20 Clear Release Time (Note 2) 25 25 Hold Time (Note 1) Free Air Operating Temperature ns ns Enable P Hold Time (Note 2) tREL 25 Clock Frequency (Note 2) Setup Time (Note 2) tH V 0.8 IOH 0 V 0.7 b 0.4 tW Units Min ns ns 30 b 55 125 Note 1: CL e 15 pF, RL e 2 kX, TA e 25 C and VCC e 5V. Note 2: CL e 50 pF, RL e 2 kX, TA e 25 C and VCC e 5V. 4 0 ns ns ns ns 70 C 'LS163 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Min Typ (Note 1) DM54 2.5 3.4 DM74 2.7 3.4 Conditions Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min DM54 0.25 0.4 DM74 0.35 0.5 IOL e 4 mA, VCC e Min DM74 0.25 0.4 VCC e Max VI e 7V Enable T VOL II IIH Input Current @ Max Input Voltage High Level Input Current VCC e Max VI e 2.7V V 0.2 Clock, Clear 0.2 Load 0.2 Others 0.1 Enable T 40 Load 40 Clock, Clear 40 Others IIL Low Level Input Current VCC e Max VI e 0.4V IOS Short Circuit Output Current ICCH Supply Current with Outputs High VCC e Max (Note 3) ICCL Supply Current with Outputs Low VCC e Max (Note 4) (Note 2) mA mA 20 Enable T b 0.8 Clock, Clear b 0.8 Load b 0.8 Others VCC e Max V mA b 0.4 DM54 b 20 b 100 DM74 b 20 b 100 18 31 18 32 mA mA mA Note 1: All typicals are at VCC e 5V, TA e 25 C. Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 3: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open. Note 4: ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open. 'LS163 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter From (Input) To (Output) RL e 2 kX CL e 15 pF Min Max 25 CL e 50 pF Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Ripple Carry 25 30 ns tPHL Propagation Delay Time High to Low Level Output Clock to Ripple Carry 30 38 ns tPLH Propagation Delay Time Low to High Level Output Clock to Any Q (Load High) 22 27 ns tPHL Propagation Delay Time High to Low Level Output Clock to Any Q (Load High) 27 38 ns 5 20 MHz 'LS163 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) (Continued) Symbol Parameter RL e 2 kX From (Input) To (Output) CL e 15 pF Min Max CL e 50 pF Min Units Max tPLH Propagation Delay Time Low to High Level Output Clock to Any Q (Load Low) 24 30 ns tPHL Propagation Delay Time High to Low Level Output Clock to Any Q (Load Low) 27 38 ns tPLH Propagation Delay Time Low to High Level Output Enable T to Ripple Carry 14 27 ns tPHL Propagation Delay Time High to Low Level Output Enable T to Ripple Carry 15 27 ns tPHL Propagation Delay Time High to Low Level Output Clear to Any Q (Note 1) 28 45 ns Note 1: The propagation delay clear to output is measured from the clock input transition. Logic Diagram LS163A TL/F/6397 - 2 The LS161A is similar, however, the clear buffer is connected directly to the flip flops. 6 Parameter Measurement Information Switching Time Waveforms TL/F/6397 - 3 Note A: The input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, duty cycle s 50%, ZOUT & 50X, tr s 10 ns, tf s 10 ns. Vary PRR to measure fMAX. Note B: Outputs QD and carry are tested at tn a 16 where tn is the bit time when all outputs are low. Note C: VREF e 1.5V. Switching Time Waveforms TL/F/6397 - 4 Note A: The input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, duty cycle s 50%, ZOUT & 50X, tr s 6 ns, tf s 6 ns. Vary PRR to measure fMAX. Note B: Enable P and enable T setup times are measured at tn a 0. Note C: VREF e 1.3V. 7 Timing Diagram LS161A, LS163A Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences TL/F/6397 - 5 Sequence: (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one, and two (4) Inhibit 8 9 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Numbers 54LS161ALMQB or 54LS163ALMQB NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (J) Order Numbers 54LS161ADMQB, 54LS163ADMQB, DM54LS161AJ or DM54LS163AJ NS Package Number J16A 10 Physical Dimensions inches (millimeters) (Continued) 16-Lead Small Outline Molded Package (M) Order Number DM74LS161AM or DM74LS163AM NS Package Number M16A 16-Lead Molded Dual-In-Line Package (N) Order Numbers DM74LS161AN, DM74LS163AN NS Package Number N16E 11 54LS161A/DM54LS161A/DM74LS161A, 54LS163A/DM54LS163A/DM74LS163A Synchronous 4-Bit Binary Counters Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Numbers 54LS161AFMQB, 54LS163AFMQB, DM54LS161AN or DM54LS163AW NS Package Number W16A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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