PH5330E - NXP SEMICONDUCTORS

PH5330E

N-channel TrenchMOS logic level FET

Rev. 02 — 19 October 2009 Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

computing, communications, consumer and industria l applications only.

1.2 Features and benefits

Higher operating power due to low

thermal resistance

Low conduction losses due to low

on-state resistance

Suitable for logic level gate drive

sources

1.3 Applications

DC-to-DC convertors

Notebook computers

Porta ble equipment

Switched-mode power supplies

1.4 Quick reference data

Table 1. Quick reference

Symbol Parameter Conditions Min Typ Max Unit

VDS drain-source voltage Tj≥25 °C; Tj≤150 °C - - 30 V

IDdrain current Tmb =25°C; V

GS =10V;

see Figure 1 and 3--80A

Ptot total power

dissipation Tmb = 25 °C; see Figure 2 - - 62.5 W

Dynamic characteristics

QGD gate-drain charge VGS =5V; I

D=20A;

VDS =10V; T

j=25°C;

see Figure 11

-6-nC

Static characteristics

RDSon drain-source

on-state resistance VGS =10V; I

D=15A;

Tj= 25 °C; see Figure 9 and 10 -4.85.7mΩ

Product data sheet Rev. 02 — 19 October 2009 2 of 12

NXP Semiconductors PH5330E

N-channel TrenchMOS logic level FET

2. Pinning information

3. Ordering information

4. Limiting values

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1S source

SOT669 (LFPAK)

2S source

3S source

4G gate

mb D mounting base; connected to

drain

1234

bb076

Table 3. Orderi ng informatio n

Type number Package

Name Description Version

PH5330E LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669

Table 4. Limiting values

In accordance with the Absolute Maxi mum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage Tj≥25 °C; Tj≤150 °C - 30 V

VGS gate-source voltage -20 20 V

IDdrain current VGS =10V; T

mb = 100 °C; see Figure 1 -50.8A

VGS =10V; T

mb =25°C; see Figure 1 and 3-80A

IDM peak drain current tp≤10 µs; pulsed; Tmb =25°C; see Figure 3 -250A

Ptot total power dissipation Tmb =25°C; see Figure 2 -62.5W

Tstg storage temperature -55 150 °C

Tjjunction temperature -55 150 °C

Source-drain diode

ISsource current Tmb =25°C - 52 A

ISM peak source current tp≤10 µs; pulsed; Tmb =25°C - 208 A

Avalanche ruggedness

EDS(AL)S non-repetitive drain-source

avalanche energy VGS =10V; T

j(init) =25°C; I

D=36.2A;

Vsup ≤30 V; unclamped; tp=0.15ms -130mJ

Product data sheet Rev. 02 — 19 October 2009 3 of 12

NXP Semiconductors PH5330E

N-channel TrenchMOS logic level FET

Fig 1. Normalized continuous drain current as a

function of mounting base temperature Fig 2. Normalized total power dissipation as a

function of mounting base temperature

Fig 3. Safe operating area; continuous and peak drain curren ts as a function of drain-source voltage

Tmb (°C)

0 20015050 100

03aa23

120

Ider

(%)

Tmb (°C)

0 20015050 100

03aa15

120

Pder

(%)

003aaa477

102

103

10−1 1 10 102

VDS (V)

(A)

100 ms

10 ms

1 ms

tp = 10 μs

100 μs

Limit RDSon = VDS / ID

Product data sheet Rev. 02 — 19 October 2009 4 of 12

NXP Semiconductors PH5330E

N-channel TrenchMOS logic level FET

5. Thermal characteristics

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-mb) thermal resistance from junction to

mounting base see Figure 4 --2K/W

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

003aaa478

10−1

10−510−410−310−210−1 1

tp (s)

Zth(j-mb)

(K/W)

single pulse

0.2

0.1

0.05

δ = 0.5

0.02

δ =

Product data sheet Rev. 02 — 19 October 2009 5 of 12

NXP Semiconductors PH5330E

N-channel TrenchMOS logic level FET

6. Characteristics

Table 6. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V(BR)DSS drain-source

breakdown voltage ID=10mA; V

GS =0V; T

j=25°C 30 - - V

VGS(th) gate-source threshold

voltage ID=1mA; V

DS = VGS; Tj= 150 °C;

see Figure 8 0.5 - - V

ID=1mA; V

DS = VGS; Tj=25°C;

see Figure 8 11.72.5V

IDSS drain leakage current VDS =30V; V

GS =0V; T

j= 25 °C - 0.06 1 µA

VDS =30V; V

GS =0V; T

j= 150 °C - - 500 µA

IGSS gate leakage current VGS =20V; V

DS =0V; T

j=25°C - 0.9 10 µA

VGS =-20V; V

DS =0V; T

j=25°C - 0.9 10 µA

RDSon drain-source on-state

resistance VGS =10V; I

D=15A; T

j=25°C;

see Figure 9 and 10 -4.85.7mΩ

VGS =4.5V; I

D=15A; T

j=25°C - 6.8 8.5 mΩ

VGS =10V; I

D=15A; T

j= 150 °C;

see Figure 9 and 10 -8.29.7mΩ

Dynamic characteristics

QG(tot) total gate charge ID=20A; V

DS =10V; V

GS =5V;

Tj=25°C; see Figure 11 -21-nC

QGS gate-source charge - 8 - nC

QGD gate-drain charge - 6 - nC

Ciss input capacitance VDS =10V; V

GS = 0 V; f = 1 MHz;

Tj=25°C; see Figure 12 - 2010 - pF

Coss output capacitance - 732 - pF

Crss reverse transfer

capacitance - 286 - pF

td(on) turn-on delay time VDS =10V; R

L=0.7Ω; VGS =10V;

RG(ext) =4.7Ω; Tj=25°C; I

D=14A -20-ns

trrise time - 22 - ns

td(off) turn-off delay time - 56 - ns

tffall time - 13 - ns

Source-drain diode

VSD source-drain voltage IS=15A; V

GS =0V; T

j=25°C;

see Figure 13 -0.81.2V

trr reverse recovery time IS=20A; dI

S/dt = -50 A/µs; VGS =0V;

VDS =25V; T

j=25°C -53-ns

Qrrecovered charge IS=20A; dI

S/dt -50 A/µs; VGS =0V;

VDS =25V; T

j=25°C -15-nC

Product data sheet Rev. 02 — 19 October 2009 6 of 12

NXP Semiconductors PH5330E

N-channel TrenchMOS logic level FET

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values Fig 6. Transfer characteristics: drain current as a

function of gate-source vo ltage; typical values

Fig 7. Sub-threshold drain current as a function of

gate-source voltage Fig 8. Gate-source threshold voltage as a function of

junction temperature

003aaa479

00.511.52

VDS (V)

(A)

3.1 V

2.6 V

2.7 V

2.9 V

3 V

10 V

VGS = 3.3 V

3.2 V

3.4 V

5 V

2.8 V

003aaa480

01234

(V)

(A)

25 °C

= 150 °C

03am28

10−5

10−4

10−3

10−2

01 23

GS (V)

(A)

min typ max

003aaa414

0120

(V)

typ

max

min

VGS(th)

Tj (°C)

−60 60 180

Product data sheet Rev. 02 — 19 October 2009 7 of 12

NXP Semiconductors PH5330E

N-channel TrenchMOS logic level FET

Fig 9. Drain-source on-state resistance as a function

of drain current; typical values Fig 10. Normalized drain-source on-state resistance

factor as a functio n o f jun ction temperature

Fig 11. Gate-source voltage as a function of gate

charge; typical values Fig 12. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

003aaa481

0 5 10 15 20

(A)

DSon

(mΩ)

3.2 V

3.3 V

5 V

3.1 V

VGS = 3 V

3.5 V

4 V

10 V

03aa27

0.5

1.5

−60 0 60 120 180

Tj (°C)

003aaa484

0 1020304050

(nC)

(V)

003aaa482

−1

1 10 10

(V)

(pF)

iss

oss

rss

Product data sheet Rev. 02 — 19 October 2009 8 of 12

NXP Semiconductors PH5330E

N-channel TrenchMOS logic level FET

Fig 13. Source current as a functio n of source-drain voltage; typical values

003aaa483

0.2 0.4 0.6 0.8 1

(V)

(A)

= 150 °C

25 °C

Product data sheet Rev. 02 — 19 October 2009 9 of 12

NXP Semiconductors PH5330E

N-channel TrenchMOS logic level FET

7. Package outline

Fig 14. Package outline SOT669 (LFPAK)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT669 MO-235 04-10-13

06-03-16

0 2.5 5 mm

scale

A2bcA e

UNIT

DIMENSIONS (mm are the original dimensions)

mm 1.10

0.95

0.15

0.00

1.20

1.01

0.50

0.35

4.41

3.62

2.2

2.0

0.9

0.7

0.25

0.19

0.30

0.24

4.10

3.80

6.2

5.8

1.3

0.8

0.85

0.40

1.3

0.8

8°

0°

D(1)

5.0

4.8

E(1)

3.3

3.1

E1(1)

D1(1)

max

0.25 4.20 1.27 0.25 0.1

1234

mounting

base

lastic single-ended surface-mounted package (LFPAK); 4 leads SOT66

1/2 e

(A )

detail X

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

Product data sheet Rev. 02 — 19 October 2009 10 of 12

NXP Semiconductors PH5330E

N-channel TrenchMOS logic level FET

8. Revision history

Table 7. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PH5330E_2 20091019 Product data sheet - PH5330E-01

Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

PH5330E-01

(9397 750 12334) 200 40109 Product data - -

Product data sheet Rev. 02 — 19 October 2009 11 of 12

NXP Semiconductors PH5330E

N-channel TrenchMOS logic level FET

9. Legal information

9.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com.

9.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict wit h the short data sheet, th e

full data sheet shall pre va il.

9.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does no t give any representa tions or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraf t,

space or life support equipment, nor in applicat ions where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environment al

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Rati ngs System of I EC 60134) may cause perman ent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other co nditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warr anty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the it em(s) described herein may

be subject to export control regulations. Export might require a prior

authorization from national authorities.

9.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respective ow ners.

TrenchMOS — is a trademark of NXP B.V.

10. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Document status [1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

NXP Semiconductors PH5330E

N-channel TrenchMOS logic level FET

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 19 October 2009

Document identifier : PH5330E_2

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

11. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 General description . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .11

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .11

10 Contact information. . . . . . . . . . . . . . . . . . . . . .11