LM98722
LM98722 3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output,
Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock
Generation
Literature Number: SNAS487
LM98722
September 24, 2009
3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/
CMOS Output, Integrated CCD/CIS Sensor Timing
Generator and Spread Spectrum Clock Generation
General Description
The LM98722 is a fully integrated, high performance 16-Bit,
45 MSPS signal processing solution for digital color copiers,
scanners, and other image processing applications. High-
speed signal throughput is achieved with an innovative archi-
tecture utilizing Correlated Double Sampling (CDS), typically
employed with CCD arrays, or Sample and Hold (S/H) inputs
(for higher speed CCD or CMOS image sensors). The signal
paths utilize 8 bit Programmable Gain Amplifiers (PGA), a
+/-9-Bit offset correction DAC and independently controlled
Digital Black Level correction loops for each input. The PGA
and offset DAC are programmed independently allowing
unique values of gain and offset for each of the three analog
inputs. The signals are then routed to a 45MHz high perfor-
mance analog-to-digital converter (ADC). The fully differential
processing channel shows exceptional noise immunity, hav-
ing a very low noise floor of -74dB. The 16-bit ADC has
excellent dynamic performance making the LM98722 trans-
parent in the image reproduction chain.
A very flexible integrated Spread Spectrum Clock Generation
(SSCG) modulator is included to assist with EM compliance
and reduce system costs.
Applications
Multi-Function Peripherals
High-speed Currency/Check Scanners
Flatbed or Handheld Color Scanners
High-speed Document Scanners
Features
LVDS/CMOS Outputs
LVDS/CMOS/Crystal Clock Source with PLL Multiplication
Integrated Flexible Spread Spectrum Clock Generation
CDS or S/H Processing for CCD or CIS sensors
Independent Gain/Offset Correction for Each Channel
Automatic per-Channel Gain and Offset Calibration
Programmable Input Clamp Voltage
Flexible CCD/CIS Sensor Timing Generator
Key Specifications
Maximum Input Level 1.2 or 2.4 Volt Modes
(both with + or - polarity option)
ADC Resolution 16-Bit
ADC Sampling Rate 45 MSPS
INL +18/-25 LSB (typ)
Channel Sampling Rate 22.5/22.5/15 MSPS
PGA Gain Steps 256 Steps
PGA Gain Range 0.64 to 8.3x
Analog DAC Resolution +/-9 Bits
Analog DAC Range +/-307mV or +/-614mV
Digital DAC Resolution +/-6 Bits
Digital DAC Range -2048 LSB to + 2016 LSB
SNR -74dB (@0dB PGA Gain)
Power Dissipation 630mW (LVDS)
Operating Temp 0 to 70°C
Supply Voltage 3.3V Nominal (3.0V to 3.6V range)
System Block Diagram
30099570
© 2009 National Semiconductor Corporation 300995 www.national.com
LM98722 3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output Integrated
Sensor Timing Generator and Spread Spectrum Clock Generation
LM98722 Overall Chip Block Diagram
30099501
FIGURE 1. Chip Block Diagram
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LM98722
LM98722 Pin Out Diagram
30099502
FIGURE 2. LM98722 Pin Out Diagram
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LM98722
Typical Application Diagram
30099573
FIGURE 3. Typical Application Diagram
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LM98722
Pin Descriptions
Pin Name I/O Typ Res Description
1 PHIC2 O D PU Configurable high speed sensor timing output.
2 PHIC1 O D PD Configurable high speed sensor timing output.
3 SH1 O D PU Configurable low speed sensor timing output.
4 CE I D Chip Serial Interface Address Setting Input
CE Level Address
VD01
Float 10
DGND 00
5 CAL I D PD Initiate calibration sequence. Leave unconnected or tie to DGND if unused.
6 RESET I D PU Active-low master reset. NC when function not being used.
7 SH_R I D PD External request for an SH interval.
8 SDI I D PD Serial Interface Data Input.
9 SDO O D Serial Interface Data Output.
10 SCLK I D PD Serial Interface shift register clock.
11 SEN I D PU Active-low chip enable for the Serial Interface.
12 VA P Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
13 AGND P Analog ground return.
14 VA P Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
15 VREFB O A Bottom of ADC reference. Bypass with a 0.1μF capacitor to ground.
16 VREFT O A Top of ADC reference. Bypass with a 0.1μF capacitor to ground.
17 VA P Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
18 AGND P Analog ground return.
19 VCLP IO A Input Clamp Voltage. Normally bypassed with a 0.1μF , and a 4.7μF capacitor to AGND.
An external reference voltage may be applied to this pin.
20 VA P Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
21 IBIAS O A Bias setting pin. Connect a 9.0 kOhm 1% resistor to AGND.
22 AGND P Analog ground return.
23 OSRI A Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.
24 AGND P Analog ground return.
25 OSGI A Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.
26 AGND P Analog ground return.
27 OSBI A Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.
28 CPOFILT2 A Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor to
CPOFILT1.
29 DGND P Digital ground return.
30 CPOFILT1 A Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor to
CPOFILT2.
31 DVB O D Digital Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to DGND.
32 INCLK+ I D Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is
selected when pin 29 is held at DGND, otherwise clock is configured for LVDS operation.
33 INCLK- I D Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.
34 DOUT7/ O D Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS Mode.
TXCLK+
35 DOUT6/ O D Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS Mode.
TXCLK-
36 DOUT5/ O D Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS Mode.
TXOUT2+
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LM98722
Pin Name I/O Typ Res Description
37 DOUT4/ O D Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode.
TXOUT2-
38 DOUT3/ O D Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS Mode.
TXOUT1+
39 DOUT2/ O D Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode.
TXOUT1-
40 DOUT1/ O D Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS Mode.
TXOUT0+
41 DOUT0/ O D Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode.
TXOUT0-
42 DGND O D PD Configurable sensor control output.
43 VD P Power supply for the digital circuits. Bypass this supply pin with 0.1μF capacitor. A single
4.7μF capacitor should be used between the supply and the VD, VR and VC pins.
44 VC P Power supply for the sensor control outputs. Bypass this supply pin with 0.1μF capacitor.
45 CLKOUT/SH2 O D Output clock for registering output data when using CMOS outputs, or a configurable
low speed sensor timing output.
46 SH3 O D Configurable low speed sensor timing output.
47 RS O D Configurable high speed sensor timing output.
48 CP O D Configurable high speed sensor timing output.
49 PHIA1 O D Configurable high speed sensor timing output.
50 PHIA2 O D Configurable high speed sensor timing output.
51 DGND P Digital ground return.
52 VC P Power supply for the sensor control outputs.
Bypass this supply pin with 0.1μF capacitor.
53 PHIB1 O D Configurable high speed sensor timing output.
54 PHIB2 O D Configurable high speed sensor timing output.
55 SH4 O D Configurable low speed sensor timing output.
56 SH5 O D Configurable low speed sensor timing output.
(I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down with an internal resistor.).
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LM98722
Absolute Maximum Ratings (Note 1, Note
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VA,VR,VD,VC) 4.2V
Voltage on Any Input Pin
(Not to exceed 4.2V)
−0.3V to
(VA + 0.3V)
Voltage on Any Output Pin
(execpt DVB and not to exceed 4.2V)
−0.3V to
(VA + 0.3V)
DVB Output Pin Voltage 2.0V
Input Current at any pin other than
Supply Pins (Note 3)
±25 mA
Package Input Current (except Supply
Pins) (Note 3)
±50 mA
Maximum Junction Temperature (TA) 150°C
Thermal Resistance (θJA)<66°C/W
Package Dissipation at TA = 25°C
(Note 4)
>1.89W
ESD Rating (Note 5)
Human Body Model 2500V
Machine Model 250V
Storage Temperature −65°C to +150°C
Soldering process must comply with National
Semiconductor’s Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.
(Note 6)
Operating Ratings (Note 1, Note 2)
Operating Temperature Range 0°C TA +70°C
All Supply Voltage +3.0V to +3.6V
Electrical Characteristics
The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface
limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Symbol Parameter Conditions Min
(Note 9)
Typ
(Note 8)
Max
(Note 9)Units
CMOS Digital Input DC Specifications (RESETb, SH_R, SCLK, SENb)
VIH Logical “1” Input Voltage 2.0 V
VIL Logical “0” Input Voltage 0.8 V
VIHYST Logic Input Hysteresis 0.6
IIH Logical “1” Input Current VIH = VD
RESET,SEN 100 nA
SH_R, SCLK, SDI, CAL 65 μA
CE 30 nA
IIL Logical “0” Input Current VIL = DGND
RESETSEN -65 μA
SH_R, SCLK, SDI, CAL -100 nA
CE -30 μA
CMOS Digital Output DC Specifications (SH1 to SH5, RS, CP, PHIA, PHIB, PHIC)
VOH Logical “1” Output Voltage IOUT = -0.5mA 3.0 V
VOL Logical “0” Output Voltage IOUT = 1.6mA 0.21 V
IOS Output Short Circuit Current VOUT = DGND 18 mA
VOUT= VD -25
IOZ CMOS Output TRI-STATE Current VOUT = DGND 20 nA
VOUT = VD -25
CMOS Digital Output DC Specifications (CMOS Data Outputs)
VOH Logical “1” Output Voltage IOUT = -0.5mA 2.3 V
VOL Logical “0” Output Voltage IOUT = 1.6mA 0.12 V
IOS Output Short Circuit Current VOUT = DGND 12 mA
VOUT= VD -14
IOZ CMOS Output TRI-STATE Current VOUT = DGND 20 nA
VOUT = VD -25
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LM98722
Symbol Parameter Conditions Min
(Note 9)
Typ
(Note 8)
Max
(Note 9)Units
LVDS/CMOS Clock Receiver DC Specifications (INCLK+ and INCLK- Pins)
VIHL Differential LVDS Clock RL = 100Ω 200 mV
High Threshold Voltage VCM (LVDS Input Common Mode
Voltage)= 1.25V
VILL Differential LVDS Clock -200 mV
Low Threshold Voltage
VIHC CMOS Clock INCLK- = DGND 2.0 V
High Threshold Voltage
VILC CMOS Clock 0.8 V
Low Threshold Voltage
IIHL CMOS Clock 230 260 μA
Input High Current
IILC CMOS Clock -135 -120 μA
Input Low Current
LVDS Output DC Specifications
VOD Differential Output Voltage RL = 100Ω 280 390 490 mV
VOS LVDS Output Offset Voltage 1.08 1.20 1.33 V
IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω 8.5 mA
Power Supply Specifications
IA VA Analog Supply Current LVDS Output Data Format 139 162 mA
LVDS Output Data Format
(Powerdown)
3.1 4.5 mA
CMOS Output Data Format
(40 MHz)
137 161 mA
ID VD Digital Output Driver Supply
Current
LVDS Output Data Format 50 65 mA
LVDS Output Data Format
(Powerdown)
5.5 8 mA
CMOS Output Data Format
(ATE Loading of CMOS Outputs
> 50 pF) (40 MHz)
48 62 mA
IC VC CCD Timing Generator Output
Driver Supply Current
Typical sensor outputs: 1 4 mA
SH1-SH5, PHIA, PHIB, PHIC,
RS, CP
(ATE Loading of CMOS
Outputs > 50pF)
PWR Average Power Dissipation LVDS Output Data Format 630 736 mW
LVDS Output Data Format
(Powerdown)
28 32 mW
CMOS Output Data Format
(ATE Loading of CMOS Outputs
> 50pF) (40 MHz)
600 740 mW
Input Sampling Circuit Specifications
VIN Input Voltage Level CDS Gain=1x, PGA Gain=1x 2.3 Vp-p
CDS Gain=2x, PGA Gain= 1x 1.22
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LM98722
Symbol Parameter Conditions Min
(Note 9)
Typ
(Note 8)
Max
(Note 9)Units
IIN_SH Sample and Hold Mode Source Followers Off 19 25 μA
Input Leakage Current CDS Gain = 1x (-103) (-95)
OSX = VA (OSX = AGND)
Source Followers Off 33 50 μA
CDS Gain = 2x (-152) (-141)
OSX = VA (OSX = AGND)
Source Followers On 20 250 nA
CDS Gain = 2x (-250) (-50)
OSX = VA (OSX = AGND)
CSH Sample/Hold Mode CDS Gain = 1x 2.5 pF
Equivalent Input Capacitance
CDS Gain = 2x 4 pF
IIN_CDS CDS Mode Source Followers Off 10 250 nA
Input Leakage Current OSX = VA (OSX = AGND) (-250) (-50)
RCLPIN CLPIN Switch Resistance 16 55
(OSX to VCLP Node)
VCLP Reference Circuit Specifications
VVCLP
VCLP Voltage 000 VCLP Voltage Setting = 000 0.85VA V
VCLP Voltage 001 VCLP Voltage Setting = 001 0.9VA V
VCLP Voltage 010 VCLP Voltage Setting = 010 0.95VA V
VCLP Voltage 011 VCLP Voltage Setting = 011 0.6VA V
VCLP Voltage 100 VCLP Voltage Setting = 100 0.55VA V
VCLP Voltage 101 VCLP Voltage Setting = 101 0.4VA V
VCLP Voltage 110 VCLP Voltage Setting = 110 0.35VA V
VCLP Voltage 111 VCLP Voltage Setting = 111 0.15VA V
ISC VCLP DAC Short Circuit Output
Current
0001 xxxxb VCLP Config.
Register =
30 mA
Black Level Offset DAC Specifications
Resolution 10 Bits
Monotonicity Guaranteed by characterization
Offset Adjustment Range CDS Gain = 1x
mVReferred to AFE Input Minimum DAC Code = 0x000 -614
Maximum DAC Code = 0x3FF 614
CDS Gain = 2x
mV Minimum DAC Code = 0x000 -307
Maximum DAC Code = 0x3FF 307
Offset Adjustment Range Minimum DAC Code = 0x000 -17500 -16130 LSB
Referred to AFE Output Maximum DAC Code = 0x3FF +16130 +17500
DAC LSB Step Size CDS Gain = 1x 1.2 mV
Referred to AFE Output (32) (LSB)
DNL Differential Non-Linearity -0.85 +0.74/
-0.37
+2.4 LSB
INL Integral Non-Linearity -2.5 +0.72/
-0.56
+2.5 LSB
PGA Specifications
Gain Resolution 8 Bits
Monotonicity Guaranteed by characterization
Maximum Gain CDS Gain = 1x 7.7 8.3 8.8 V/V
CDS Gain = 1x 17.7 18.4 18.9 dB
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LM98722
Symbol Parameter Conditions Min
(Note 9)
Typ
(Note 8)
Max
(Note 9)Units
Minimum Gain CDS Gain = 1x 0.58 0.64 0.70 V/V
CDS Gain = 1x -4.7 -4.2 -3.5 dB
PGA Function Gain (V/V) = (180/(277-PGA Code))
Gain (dB) = 20LOG10(180/(277-PGA Code))
Channel Matching Minimum PGA Gain 3 %
Maximum PGA Gain 12.7
ADC Specifications
VREFT Top of Reference 2.07 V
VREFB Bottom of Reference 0.89 V
VREFT -
VREFB
Differential Reference Voltage 1.06 1.18 1.30 V
Overrange Output Code 65535
Underrange Output Code 0
Digital Offset “DAC” Specifications
Resolution 7 Bits
Digital Offset DAC LSB Step Size Referred to AFE Output 32 LSB
Offset Adjustment Range Min DAC Code =7b0000000 -2048
LSBReferred to AFE Output Mid DAC Code =7b1000000 0
Max DAC Code = 7b1111111 +2016
Full Channel Performance Specifications
DNL Differential Non-Linearity (Note 10) -0.999 +0.8/-0.7 2.5 LSB
INL Integral Non-Linearity (Note 10) -75 +18/-25 75 LSB
SNR Total Output Noise
Minimum PGA Gain
(Note 10)
-76 dB
10 26 LSB RMS
Maximum PGA Gain
(Note 10)
-56 dB
96 LSB RMS
Channel to Channel Crosstalk Mode 3 26 LSB
Mode 2 17
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LM98722
AC Timing Specifications
The following specifications apply for VA = VD = VC = 3.3V, CL = 10pF, and fINCLK = 15MHz unless otherwise specified. Boldface
limits apply for TA = TMIN to TMAX; all other limits TA = 25°C.
Symbol Parameter Conditions
Min
(Note
9)
Typ
(Note 8)
Max
(Note 9)Units
Input Clock Timing Specifications
fINCLK Input Clock Frequency
INCLK = PIXCLK 0.66
15 (Mode 3)
MHz(Pixel Rate Clock) 1 22.5 (Mode 2)
1 22.5 (Mode 1)
INCLK = ADCCLK
2
45 (Mode 3)
MHz(ADC Rate Clock) 45 (Mode 2)
22.5 (Mode 1)
Tdc Input Clock Duty Cycle 40/60 50/50 60/40 %
Full Channel Latency Specifications
tLAT3
3 Channel Mode Pipeline Delay PIXPHASE0 24
TADC
PIXPHASE1 23 1/2
PIXPHASE2 23
PIXPHASE3 22 1/2
tLAT2
2 Channel Mode Pipeline Delay PIXPHASE0 21
TADC
PIXPHASE1 20 1/2
PIXPHASE2 20
PIXPHASE3 19 1/2
tLAT1
1 Channel Mode Pipeline Delay PIXPHASE0 19
TADC
PIXPHASE1 18 1/2
PIXPHASE2 18
PIXPHASE3 17 1/2
SH_R Timing Specifications
tSHR_S SH_R Setup Time 2 ns
tSHR_H SH_R Hold Time 2 ns
LVDS Output Timing Specifications
TXpp0 TXCLK to Pulse Position 0 LVDS Output -0.46 0 0.46 ns
TXpp1 TXCLK to Pulse Position 1 Specifications not 2.71 3.17 3.63 ns
TXpp2 TXCLK to Pulse Position 2 tested in production. 5.89 6.35 6.81 ns
TXpp3 TXCLK to Pulse Position 3 Min/Max guaranteed 9.06 9.52 9.98 ns
TXpp4 TXCLK to Pulse Position 4 by design, 12.24 12.70 13.16 ns
TXpp5 TXCLK to Pulse Position 5 characterization and statistical 15.41 15.87 16.33 ns
TXpp6 TXCLK to Pulse Position 6 analysis. 18.59 19.05 19.51 ns
CMOS Output Timing Specifications
tCRDO
CLKOUT Rising Edge to CMOS
Output Data Transition
fINCLK = 40MHz
2 6 9 ns
INCLK = ADCCLK
(ADC Rate Clock)
Serial Interface Timing Specifications
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LM98722
Symbol Parameter Conditions
Min
(Note
9)
Typ
(Note 8)
Max
(Note 9)Units
fSCLK Input Clock Frequency
fSCLK <= fINCLK
15/22.5/22.5 MHz
INCLK = PIXCLK
(Pixel Rate Clock)
Mode 3/2/1
fSCLK <= fINCLK
45/45/22.5 MHz
INCLK = ADCCLK
(ADC Rate Clock)
Mode 3/2/1
SCLK Duty Cycle 50/50 ns
tIH Input Hold Time 1.5 ns
tIS Input Setup Time 2.5 ns
tSENSC SCLK Start Time After SEN Low 1.5 ns
tSCSEN
SEN High after last SCLK Rising
Edge 2.5 ns
tSENW SEN Pulse Width
INCLK present 6
TINCLK
INCLK stopped
(Note 11, Note 12)
50 ns
tOD Output Delay Time 11 14 ns
tHZ Data Output to High Z 0.5 TSCLK
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA.
The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25
mA to two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJMAX – TA)/θJA. The values for maximum power dissipation listed above will be reached only when the
device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is
limited per note 3. However, input errors will be generated If the input goes above VA and below AGND.
30099571
Note 8: Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not
guaranteed.
Note 9: Test limis are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 10: This parameter guaranteed by design and characterization.
Note 11: If the input INCLK is divided down to a lower internal clock rate via the PLL, the parameter tSENW will be increased by the same factor.
Note 12: When the Spread Spectrum Clock Generation feature is enabled, tSENW should be increased by 1.
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LM98722
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead TSSOP
NS Package Number MTD56
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LM98722
Notes
LM98722 3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output Integrated
Sensor Timing Generator and Spread Spectrum Clock Generation
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