Document Number: 320767-025US

Intel® Core™ i7-900 Mobile

Processor Extreme Edition Series,

Intel® Core™ i7-800 and i7-700

Mobile Processor Series

Specification Update

December 2013

Intel® Core™ i7-900 Mobile Processor Extreme Edition Series,

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

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Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

Document Number: 320767-025US 3

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

Revision History

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

update and are no longer published in other documents.

This document may also contain information that was not previously published.

Core™ i7-800 and i7-700 Mobile Processor Series Datasheet - Volume 2 320766

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume

1: Basic Architecture

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume

2A: Instruction Set Reference Manual A-M

2B: Instruction Set Reference Manual N-Z

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume

3A: System Programming Guide

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

Summary Tables of Changes

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

16 Document Number: 320767-025US

SLBMP i7-840QM B-1 106E5h 1.86 / 1333

SLBQG i7-740QM B-1 106E5h 1.73 / 1333

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

WP or WT memory type within a single REP MOVS or REP STOS instruction that will

execute with fast strings enabled.

AAP3. Code Segment Limit/Canonical Faults on RSM May Be Serviced before

Higher Priority Interrupts/Exceptions and May Push the Wrong

Address onto the Stack

code execution, a #GP (Gener al Protection Exception) fault is generated after all higher

priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume

from System Management Mode) returns to execution flow that results in a Code

Interrupts and Exceptions. Intel has not observed this erratum on any commercially-

available software.

Workaround:None identified.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

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AAP4. Performance Monitor SSE Retired Instructions May Return Incorrect

retired SSE instructions. Due to this err atum, the processor may also count other types

of instructions resulting in higher than expected values.

instruction will have executed before the exception handler is entered.

• If an instruction that performs a memory load causes a code segment limit

violation.

• If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX)

instruction that performs a memory load has a floating-point exception pending.

• If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a

memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point Top-

of-Stack (FP TOS) not equal to 0, or a DNA exception pending.

memory there is no impact from the load being prematurely executed, or from the

workaround this behavior by using simple integer-based load instructions when

segment limit violation cannot occur as a part of reading from side-effect memory.

AAP6. MOV To/From Debug Registers Causes Debug Exception

general-protection exception (#GP) should be generated. However, in the case when

the general detect enable flag (GD) bit is set, the observed behavior is that a debug

exception (#DB) is generated instead.

execute a MOV on debug registers in V86 mode, a debug exception will be generated

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

Leads to Partial Memory Update

restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit

while the processor is operating in 16-bit mode or if a memory address exceeds the

4GB limit while the processor is operating in 32-bit mode.

but the memory state may be only partially saved or restored.

Workaround:Software should avoid memory accesses that wrap around the respective 16-bit and

32-bit mode memory limits.

AAP8. Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM

AAP9. Single Step Interrupts with Floating Point Exception Pending May Be

Mishandled

single-step execution, processing of the single-step debug exception (#DB) may be

Workaround:None identified.

result of processing the fault).

Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for information

on the usage of the ENTER instructions. This erratum is not expected to occur in Ring 3.

Faults are usually processed in Ring 0 and stack switch occurs when transferring to

Ring 0. Intel has not observed this erratum on any commercially-available software.

Workaround:None identified.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

20 Document Number: 320767-025US

AAP11. IRET under Certain Conditions May Cause an Unexpected Alignment

Check Exception

instruction even though alignment checks were disabled at the start of the IRET. This

can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs

from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the

stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e

AAP12. General Protection Fault (#GP) for Instructions Greater Than 15 Bytes

May Be Preempted

#GP is signaled when the instruction is decoded. Under some circumstances, the #GP

fault may be preempted by another lower priority fault (e.g., Page Fault (#PF)).

However, if the preempting lower priority faults are resolved by the operating system

and the instruction retried, a #GP fault will occur.

placed before the instruction.

Workaround:None identified.

Workaround:Software should ensure that memory accesses in 32-bit mode do not occur above the

4-G limit (0ffffffffh).

the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF)

in 64-bit mode, the LBR return registers will save a wrong return address with Bits 63

to 48 incorrectly sign extended to all 1's. Subsequent BTS and BTM operations which

report the LBR will also be incorrect.

Workaround:None identified.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

AAP15. MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in

xAPIC's address space, the processor will hang.

must be uncached. The MONITOR instruction only functions correctly if the specified

Intel has not observed this erratum with any commercially-available software.

Workaround:Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.

Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection

Enable, Bit 0) and the first FAR JMP, the subsequent RSM (Resume from System

Management Mode) may cause the lower two bits of CS segment register to be

unless software explicitly examines the CS segment register between enabling

Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section

commercially-available software.

AAP17. Performance Monitoring Events for Read Miss to Level 3 Cache Fill

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

22 Document Number: 320767-025US

As Armed

immediately trigger the monitoring hardware. Consequently, a VM exit on a later

MWAIT may incorrectly report the monitoring hardware as armed, when it should be

reported as unarmed due to the write occurring prior to the MWAIT.

MONITOR and the MWAIT, the MWAIT instruction may start executing before the

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

AAP22. Improper Parity Error Signaled in the IQ Following Reset When a Code

Breakpoint Is Set on a #GP Instruction

instruction longer than 15 bytes (which causes a #GP) and a code breakpoint is

enabled on that instruction, an IQ (Instruction Queue) parity error may be incorrectly

logged resulting in an MCE (Machine Check Exception).

AAP24. IA32_MPERF Counter Stops Counting during On-Demand TM1

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

24 Document Number: 320767-025US

AAP25. The Memory Controller tTHROT_OPREF Timings May Be Violated

during Self Refresh Entry

permitted by tTHROT_OPREF (bits 29:19 in MC_CHANNEL_{0,1}_REFRESH_TIMING

CSR).

specification, this erratum should never be seen during normal operation.

Workaround:Software should not disable Thermal Monitor during processor operation.

AAP29. OVER Bit for IA32_MCi_STATUS Register May Get Set on Specific

lnternal Error

IA32_MCi_ST ATUS.MCACOD=0x0405, the IA32_MCi_ ST ATUS.OVER (overflow) Bit [62]

may be erroneously set.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

AAP30. Writing the Local Vector Table (LVT) When an Interrupt Is Pending

May Cause an Unexpected Interrupt

on the new interrupt vector even if the mask bit is set.

written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service

Workaround:Any vector progr ammed into an LVT entry must hav e an ISR associated with it, even if

to 0x0000).

that uses an index register (this condition does not apply to MASKMOVQ).

to a 0x0000 value when it should not have been modified.

Workaround:None identified.

AAP32. xAPIC Timer May Decrement Too Quickly following an Automatic

xAPIC timer may be shortened by up to one xAPIC timer tick.

Workaround:None identified.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

32 Document Number: 320767-025US

AAP56. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits

after a Translation Change

linear address from writable to non-writable without software performing an

appropriate TLB invalidation. When a subsequent access to that address by a specific

MC_CHANNEL_{0,1}_MC_DIMM_INIT_CMD.DO_ZQCL Commands Are

AAP58. Package C3/C6 Transitions When Memory 2x Refresh Is Enabled May

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

AAP59. Back to Back Uncorrected Machine Check Errors May Overwrite

in the IA32_MC3_STATUS MSR (40CH), the IA32_MC3_STATUS.MSCOD (bits [31:16])

field may reflect the status of the most recent error and not the first error. The rest of

the IA32_MC3_STATUS MSR contains the information from the first error.

IA32_MC3_STATUS.OVER (Bit [62]) is set.

Workaround:None identified.

system hang.

AAP62. PSI# Signal May Incorrectly Be Left Asserted

Workaround:It is possible for the BIOS to contain a workaround for this erratum.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

34 Document Number: 320767-025US

AAP63. Performance Monitor Events DCACHE_CACHE_LD and

DCACHE_CACHE_ST May Overcount

DCACHE_CACHE_ST (Event 41H) count cacheable loads and stores that hit the L1

counter will incorrectly count speculative loads and stores that were aborted prior to

Workaround:None identified.

AAP64. Rapid Core C3/C6 Transitions May Cause Unpredictable System

check error (IA32_MCi_STATUS.MCACOD = 0x0106), system hang or unpredictable

system behavior.

of load or store instructions retired. However, due to this erratum, they may

undercount.

a count lower than the actual number of events.

Workaround:None identified.

AAP66. A Page Fault May Not Be Generated When the PS Bit Is Set to "1" in a

PML4E or PDPTE

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

AAP67. CPURESET Bit Does Not Get Cleared

Workaround:The CPURESET bit must be cleared by software prior to setting it.

AAP68. PHOLD Disable in MISCCTRLSTS Register Does Not Work

Offset 188H) does not function as described. Setting this bit will not cause the

Assert_PHOLD message from the PCH (Platform Controller Hub).

states should have been ignored. The PCIe port does not change power state from D0

or D3hot when the Power State bits are written to D1 or D2, so there is no functional

impact to the PCIe port. However, the Power State field is incorrectly modified.

Workaround:None identified.

Workaround:It is possible for the BIOS to contain a workaround for this erratum.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

36 Document Number: 320767-025US

AAP72. Uncacheable Access to a Monitored Address Range May Prevent

Future Triggering of the Monitor Hardware

instruction could be written without triggering the monitor hardware. A read from the

monitored address range which is issued as uncacheable (for example having the

AAP73. BIST Results May Be Additionally Reported after a GETSEC[WAKEUP]

or INIT-SIPI Sequence

from the Wait-For-SIPI state. Due to this erratum, BIST results may be additionally

reported after INIT-SIPI sequences and when waking up RLP's from the SENTER sleep

state using the GETSEC[WAKEUP] command.

value is expected. RLP's waking up for the SENTER sleep state using the

GETSEC[WAKEUP] command may show a different value in EAX upon wakeup than

before going into the SENTER sleep state.

Workaround:If necessary software may save the value in EAX prior to launching into the secure

environment and restore upon wakeup and/or clear EAX after the INIT-SIPI sequence.

AAP74. Pending x87 FPU Exceptions (#MF) May Be Signaled Earlier Than

this erratum, if an instruction that triggers #MF is executed while Enhanced Intel

SpeedStep Technology transitions, Intel® Turbo Boost Technology transitions, or

Thermal Monitor events occur, the pending #MF may be signaled before pending

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

AAP75. VM Exits Due to "NMI-Window Exiting" May Be Delayed by One

events by STI. If VM entry is made with no virtual-NMI blocking but with blocking of

events by either MOV SS or STI, such a VM exit should occur after execution of one

field will not match the actual payload size.

Workaround:A BIOS code change has been identified and may be implemented as a workaround for

this erratum.

AAP77. PCIe* Operation in x16 Mode with Inbound Posted Writes May Be

operation inbound writes may store incorrect data.

Chipset and Intel 3400 Series Chipset may cause PCI devices to subsequently become

available software and has only observed this in a synthetic test environment.

Workaround:None identified.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

38 Document Number: 320767-025US

AAP79. VM Exits Due to EPT Violations Do Not Record Information about Pre-

IRET NMI Blocking

12 of the exit qualification if the EPT violation was a result of an execution of the IRET

instruction that commenced with non-maskable interrupts (NMIs) blocked. Due to this

erratum, such VM exits will instead clear this bit.

12 of the exit qualification may deliver NMIs to guest software prematurely.

Workaround:It is possible for the BIOS to contain a workaround for this erratum.

Remap-Cache Invalidation Command

remapping hardware receives two identical back-to-back interrupt requests, then the

attributes of the remapped interrupt returned may be corrupted. This interrupt

sequence may also hang the system if the software executes a subsequent interrupt-

AAP81. S1 Entry May Cause Cores to Exit C3 or C6 C-State

power than expected and software may observe a different C-state on S1 exit than on

Workaround:It possible for the BIOS to contain a workaround for this erratum.

AAP82. Multiple Performance Monitor Interrupts Are Possible on Overflow of

Workaround:None identified.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

AAP83. LBRs May Not Be Initialized during Power-On Reset of the Processor

Workaround:Ensure that the processor has completed its power-on reset cycle prior to initiating a

second reset.

logical processor.

Workaround:Software should stop the APIC timer (by writing 0 to the Initial Count Register) before

allowing the core to enter the C6 state.

Transition, T-states, C1E, or Adaptive Thermal Throttling

Message) or BTS (Branch Trace Store) may be incorrect for the first branch after an

Enhanced Intel SpeedStep Technology transition, T-states, C1E (C1 Enhanced), or

Adaptive Thermal Throttling.

AAP86. VMX-Preemption Timer Does Not Count Down at the Rate Specified

[4:0] (0x485h) and has a value of 5 on the affected processors.) Due to this erratum,

the VMX-preemption timer may instead count down at a different rate and may do so

only intermittently.

by software.

Workaround:None identified.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

40 Document Number: 320767-025US

AAP87. Multiple Performance Monitor Interrupts Are Possible on Overflow of

Fixed Counter 0

overflow of the IA32_FIXED_CTR0 MSR (309H). A single PMI should be observed on

occurs.

• IA32_FIXED_CTR0 local and global controls are enabled

• IA32_FIXED_CTR0 is set to count events only on its own thread

(IA32_FIXED_CTR_CTRL MSR (38DH) Bit [2] = ‘0)

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

AAP90. VM Exits Due to LIDT/LGDT/SIDT/SGDT Do Not Report Correct

Operand Size

operand, Bit 11 of the VM-exit instruction information field should be set to 1. Due to

this erratum, this bit is instead cleared to 0 (indicating a 16-bit operand).

size.

Regulator) signal may be incorrectly asserted.

Workaround:None identified.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

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48 Document Number: 320767-025US

AAP117. NTB/RP Link Will Send Extra TS2 Ordered Set During Link Training

CONFIGURATION.IDLE before this ordered set is sent and will ignore it.

AAP118. PCIe* Ports May Not Enter Slave Loopback Mode From the

Configuration LTSSM State

CONFIG.LINK_WIDTH_START state, it may not enter slave loopback mode when

requested to do so by the link partner. If the request is missed the link will continue to

RECOVERY LTSSM states.

long enough so that the same packet is NAKed four times, the link will retrain and a

correctable error may be signaled by the PCIe end point. Overall performance of the

link is not impacted.

Workaround:A BIOS code change has been identified and may be implemented as a workaround for

this erratum.

is a small chance that a lane could be dropped during the deskew phase of tr aining. In

the case of a lane being dropped this will be detected and a retry will be done until the

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

AAP121. PerfMon Overflow Status Can Not be Cleared After Certain Conditions

Have Occurred

through MSR IA32_PERF_GLOBAL_CTRL (0x38F) or through the per-counter event-

select (e.g. MSR 0x186) and the counter reached its overflow state very close to that

time, then due to this erratum the overflow status indication in MSR

IA32_PERF_GLOBAL_STAT (0x38E) may be left set with no way for software to clear it.

Workaround:Software may avoid this erratum by clearing the PerfMon counter value prior to

AAP122. An Unexpected Page Fault or EPT Violation May Occur After Another

following conditions:

seeing value 1 for the present bit).

linear address on the page.

indicating that the fault was caused by a not -present page). Intel has not observed this

erratum with any commercially available software.

erratum.

Workaround:System software can be constructed to tolerate these unexpected page faults. See

should not assume that an LL value of 01b is the L2 Cache.

Workaround:None identified.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

50 Document Number: 320767-025US

AAP124. Stack Pushes May Not Occur Properly for Events Delivered

Immediately After VM Entry to 16-Bit Software

if the VM entry establishes IA32_EFER.LMA = 0 and CS.D = 0 and only if the event

handler is also invoked with CS.D = 0.

not cause VM exits. Examples include debug exceptions, interrupts, and general-

hang. Intel has not been observed this erratum with any commercially available

software.

Workaround:None identified.

there is a preceding ongoing cache fill request initiated by a locking instruction.

of them. This means that the counter’s overflow status bit (in

MSR_PERF_GLOBAL_STATUS, MSR 38EH) may not be updated properly; additionally,

PMI interrupt may be missed if software progr ams a counter in Sampling-Mode (PMI bit

is set on counter configuration).

Workaround:Software can avoid this by:

• Avoid using Freeze PerfMon on PMI bit

• Enable only one fixed counter at a time when using Freeze PerfMon on PMI

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

AAP128. #GP May be Signaled When Invalid VEX Prefix Precedes Conditional

Branch Instructions

instruction resides in 16-bit code-segment and is associated with invalid VEX prefix, it

may sometimes signal a #GP fault (illegal instruction length > 15-bytes) instead of

#UD (illegal opcode).

TR bit [6] is set.

specifies an inaccessible location in the GDT (Global Descriptor Table).

Workaround:Operating system code should ensure that segment selectors used during task

paged into memory.

AAP131. VM Entries That Return From SMM Using VMLAUNCH May Not Update

the VMCS to "launched". Due to this erratum, such a VM entry may not update the

launch state of the current VMCS if the VM entry is returning from SMM.

is stored in the VM-instruction error field. This erratum applies only if dual monitor

treatment of SMI and SMM is active.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

52 Document Number: 320767-025US

AAP132. VM Entry May Clear Bytes 81H-83H on Virtual-APIC Page When "Use

TPR Shadow" Is 0

shadow" VM-execution control is 0. Due to this erratum, VM entry will do so if the

"virtualize x2APIC mode" VM-execution control is 1.

at bytes 81H-83H on the virtual-APIC page to be lost. Note that this combination of

Workaround:Software should alwa ys set the "use TPR shadow" VM-execution control to 1 whenev er

AAP133. A First Level Data Cache Parity Error May Result in Unexpected

the processor may exhibit unexpected behavior.

AAP135. An Event May Intervene Before a System Management Interrupt That

Results from IN or INS

Workaround:The SMM handler has to evaluate the saved context to determine if the SMI was

triggered by an instruction that read from an I/O port. The SMM handler must not

restart an I/O instruction if the platform has not been configured to generate a

synchronous SMI for the recorded I/O port address.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

AAP136. The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not

Updated After a UC Error is Logged

Error Count will not get updated after a UC error is logged.

uncorrectable error has been logged.

Workaround:None identified.

32-bit physical address specified in bits 31:12 of CR3; the upper 32 bits of CR3 should

be ignored. Due to this erratum, the processor will use a page directory located at the

64-bit physical address specified in bits 63:12 of CR3.

is in use, cause an unexpected EPT violation. This erratum applies only if software

enters 64-bit mode, loads CR3 with a 64-bit value, and then returns to 32-bit paging

AAP138. EPT Violations May Report Bits 11:0 of Guest Linear Address

dirty flag in a paging-structure entry and if that update causes an EPT violation, the

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

54 Document Number: 320767-025US

AAP140. Virtual-APIC Page Accesses With 32-Bit PAE Paging May Cause a

System Crash

paging, and accesses the virtual-APIC page then a complex sequence of internal

processor micro-architectural events may cause an incorrect address translation or

machine check on either logical processor.

IA32_MCi_STATUS.MCACOD (bits [15:0]) with a value of 0000_0000_0001_xxxxb

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

Specification Changes

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

Specification Update December 2013

56 Document Number: 320767-025US

Register 2

and i7-700 Mobile Processor Series Datasheet - Volume 2 Section 3.3.4.31 will be

updated in red text below.

Affected Docs:Intel® Core™ i7-900 Mobile Processor Extreme Edition Series, Intel® Core™ i7-800

15:6 RO 0h Reserved

Software can change this field while there is active traffic in the

3:0 RW 0000b

0000b = 2 ms

root port.

Intel® Core™ i7-800 and i7-700 Mobile Processor Series

December 2013 Specification Update

800 and i7-700 Mobile Processor Series Datasheet - Volume 2 Section 3.3.5.8 will be

updated in red text below.

Affected Docs:Intel® Core™ i7-900 Mobile Processor Extreme Edition Series, Intel® Core™ i7-800