Agilent HDMP-1687
Four Channel SerDes Circuit
for Gigabit Ethernet and
Fibre Channel
Data Sheet
Functional Description
The HDMP-1687 is a four channel
SERDES device. HDMP-1687 is in a
208-ball TBGA package with four
1.0625/1.25 Gbps serial I/O. This
integrated circuit provides a low-
cost, low-power, small-form-factor
physical-layer solution for multi-link
Gigabit Ethernet/Fibre Channel
interfaces. This IC may be used to
directly drive copper cables, or it
may be used to interface with opti-
cal transceivers. Each IC contains
transmit and receive channel cir-
cuitry for all four channels.
The transmitter section accepts
10-bit-wide parallel TTL data on
each channel and serializes it into
a high-speed serial stream. The
parallel data is expected to be
8B/10B encoded (or equivalent).
Four banks of parallel data are
latched into the input registers of
the transmitter sections on the ris-
ing edge of RFCT.
Receive data are latched out with
separate clock pins for each chan-
nel. These pins may be single
106.25/125 MHz TTL clock outputs
RC [0:3] [1] or dual 53.125/62.5
MHz TTL pairs RC [0:3] [0:1] to
serve legacy applications where
single SerDes devices were used
before. The receive clock mode
select (RCM0) pin is used to de-
fine the designer’s choice.
RCM0 Receive Clock Mode
0 half speed dual clocks
1 full speed single clocks
The SYNC pin enables bytesync
detection on all four channels.
When a comma character is
detected on any channel, its corre-
sponding SYN [0:3] pin goes high.
A single LOOP pin is provided for
all channels to enable the local
loopback function.
HDMP-1687 Block Diagram
The following is a description of
the blocks in each channel. Ex-
cept for the transmit PLL section,
circuits for the channels are inde-
pendent. Figure 1 shows how this
IC may be connected to a protocol
device that controls four channels.
Each channel of the four channel
SERDES (Figure 2) was designed
to transmit and receive 10-bit-
wide characters over dedicated
differential high-speed lines. The
parallel data applied to the trans-
mitter is expected to be encoded
per the 8B/10B encoding scheme,
with special reserve characters for
link management purposes. Other
encoding schemes will also work
as long as they provide dc balance
and sufficient transition density.
In order to accomplish this task,
the SERDES circuitry incorporates
the following:
Features
• Four ANSI x3.230- 1994 Fibre Chan-
nel (FC-O) or IEEE 802.3z Gigabit
Ethernet compatible SerDes in
a single package
• Supports serial data rates of 1062.5
MBd (Fibre Channel) & 1250 MBd
(Gigabit Ethernet)
• Based on X3T11 Fibre Channel
”10 bit specification“
• Uses reference clock (RFCT) for Tx
data latching
• Half or full speed Rx clocks
• 5-Volt tolerant TTL I/Os
• Low power consumption
• 208 ball, 23 mm TBGA package
• Single +3.3 V power supply
• 1.5 kV ESD protection on all pins
• Equalizers on inputs
• Copper drive capability
• Buffered line logic outputs
Applications
• 1250 MBd Gigabit Ethernet high
density ports
• 1062.5 MBd Fibre Channel interface
• Mass storage system I/O channel
• Work station/server I/O channel
• FC interface for disk drives and
arrays
• Serial backplanes
• Clusters
2
• TTL parallel I/Os
• High-speed phase locked loops
• Parallel-to-serial converter
• High-speed serial clock and
data recovery circuitry
• Comma character recognition
circuitry for 8B/10B
• Character alignment circuitry
• Serial-to-parallel converter
PARALLEL INPUT LATCH
The transmitter accepts 10-bit
wide single-ended TTL parallel
data at inputs TX [0:3] [0:9]. The
RFCT pin is used as transmit byte
clock. The TX [0:3] [0:9] and
RFCT signals must be properly
aligned, as shown in Figure 3.
RFCT is also used as a clean fre-
quency reference for the receiver
PLLs.
TX PLL/CLOCK GENERATOR
The transmitter Phase Locked
Loop and Clock Generator (TX
PLL/CLOCK GENERATOR) block
generates all internal clocks
needed by the transmitter section
to perform its functions. These
clocks are based on the supplied
reference clock (RFCT). RFCT is
used as the frequency reference
clock for the PLL as well as for
the incoming data latches. The
RFCT clock is multiplied by 10 to
generate the serial rate clock
necessary for clocking the high
speed serial outputs.
FRAME MUX
The FRAME MUX accepts the
10-bit wide parallel data from the
INPUT LATCH. Using internally
generated high speed clocks, this
parallel data is multiplexed into
serial data streams. The data bits
are transmitted sequentially, from
TX [0:3] [0] to TX [0:3] [9].
SERIAL OUTPUT SELECT
The OUTPUT SELECT block
provides for an optional internal
loopback of the high speed serial
signal for testing purposes.
In normal operation, LOOP is set
low and the serial data stream is
placed at SO [0:3]±. When
wrap-mode is activated by setting
LOOP high, the SO [0:3]± pins
are held static at logic 1 and the
serial output signal is internally
wrapped to the INPUT SELECT
block of the receiver section.
SERIAL INPUT SELECT
The INPUT SELECT block deter-
mines whether the signal at
SI [0:3]± or the internal loop-
back serial signal is used. In
normal operation, LOOP is set
low and the serial data is ac-
cepted at SI [0:3]±. When LOOP
is set high, the outgoing high
speed serial signal is internally
looped-back from the transmitter
section to the receiver section.
This feature allows parallel
loopback testing, exclusive of the
transmission medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto the in-
coming serial data stream and
recovering the bit and byte
clocks. The Rx PLL continually
frequency locks onto the refer-
ence clock, and then phase locks
onto the selected input data
stream. The frequency lock part
of the PLL is shared among all
channels. Phase locking is per-
formed separately on each chan-
nel. An internal signal detection
circuit monitors the presence of
the input, and invokes the phase
detection once the minimum
differential input signal level is
supplied (AC Electrical Specifica-
tions). Once bit locked, the re-
ceiver generates the high speed
sampling clock at serial data
rates for the input sampler.
SERIAL INPUT SAMPLER
The INPUT SAMPLER converts
the serial input signal into a high
speed serial bit stream. In order
to accomplish this, it uses the
high speed serial clock recovered
from the RX PLL/CLOCK RECOV-
ERY block. This serial bit stream
is sent to the FRAME DEMUX
AND BYTE SYNC block.
FRAME DEMUX, BYTE SYNC
The FRAME DEMUX, BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also re-
sponsible for recognizing the
comma character (K28.5+) of
positive disparity (0011111xxx).
When recognized, the FRAME
DEMUX, CHAR SYNC block
works with the RX PLL/CLOCK
RECOVERY block to properly
select the parallel data edge out
of the bit stream so that the
comma character starts at bit
RX [0:3] [0]. When a comma
character is detected and realign-
ment of the receiver byte clock
RC [0:3] [0:1] is necessary, this
clock is stretched, not slivered, to
the next possible correct align-
ment position. This clock will be
fully aligned by the start of the
second 4-byte ordered set. The
second comma character received
will be aligned with the rising
edge of RC [0:3] [1] and will
follow it with a delay. This delay
guarantees hold time at the re-
ceiving ICs input latches. Comma
characters of positive disparity
must not be transmitted in con-
secutive bytes to allow the re-
ceiver byte clocks to maintain
their proper recovered frequen-
cies.
PARALLEL OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the
receive byte clocks RC [0:3]
[0:1] as shown in Figure 5.
These output data buffers provide
single ended TTL compatible
signals.
3
Figure 1. Typical application using HDMP-1687.
Figure 2. Block diagram of HDMP-1687.
SO0
SI0
SO1
SI1
SI2
SO2
SI3
SO3
4-CHANNEL MAC
RC0
RX0
RFCT
RC1
RX1
RC2
RX2
RC3
RX3
HDMP-1687
TX1
TX0
TX3
TX2
SO [0:3]±
TX PLL
CLOCK
GENERATOR
CAP0
LOOP
RFCT
RC[0:3][1]
OUTPUT
DRIVER INPUT
LATCH
RX [0:3][0:9]
TX[0:3][0:9] OUTPUT
SELECT
FRAME
MUX
RX PLL
CLOCK
RECOVERY
INPUT
SELECT
FRAME
DEMUX
AND
BYTE SYNC INPUT
SAMPLER
RC[0:3][0]
CAP1
RX CLOCKS
TX CLOCKS
SYNCSYN [0:3]
LOOPBACK
SI [0:3]±
4
Timing Characteristics for Gigabit Ethernet – Transmitter Section
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol Parameter Units Min. Typ. Max.
Ttxsetup Tx Input Setup Time ns 1.5
Ttxhold Tx Input Hold Time ns 0.5
t_txlat[1] Transmitter Latency ns 2.3
bits 2.8
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of
the transmit byte clock, RFCT) and the transmission of the first serial bit of that parallel word (defined by the edge of the first bit transmitted).
Figure 3. Transmitter section timing.
Figure 4. Transmitter latency.
TX BYTE C
TX BYTE B
TX [0:3] [0:9]
TX BYTE A
SO [0:3] ±
TX BYTE B
t_txlat
S5 S6 S7 S8 S9 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S0 S1 S2 S3 S4 S5
RFCT
S6
DATA DATA
TX [0:3] [0:9]
t
txsetup
t
txhold
RFCT
DATA DATA DATA
1.4 V
2.0 V
0.8 V
Timing Characteristics for Fibre Channel – Transmitter Section
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol Parameter Units Min. Typ. Max.
Ttxsetup Tx Input Setup Time ns 2.0
Ttxhold Tx Input Hold Time ns 1.5
t_txlat[1] Transmitter Latency ns 3.8
bits 4.0
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of
the transmit byte clock, RFCT) and the transmission of the first serial bit of that parallel word (defined by the edge of the first bit transmitted).
5
Figure 5a. Receiver section timing (dual receive clocks).
Timing Characteristics for Gigabit Ethernet – Receiver Section
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol Parameter Units Min. Typ. Max.
f_lock Frequency Lock at Powerup µs 500
b_sync[1,2] Bit Sync Time bits 2500
trxsetup RX [0:3][0:9] Output Setup Time (Data Valid Before Clock) ns 2.5
trxhold RX [0:3][0:9] Output Hold Time (Data Valid After Clock) ns 2.0
Tduty RC [0:3][0] and RC [0:3][1] Duty Cycle % 40 60
tA-B Rising Edge Time Difference between RBC0 and RBC1 (Half Rate) ns 7.5 8.5
t_rxlat[3] Receiver Latency ns 20.7
bits 26.0
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using CPLL = 0.1 µF.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the
edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).
DATA DATA
RX [0:3] [0:9]
t
rxsetup
t
rxhold
RC [0:3] [1]
DATA DATA
1.4 V
2.0 V
0.8 V
SYNC
RC [0:3] [0]
t
A-B
2.0 V
0.8 V
1.4 V
K28.5+
Timing Characteristics for Fibre Channel – Receiver Section
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol Parameter Units Min. Typ. Max.
f_lock Frequency Lock at Powerup µs 500
b_sync[1,2] Bit Sync Time bits 2500
trxsetup RX [0:3][0:9] Output Setup Time (Data Valid Before Clock) ns 3.0
trxhold RX [0:3][0:9] Output Hold Time (Data Valid After Clock) ns 1.5
Tduty RC [0:3][0] and RC [0:3][1] Duty Cycle % 40 60
tA-B Rising Edge Time Difference between RBC0 and RBC1 (Half Rate) ns 8.9 9.9
t_rxlat[3] Receiver Latency ns 22.4
bits 28.0
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using CPLL = 0.1 µF.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the
edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).
6
Absolute Maximum Ratings
TA = 25°C, except as specified. Operation in excess of any one of these conditions may result in permanent damage
to this device. Continuous operation at these minimum or maximum ratings is not recommended.
Symbol Parameter Units Min. Max.
VCC Supply Voltage V –0.5 4.0
VIN,TTL TTL Input Voltage V –0.7 VCC + 2.8
VIN,HS_IN HS_IN Input Voltage (Differential) V 2.2
IO,TTL TTL Output Sink / Source Current mA ± 13
Tstg Storage Temperature °C –65 +150
TjJunction Temperature °C 0 +125
TCCase Temperature °C 0 +95
Guaranteed Operating Rates
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Parallel Clock Rate (MHz) Serial Baud Rate (MBaud)
Min. Max. Min. Max.
124.0 126.0 1240 1260 Gigabit Ethernet
105.25 107.25 1052.5 1072.5 Fibre Channel
Figure 6. Receiver latency.
RX BYTE A
RX [0:3] [0:9]
RX BYTE A
SI [0:3] ±
RX BYTE B
t_rxlat
S5 S6 S7 S8 S9 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S0 S1 S2 S3 S4 S5
RC [0:3] [1]
S6
Figure 5b. Receiver section timing (single receive clock).
DATA DATA
RX [0:3] [0:9]
t
rxsetup
t
rxhold
RC [0:3] [1]
K28.5 DATA DATA
1.4 V
2.0 V
0.8 V
7
Transceiver Reference Clock Requirements
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol Parameter Units Min. Typ. Max.
f Nominal Frequency (for Gigabit Ethernet Compliance) MHz 125
f Nominal Frequency (for Fibre Channel Compliance) MHz 106.25
Ftol Frequency Tolerance ppm –100 +100
Symm Symmetry (Duty Cycle) % 40 60
TTL I/O DC Electrical Specifications
TA = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol Parameter Units Min. Typ. Max.
VIH,TTL TTL Input High Voltage Level, V 2 5.5
Guaranteed High Signal for All Inputs
VIL,TTL TTL Input Low Voltage Level, V 0 0.8
Guaranteed Low Signal for All Inputs
VOH,TTL TTL Output High Voltage Level, IOH = –400 µA V 2.2 VCC
VOL,TTL TTL Output Low Voltage Level, IOL = 1 mA V 0 0.5
IIH,TTL Input High Current, VIN = 2.4 V, VCC = 3.45 V µA40
I
IL,TTL Input Low Current, VIN = 0.4 V, VCC = 3.45 V µA –600
ICC,TRx Transceiver VCC Supply Current, TA = 25°C mA 800
AC Electrical Specifications (TRx)
TA = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol Parameter Units Min. Typ. Max.
tr,TCi RFCT Rise Time, 0.8 to 2.0 Volts ns 0.2 2.4
tf,TCi RFCT Fall Time, 2.0 to 0.8 Volts ns 0.2 2.4
tr,TTLin Input TTL Rise Time, 0.8 to 2.0 Volts ns 1.0
tf,TTLin Input TTL Fall Time, 2.0 to 0.8 Volts ns 1.0
tr,TTLout Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load ns 1.5 2.4
tf,TTLout Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load ns 1.1 2.4
trs, HS_OUT HS_OUT Single-Ended SO [0:3]± Rise Time ps 200 300
tfs, HS_OUT HS_OUT Single-Ended SO [0:3]± Fall Time ps 200 300
trd, HS_OUT HS_OUT Differential Rise Time ps 200 300
tfd, HS_OUT HS_OUT Differential Fall Time ps 200 300
VIP,HS_IN HS_IN Input Peak-To-Peak Differential Voltage mV 200 1200 2000
VOP,HS_OUT[1] HS_OUT Output Pk-Pk Diff. Voltage (Z0=50 Ohms, Fig.10) mV 1000 1300 1800
Note:
1. Output Peak-to-Peak Differential Voltage specified as SO [0:3]+ minus SO [0:3]–. The output will be 25% higher when terminating into 75 Ω loads.
8
Note:
1. Defined by Fibre Channel Specification X3.230-1994 FC-PH Standard, Annex A, Section A.4 and tested using measurement method shown
in Figure 8.
Output Jitter Characteristics – Transmitter Section
TA = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol Parameter Units Typ.
RJ[1] Random Jitter at SO [0:3]±, the High Speed Electrical Data Port, ps 11
specified as 1 sigma deviation of the 50% crossing point (RMS)
DJ[1] Deterministic Jitter at SO [0:3]±, the High Speed Electrical Data Port (pk-pk) ps 36
Figure 7b. Eye diagram of a high speed differential output for Fibre Channel.
Figure 7a. Eye diagram of a high speed differential output for Gigabit Ethernet.
9
I/O Type Definitions
I/O Type Definition
I-TTL Input TTL, floats high when left open
O-TTL Output TTL
HS_OUT 50 Ω matched output driver. Will drive AC coupled 50 Ω loads. PECL Level Compatible (Figure 10).
HS_IN PECL Level Compatible. Must be AC coupled (Figure 10).
C External Circuit Node
S Power Supply or Ground
Pin Input Capacitance (TRx)
Symbol Parameter Units Typ. Max.
CINPUT Input Capacitance on TTL Input Pins pF 1.6
Figure 8. Transmitter jitter measurement method.
A 70841B
PATTERN
GENERATOR* A 83480A
OSCILLOSCOPE
HDMP-1687
A 70311A
CLOCK SOURCE
+ DATA
– DATA
0000011111
TRIGGER
CH1 CH2
+SOi –SOi
RFCT LOOP
TXi(0-9)
0011111000
(STATIC K28.7)
125 MHz
A. BLOCK DIAGRAM OF RJ MEASUREMENT METHOD
BIAS
TEE
1.4 V
1.25 GHz
VARIABLE
DELAY
*PATTERN
GENERATOR
PROVIDES A
DIVIDE BY 10
FUNCTION
A 70841B
PATTERN
GENERATOR
A 83480A
OSCILLOSCOPE
HDMP-1687
A 70311A
CLOCK SOURCE
+ DATA
– DATA
+K28.5, –K28.5
TRIGGER
CH1 CH2
+SOi –SOi
RFCT LOOP
TXi(0..9)
1.25 GHz
125 MHz SYNC
RXi(0..9)
–SIi
+SIi
DIVIDE
BY 2
DIVIDE BY 10
CIRCUIT
(DUAL OUTPUT)
VARIABLE
DELAY
B. BLOCK DIAGRAM OF DJ MEASUREMENT METHOD
TTL
Notes:
1. θJA is measured in a still air environment at 25°C on a standard 3 x 3" FR4 PCB as specified in EIA/JESD 51-7.
2. θJC data relevant for packages used with external heat sink.
3. To determine the actual junction temperature in a given application, use the following: TJ = TT + (ψJT x PD), where TT is the case temperature
measured on the top center of the package and PD is the power being dissipated.
Thermal and Power Characteristics (TRx)
T = 0°C Ambient to 85°C Case, VCC = 3.15 V to 3.45 V
Symbol Parameter Units Typ. Max.
PD, TRx Transceiver Power Dissipation, Outputs Connected W 2.6 3.3
per Recommended Bias Terminations with Idle Pattern
θJA[1] Thermal Resistance: Junction to Ambient °C/W 15.8
θJC[2] Thermal Resistance: Junction to Case °C/W 2.5
ψJT[3] Thermal Characterization Parameter: Junction to Package Top °C/W 1.1
10
Figure 9. O-TTL and I-TTL simplified circuit schematic.
Figure 10. HS_OUT and HS_IN simplified circuit schematic.
V
BB
1.4 V
GND
V
CC
ESD
PROTECTION
GND
V
CC
O_TTL I_TTL
GND ESD
PROTECTION
V
CC
V
CC
0.01 µF Zo = 50 Ω
Zo = 50 Ω
V
CC
V
CP
GND
GND
SI[0:3]+
SI[0:3]–
*ESD
PROTECTION
+
–+
–
HS_IN
2 * Zo = 100 Ω
V
CC
GND
GND
V
CC
NOTES:
1. HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT.
2. CAPACITORS MAY BE PLACED AT THE SENDING END OR THE RECEIVING END.
HS_OUT
ESD
PROTECTION
SO[0:3]+
Zo Zo
SO[0:3]–
0.01 µF
11
Figure 11. Pinout of HDMP-1687 (top view).
01
GND
RX04
RX00
RC00
TX14
TX10
TX04
TX00
RFCT
GND
U
T
R
P
N
M
L
K
J
H
G
A
B
C
D
E
F
02
V
CC
RX01
RC01
TX11
TX01
GND
SYN0
GND
03
GND
VCR0
RX02
TX12
TX02
SIO–
VCR0
V
CC
GND
GND
GND
GND
04
SYN1
GND
RX03
TX13
TX03
SIO+
GND
V
CC
V
CC
GND
V
CC
V
CC
GND
VCR0
GND
05
RC10
GND
V
CC
VCP0
SO0+
RC11
VCR1
SO0–
06
RX10
RX13
SI1–
GND
GND
RX11
RX12
GND
07
RX14
SI1+
VCP1
SO1+
VCR1
GND
SO1–
08
GND
GND
GNDA
GND
09
GND
V
CCA
CAP1
CAP0
VCR1
GND
N/C
10
SI2–
GND
GND
GND
V
CC
SYN2
RC20
RC21
11
SI2+
VCP2
SO2–
SO2+
GND
RX20
VCR2
GND
12
GND
GND
GND
GND
RX21
RX22
RX23
RX24
13
SI3–
VCP3
SO3–
SO3+
VCR2
14
RX31
VCR3
V
CC
LOOP
SI3+
V
CC
TX26
GND
TX33
V
CC
V
CC
15
RX32
GND
V
CC
GND
GND
TX25
GND
TX32
GND
VCR3
GND
SYN3
16
RX33
GND
GND
TX20
V
CC
TX31
V
CC
GND
VCR2
RC30
TX24
17
RX34
GND
VCR3
TX30
SYNC
RX30
GND
RC31
TX23
GND
TX34
GND
V
CC
GNDA
V
CRX
V
CCA
RX16 RX28
RX07 RX08 RX09 RX17 RX25 RX29
RX05 RX06 RX18 RX26
RX15 RX19 N/C RX27
RX36
TX18 TX19
TX15 TX16 TX17
TX08 TX09
TX05 TX06 TX07
RCM0
TX37 TX36 TX35
TX39 TX38
GND
TX29 TX28 TX27
TX22 TX21
RX39RX37 RX38
RX35
VCPX
N/C N/C
N/C
N/C
N/CN/CN/CN/CN/C
N/C
N/C
N/C
*
* Previously RFC1 changed to RFCT for data sheet consistency.
Filtering Schematic
GND
GND GND GND
GND
GND
GND
GND
GND
GND
GNDGND
GND GND
GND
GND GND
GND GND
GND GND
GNDGNDGND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGNDGND
GNDGNDGND
GND
GND
GND
GNDGND
VCR
VCR
VCR VCR
VCR
VCR VCR
VCR
VCR
VCR VCR VCR
V
CC
A
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
VCP VCP VCP VCP
0.1 µF 0.1 µF
0.1 µF 0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF 0.1 µF
0.1 µF
0.1 µF 0.1 µF
0.1 µF
10 µF*
10 µF
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
* 10 µF PLACEMENT NOT CRITICAL – INDICATES
NEED FOR LOW-FREQUENCY BYPASS CAPACITANCE
HDMP-1687
TO V
CC
A PI-FILTER (SEE SCHEMATIC)
12
Guidelines for Decoupling Capacitor Placements/Connections
VCR
V
CC
HDMP-1687
GUIDELINES FOR
DECOUPLING CAPACITOR
PLACEMENTS/CONNECTIONS
R4
V
CC
VCR
VCR
VCR
V
CC
V
CC
V
CC
V
CC
VCR
VCR
VCR
VCR
V
CC
V
CC
V
CC
VCR
VCR
V
CC
VCR
VCR
V
CC
V
CC
VCP
V
CC
VCP
V
CCA
VCP
VCP
V
CC
V
CC
R14
A2
0.1 µF
0.1 µF
+
+
1 µH
0.1 µF
L4
G4
0.1 µF
C4
C5
D3
F3
0.1 µF
B7
A9
A10
A13
A16
10 µF
0.1 µF
C11
C14
C15
E14
G17
K16
N15
J14
R16
T14
T13
T11
+10 µF
T7
T3
U5
T5
T4
T9
0.1 µF 0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF 0.1 µF
V
CC
10 µF
0.1 µF
V
CC
+
*
*
+
PLACEMENT NOT CRITICAL.
INDICATES THE NEED FOR ADDITIONAL
LOW FREQUENCY CAPACITIVE DECOUPLING.
OPTIONAL – PROVIDES INCREASED
LOW FREQUENCY DECOUPLING.
13
TRx I/O Definition
Name Type Signal
SI [0:3]+ HS_IN Serial Data Inputs: High-speed inputs. Serial data is accepted from the SI [0:3]±
SI [0:3]– inputs when LOOP is low.
SO [0:3]+ HS_ OUT Serial Data Outputs: High speed outputs. These lines are active when LOOP is
SO [0:3]– set low. When LOOP is set high, these outputs are held static at logic 1.
SYNC I-TTL Enable Byte Sync Input: When high, turns on the internal byte sync functions to
allow clock synchronization to a comma character of positive disparity (0011111XXX).
When the line is low, the function is disabled and will not reset registers and clocks,
or strobe the SYN [0:3] lines.
SYN [0:3] O-TTL Byte Sync Outputs: Active high outputs. Used to indicate detection of a comma
character of positive disparity (0011111XXX) when SYNC is enabled.
N/C These pins need to be left open. Do not apply voltage on this pin.
LOOP I-TTL Loopback Enable Input: When set high, the high speed serial signal is internally
wrapped from the transmitter’s serial loopback outputs back to the receiver‘s
loopback inputs. Also when in loopback mode, the SO [0:3]± outputs are held static
at logic 1. When set low, SO [0:3]± outputs and SI [0:3]± inputs are active.
RCM0 I-TTL Receivers Clocking Mode Definition Pins: These pins define how received
parallel data are driven as follows:
RCM0 Receive Clock Mode
0 half speed dual clocks
1 full speed single clocks
RC [0:3] [0:1] O-TTL Receiver Byte Clocks: The receiver sections drive 125 MHz receive byte clocks
RC [0:3] [1]. Alternatively, they may drive half speed clocks RC [0:3] [0:1]. See RCM0
definition.
RFCT I-TTL Reference Clock and Transmit Byte Clock: A 125 MHz clock supplied by the host
system. The transmitter sections accept this signal as the frequency reference clock.
It is multiplied by 10 to generate the serial bit clock and other internal clocks. The
transmit sections use this clock as the transmit byte clock for transmitting parallel
data at TX [0:3] [0:9].
RX [0:3] [0] O-TTL Data Outputs: Four 10 bit data bytes. RX [0:3] [0] are the first bits received.
RX [0:3] [1]
RX [0:3] [2]
RX [0:3] [3]
RX [0:3] [4]
RX [0:3] [5]
RX [0:3] [6]
RX [0:3] [7]
RX [0:3] [8]
RX [0:3] [9]
CAP0 C Loop Filter Capacitor: A loop filter capacitor for the internal PLLs must be connected
CAP1 across the CAP0 and CAP1 pins. (typical value = 0.1µF).
14
TRx I/O Definition, continued
Name Type Signal
TX [0:3] [0] I-TTL Data Inputs: Four 10 bit, 8B/10B encoded data bytes. TX [0:3] [0] are the first bits
TX [0:3] [1] transmitted.
TX [0:3] [2]
TX [0:3] [3]
TX [0:3] [4]
TX [0:3] [5]
TX [0:3] [6]
TX [0:3] [7]
TX [0:3] [8]
TX [0:3] [9]
VCC SPower Supply: Nominally 3.3 volts. Used for logic and TTL inputs.
VCCA SAnalog Power Supply: Nominally 3.3 volts. Used to provide a clean supply
line for the PLLs and high speed analog cells.
VCR3-0 S Rx TTL Output Power Supply: Nominally 3.3 volts.
Used for all TTL receiver output buffer cells.
VCP3-0 S High Speed Output Supply: Nominally 3.3 volts. Used only for the last stage
of the high speed transmitter output cells (HS_OUT) as shown in Figure 10.
Due to high current transitions, this Vcc should be well bypassed to a ground plane.
GND S Ground: Nominally 0 volts. All GND pads on the chip are connected to one ground slug
in the package which then distributes these to GND balls.
GNDA S Analog Ground: Normally 0 volts. All GND pads on the chip are connected to one
ground slug in the package, which then distributes these to GND balls.
208 Ball 23 mm x 23 mm TBGA Package Drawing
HDMP-1687
ABCD–N RE.FG
S YYWW
HONG KONG
TOP VIEW
Procedure to follow for soldering the HDMP-1687, 208-ball TBGA package:
IR or Convective Reflow per IPC/JEDEC J-STD-020A standard for BGA IR Reflow.
A1 CORNER
15
Package Drawing
Zddd
DETAIL A
[–Z–] SEATING PLANE
A
A2
D
E
[–Y–]
[–X–]
SEATING PLANE
A1
A3
(BACKFILL)
[–Z–]
DETAIL A
E1
Nx0b
e
S
D1
e
S
O (4x)
Y∅ eee
A
B
C
D
E
12345 (CAVITY DOWN)
(BACKFILL)
XZM
A1 CORNER
SYMBOL MIN. NOM. MAX.
A 1.35 1.50 1.65
A1 0.60 0.65 0.70
A2 0.85 0.90 0.95
A3 0.15
D 23.00 ± 0.20
D1 20.32 BSC
E 23.00 ± 0.20
E1 20.32 BSC
MD/ME 17
N 208
N1 4
O 0.60
b 0.60 0.75 0.90
e 1.27 ± 0.10
DIMENSIONS IN MILLIMETERS
SYMBOL MIN. NOM. MAX.
ddd 0.15
eee 0.30
TOLERANCE OF FORM AND POSITION
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2001 Agilent Technologies, Inc.
September 21, 2001
Obsoletes 5988-1305EN
5988-4080EN
