MAX4969CTO+ - Maxim Integrated

_______________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

PCIe, Single Lane, 2:1/1:2 Multiplexer and

Redriver with Equalization

MAX4969

General Description

The MAX4969 active 2:1 and 1:2 multiplexer equalizes

and redrives PCIeM signals up to 5.0GT/s (Gigatransfers

per second) and operates from a single +3.3V supply.

The MAX4969 features PCIe-required electrical idle and

receiver detection on each channel, and improves signal

integrity at the receiver through independent program-

mable input equalization and output deemphasis.

The MAX4969 is available in a small, 42-pin (3.5mm x

9.0mm) TQFN package optimal for simplified layout and

space-saving requirements. The MAX4969 is specified

over the 0NC to +70NC commercial operating tempera-

ture range.

Applications

Blade Servers

Workstations

Communications Switches

Test Equipment

Storage Area Network

Features

S Single +3.3V Supply Operation

S PCIe Gen 1 (2.5GT/s) and Gen 2 (5.0GT/s)

Return Loss ≥ 8dB (1.25GHz ≤ f ≤ 2.5GHz)

S Independent Input Equalization

S Independent Output Deemphasis

S Independent Output Level Selection

Reduced Power and EMI

S On-Chip 50I Input/Output Terminations

S Inline Signal Traces for Simplified Layout

S Space-Saving, 3.5mm x 9.0mm TQFN Package

19-4810; Rev 0; 7/09

Pin Configuration

Ordering Information

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

PCIe is a registered trademark of PCI-SIG Corp.

TOP VIEW

TQFN

INEQA1

INEQA0

INEQB1

INEQB0

42 +

ODEA1

ODEA0

ODEB1

ODEB0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

OUTP

OUTM

GND

ODE1

ODE0

VCC

GND

SEL2

SEL1

GND

INM

INP

GND

INEQ0

INEQ1

VCC

INAM

GND

INBP

INBM

GND

VCC

INAP

GND

RX_DET

GND

OUTBM

OUTBP

GND

OUTAM

OUTAP

GND

VCC

*CONNECT EXPOSED PAD (EP) TO GND.

*EP

MAX4969

PART TEMP RANGE PIN-PACKAGE

MAX4969CTO+ 0NC to +70NC42 TQFN-EP*

PCIe, Single Lane, 2:1/1:2 Multiplexer and

Redriver with Equalization

MAX4969

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

(Voltages referenced to GND.)

VCC .......................................................................-0.3V to +4.0V

All Other Pins (Note 1) ............................ -0.3V to (VCC + 0.3V)

Continuous Current, IN_P, IN_M, OUT_P, OUT_M ......... Q30mA

Peak Current, IN_P, IN_M, OUT_P,

OUT_M (for 10kHz, 1% duty cycle) .......................... Q100mA

Continuous Power Dissipation (TA = +70NC)

42-Pin TQFN (derate 34.5mW/NC above +70NC) ......2758mW

Junction-to-Case Thermal Resistance

BJC (Note 2) ................................................................ +2NC/W

Junction-to-Ambient Thermal Resistance

BJA (Note 2) .............................................................. +29NC/W

Operating Temperature Range ............................. 0NC to +70NC

Junction Temperature Range ........................... -40NC to +150NC

Storage Temperature Range ............................ -65NC to +150NC

Lead Temperature (soldering, 10s) ................................+300NC

ELECTRICAL CHARACTERISTICS

(VCC = +3.0V to +3.6V, CCL = 75nF coupling capacitor on each output, RL = 50I on each output, TA = 0NC to +70NC, unless other-

wise noted. Typical values are at VCC = +3.3V and TA = +25NC.) (Note 3)

ABSOLUTE MAXIMUM RATINGS

Note 1: All I/O pins are clamped by internal diodes.

Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC PERFORMANCE

Power-Supply Range VCC 3.0 3.6 V

Supply Current ICC EN = VCC INEQ_ = ODE_ = GND 120 150

mAINEQ_ = ODE_ = VCC 160 200

EN = GND 50

Input Impedance, Differential ZRX-DIFF-DC DC 80 100 120 I

Output Impedance, Differential ZTX-DIFF-DC DC 80 100 120 I

Common-Mode Resistance to

GND, Input Terminations Not

Powered

ZRX-HIGH-IMP-

DC-POS VIN_P = VIN_M = 0 to 200mV 50 kI

ZRX-HIGH-IMP-

DC-NEG VIN_P = VIN_M = -150mV to 0V 1 kI

Common-Mode Resistance

to GND, Input Terminations

Powered

ZRX-DC DC 40 50 60 I

Output Short-Circuit Current ITX-SHORT Single-ended (Note 4) 90 mA

Common-Mode Delta, Between

Active and Idle States

VTX-CM-DC-

ACTIVE-IDLE-

DELTA

-100 +100 mV

DC Output Offset, During

Active State

VTX-CM-DC-

LINE-DELTA

Difference between DC average of

VOUT_P and VOUT_M -25 +25 mV

DC Output Offset, During

Electrical Idle

VTX-IDLE-DIFF-

DC ABS(VOUT_P - VOUT_M) -10 +10 mV

AC PERFORMANCE

Input Return Loss, Differential RLRX-DIFF 0.05GHz < f P 1.25GHz (Note 4) 10 dB

1.25GHz < f P 2.5GHz (Note 4) 8 dB

PCIe, Single Lane, 2:1/1:2 Multiplexer and

Redriver with Equalization

MAX4969

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +3.0V to +3.6V, CCL = 75nF coupling capacitor on each output, RL = 50I on each output, TA = 0NC to +70NC, unless other-

wise noted. Typical values are at VCC = +3.3V and TA = +25NC.) (Note 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Return Loss, Common

Mode RLRX-CM 0.05GHz < f P 2.5GHz (Note 4) 6 dB

Output Return Loss, Differential RLTX-DIFF 0.05GHz < f P 1.25GHz (Note 4) 10 dB

1.25GHz < f P 2.5GHz (Note 4) 8 dB

Output Return Loss, Common

Mode RLTX-CM 0.05GHz < f P 2.5GHz (Note 4) 6 dB

Differential Input Signal Range,

Redriver Operation VRX-DIFF-PP 0.05GHz < f P 2.5GHz 150 1200 mVP-P

Differential Output Voltage, Full

Swing, No Deemphasis VTX-DIFF-PP

2 x ABS(VOUT_P - VOUT_M),

ODE_1 = GND, ODE_0 = VCC

(see Table 1), f = 500MHz

800 1000 1200 mVP-P

Differential Output Voltage, Low

Swing, No Deemphasis

VTX-DIFF-PP-

LOW

2 x ABS(VOUT_P - VOUT_M),

ODE_1 = ODE_0 = GND (see Table 1),

f = 500MHz

600 750 900 mVP-P

Output Deemphasis Ratio, 0dB VTX-DE-RATIO-

0dB

f = 2.5GHz, ODE_1 = GND, ODE_0 =

VCC or GND, Figure 1 (see Table 1) 0 dB

Output Deemphasis Ratio,

3.5dB

VTX-DE-RATIO-

3.5dB

f = 2.5GHz, ODE_1 = VCC,

ODE_0 = GND, Figure 1 (see Table 1) 3.5 dB

Output Deemphasis Ratio, 6dB VTX-DE-RATIO-

6dB

f = 2.5GHz, ODE_1 = VCC,

ODE_0 = VCC, Figure 1 (see Table 1) 6 dB

Input Equalization, 0dB VRX-EQ-0dB f = 2.5GHz, INEQ_1 = GND,

INEQ_0 = GND or VCC (see Table 2) 0 dB

Input Equalization, 3.5dB VRX-EQ-3.5dB f = 2.5GHz, INEQ_1 = VCC,

INEQ_0 = GND (see Table 2) 3.5 dB

Input Equalization, 6dB VRX-EQ-6dB f = 2.5GHz, INEQ_1 = VCC, INEQ_0 =

VCC (see Table 2) 6 dB

Output Common-Mode Voltage VTX-CM-AC-PP MAX(VOUT_P + VOUT_M)/2 -

MIN(VOUT_P + VOUT_M)/2 (Note 4) 100 mVP-P

Propagation Delay TPD (Note 4) 160 280 400 ps

Rise/Fall Time TTX-RISE-FALL (Notes 4, 5) 30 ps

Rise/Fall Time Mismatch TTX-RF-

MISMATCH (Notes 4, 5) 20 ps

Output Skew Same Pair TSK (Note 4) 10 15 ps

Deterministic Jitter TTX-DJ-DD

K28.5 P pattern, AC-coupled, RL = 50I,

effects of deemphasis deembedded

(Note 4), 5GT/s

20 psP-P

Random Jitter TTX-RJ-DD D10.2 pattern, f > 1.5MHz 0.5 1.4 psRMS

Electrical Idle Entry Delay TTX-IDLE-SET-

TO-IDLE From input to output 15 ns

Electrical Idle Exit Delay TTX-IDLE-TO-

DIFF-DATA From input to output 8 ns

PCIe, Single Lane, 2:1/1:2 Multiplexer and

Redriver with Equalization

MAX4969

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +3.0V to +3.6V, CCL = 75nF coupling capacitor on each output, RL = 50I on each output, TA = 0NC to +70NC, unless other-

wise noted. Typical values are at VCC = +3.3V and TA = +25NC.) (Note 3)

Note 3: All devices are 100% production tested at TA = +70NC. Specifications for all temperature limits are guaranteed by design.

Note 4: Guaranteed by design.

Note 5: Rise and fall times are measured using 20% and 80% levels.

Timing Diagram

Figure 1. Illustration of Output Deemphasis

VLOW_P-P VHIGH_P-P

VHIGH_P-P

VLOW_P-P

DE(dB) = 20 log

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Electrical Idle Detect Threshold VTX-IDLE-

THRESH 65 100 120 mVP-P

Output Voltage During

Electrical Idle (AC)

VTX-IDLE-DIFF-

AC-P ABS(VOUT_P - VOUT_M) 35 mVP-P

Receiver Detect Pulse

Amplitude

VTX-RCV-

DETECT

Voltage change in positive direction

(Note 4) 600 mV

Receiver Detect Pulse Width 100 ns

Receiver Detect Retry Period 200 ns

CONTROL LOGIC

Input Logic-Level Low VIL 0.6 V

Input Logic-Level High VIH 1.4 V

Input Logic Hysteresis VHYST 130 mV

Input Pulldown Resistor RDOWN 37.5 60 150 kW

PCIe, Single Lane, 2:1/1:2 Multiplexer and

Redriver with Equalization

MAX4969

Typical Operating Characteristics

(VCC = +3.3V, TA = +25NC, unless otherwise noted.)

VIN = 500mVP-P WITH 19in STRIPLINE,

5GT/s, ODE_ = 01, INEQ_ = 00

50ps/div

200mV/div

1501000 50-100 -50-150

-600

-400

-200

200

400

600

MAX4969 toc06

VIN = 500mVP-P WITH 6in STRIPLINE,

5GT/s, ODE_ = 01, INEQ_ = 00

50ps/div

200mV/div

1501000 50-100 -50-150

-600

-400

-200

200

400

600

MAX4969 toc05

VIN = 200mVP-P, 5GT/s,

ODE_ = 11, INEQ_ = 00

50ps/div

200mV/div

1501000 50-100 -50-150

-600

-400

-200

200

400

600

MAX4969 toc04

VIN = 200mVP-P, 5GT/s,

ODE_ = 10, INEQ_ = 00

50ps/div

200mV/div

1501000 50-100 -50-150

-600

-400

-200

200

400

600

MAX4969 toc03

VIN = 200mVP-P, 5GT/s,

ODE_ = 01, INEQ_ = 00

50ps/div

200mV/div

1501000 50-100 -50-150

-600

-400

-200

200

400

600

MAX4969 toc02

VIN = 200mVP-P, 5GT/s,

ODE_ = 00, INEQ_ = 00

50ps/div

100mV/div

1501000 50-100 -50-150

-500

-400

-300

-200

-100

100

200

300

400

500

MAX4969 toc01

PCIe, Single Lane, 2:1/1:2 Multiplexer and

Redriver with Equalization

MAX4969

Typical Operating Characteristics (continued)

(VCC = +3.3V, TA = +25NC, unless otherwise noted.)

VIN = 500mVP-P, 5GT/s, ODE_ = 11,

INEQ_ = 00, AFTER 19in STRIPLINE

50ps/div

100mV/div

1501000 50-100 -50-150

-300

-200

-100

100

200

300

MAX4969 toc10

VIN = 500mVP-P, 5GT/s, ODE_ = 01,

INEQ_ = 00, AFTER 19in STRIPLINE

50ps/div

200mV/div

1501000 50-100 -50-150

-600

-400

-200

200

400

600

MAX4969 toc09

VIN = 500mVP-P, 5GT/s, ODE_ = 01,

INEQ_ = 00, AFTER 6in STRIPLINE

50ps/div

200mV/div

1501000 50-100 -50-150

-600

-400

-200

200

400

600

MAX4969 toc08

VIN = 500mVP-P WITH 19in STRIPLINE,

5GT/s, ODE_ = 01, INEQ_ = 11

50ps/div

200mV/div

1501000 50-100 -50-150

-600

-400

-200

200

400

600

MAX4969 toc07

PCIe, Single Lane, 2:1/1:2 Multiplexer and

Redriver with Equalization

MAX4969

Pin Description

PIN NAME FUNCTION

1, 17, 22,

38 VCC Power-Supply Input. Bypass VCC to GND with 1FF and 0.01FF capacitors in parallel as close to the

device as possible, recommended on each VCC pin.

2 INEQ1 Channel 1 Input Equalization Control MSB. See Table 2. INEQ1 is internally pulled down by a 60kI

(typ) resistor.

3 INEQ0 Channel 1 Input Equalization Control LSB. See Table 2. INEQ0 is internally pulled down by a 60kI

(typ) resistor.

4, 7, 11, 14,

23, 26, 29,

31, 34, 37

GND Ground

5 INP Channel 1 Noninverting Input

6 INM Channel 1 Inverting Input

8 SEL1 Channel 1 Active Output Selection Input. Drive SEL1 low to activate A outputs. Drive SEL high to

activate B outputs. SEL1 is internally pulled down by a 60kI (typ) resistor.

9 SEL2 Channel 2 Active Input Selection Input. Drive SEL2 low to activate A inputs. Drive SEL high to acti-

vate B inputs. SEL2 is internally pulled down by a 60kI (typ) resistor.

10 EN Enable Input. Drive EN low for reduced power standby mode. Drive EN high for normal operation.

EN is internally pulled down by a 60kI (typ) resistor.

12 OUTP Channel 2 Noninverting Output

13 OUTM Channel 2 Inverting Output

15 ODE1 Channel 2 Output Deemphasis Control MSB. See Table 1. ODE1 is internally pulled down by a 60kI

(typ) resistor.

16 ODE0 Channel 2 Output Deemphasis Control LSB. See Table 1. ODE0 is internally pulled down by a 60kI

(typ) resistor.

18 INEQA1 Channel 2 Input A Equalization Control MSB. See Table 2. INEQA1 is internally pulled down by a

60kI (typ) resistor.

19 INEQA0 Channel 2 Input A Equalization Control LSB. See Table 2. INEQA0 is internally pulled down by a

60kI (typ) resistor.

20 INEQB1 Channel 2 Input B Equalization Control MSB. See Table 2. INEQB1 is internally pulled down by a

60kI (typ) resistor.

21 INEQB0 Channel 2 Input B Equalization Control LSB. See Table 2. INEQB0 is internally pulled down by a

60kI (typ) resistor.

24 INBM Channel 2 Inverting Input B

25 INBP Channel 2 Noninverting Input B

27 INAM Channel 2 Inverting Input A

28 INAP Channel 2 Noninverting Input A

30 RX_DET Receiver Detection Control Bit. Toggle RX_DET to initiate receiver detection. RX_DET is internally

pulled down by a 60kI (typ) resistor.

32 OUTBM Channel 1 Inverting Output B

33 OUTBP Channel 1 Noninverting Output B

35 OUTAM Channel 1 Inverting Output A

36 OUTAP Channel 1 Noninverting Output A

39 ODEB0 Channel 1 Output B Deemphasis Control LSB. See Table 1. ODEB0 is internally pulled down by a

60kI (typ) resistor.

PCIe, Single Lane, 2:1/1:2 Multiplexer and

Redriver with Equalization

MAX4969

Pin Description

Functional Diagram

MAX4969

VCC

CHANNEL 1

CONTROL

GLOBAL CONTROL

ODEB0

OUTAP

OUTAM

OUTBP

OUTBM

INAP

INAM

INBP

INBM

ODEB1

ODEA0

ODEA1

INEQ1

INEQ0

SEL1

RX_DET

INP

INM

CHANNEL 2

CONTROL

SEL2

ODE1

GND

ODE0

INEQA1

INEQA0

INEQB1

INEQB0

OUTP

OUTM

VCC

PIN NAME FUNCTION

40 ODEB1 Channel 1 Output B Deemphasis Control MSB. See Table 1. ODEB1 is internally pulled down by a

60kI (typ) resistor.

41 ODEA0 Channel 1 Output A Deemphasis Control LSB. See Table 1. ODEA0 is internally pulled down by a

60kI (typ) resistor.

42 ODEA1 Channel 1 Output A Deemphasis Control MSB. See Table 1. ODEA1 is internally pulled down by a

60kI (typ) resistor.

— EP Exposed Pad. Internally connected to GND. Connect EP to a large ground plane to maximize ther-

mal performance. EP is not intended as an electrical connection point.

PCIe, Single Lane, 2:1/1:2 Multiplexer and

Redriver with Equalization

MAX4969

Detailed Description

The MAX4969 is an active 2:1/1:2 multiplexer designed

to equalize and redrive PCIe signals up to 5.0GT/s. The

MAX4969 features PCIe-required electrical idle and

receiver detection on each channel, and improves signal

integrity at the receiver through independent program-

mable input equalization and output deemphasis.

Enable Input (EN)

The MAX4969 features an active-high enable input (EN).

EN has an internal pulldown resistor of 60kI (typ). When

EN is driven low or left unconnected, the MAX4969

enters reduced power standby mode and the redrivers

are disabled. Drive EN high for normal operation.

Active Input/Output Select (SEL1, SEL2)

SEL1 selects the active output for channel 1 and SEL2

selects the active input for channel 2. Drive SEL1 or

SEL2 low or leave unconnected to activate A inputs or

outputs. Drive SEL1 or SEL2 high to activate B inputs or

outputs. SEL1 and SEL2 have internal pulldown resistors

of 60kI (typ).

Programmable Output Deemphasis

(ODE_0, ODE_1)

The MAX4969 features independent programmable out-

put deemphasis capable of providing 0dB, 3.5dB, or

6dB deemphasis on any channel. When both ODE_0 and

ODE_1 are driven low or left unconnected, the output is

in low-swing mode (750mV typ) (see Table 1). ODE0,

ODE1, ODEA0, ODEA1, ODEB0, and ODEB1 have inter-

nal pulldown resistors of 60kI (typ).

Programmable Input Equalization

(INEQ_0, INEQ_1)

The MAX4969 features independent programmable

input equalization capable of providing 0dB, 3.5dB, or

6dB of high-frequency equalization on any channel (see

Table 2.) INEQ0, INEQ1, INEQA0, INEQA1, INEQB0, and

INEQB1 have internal pulldown resistors of 60kI (typ).

Receiver Detection (RX_DET)

The MAX4969 features receiver detection on each chan-

nel. Receiver detection initializes on the rising edge

of EN, or upon initial power-up if EN is high. Receiver

detection can also be initiated on a rising or falling edge

of the RX_DET, SEL1, or SEL2 inputs when EN is high.

During this time, the part remains in reduced power

standby mode and the outputs are squelched, despite

the logic-high state of EN. Once started, receiver detec-

tion repeats indefinitely on each channel. Once a receiv-

er is detected on one of the channels, up to 216 more

attempts are made on the other channel. Upon receiver

detection, channel output and electrical idle detection

are enabled (see Table 3). RX_DET has an internal pull-

down resistor of 60kI (typ).

Electrical Idle Detection

The MAX4969 features electrical idle detection to pre-

vent unwanted noise from being redriven at the output.

If the MAX4969 detects that the differential input has

fallen below VTX-IDLE-THRESH, the MAX4969 squelches

the output. For differential input signals that are above

VTX-IDLE-THRESH, the MAX4969 turns on the output and

redrives the signal.

Table 1. Output Deemphasis

Table 3. Receiver Detection

Table 2. Input Equalization

X = Don’t Care

ODE_1 ODE_0 OUTPUT DEEMPHASIS

(dB)

0 0 0, low swing

0 1 0, full swing

1 0 3.5, full swing

1 1 6, full swing

INEQ_1 INEQ_0 INPUT EQUALIZATION

(dB)

0 X 0

1 0 3.5

1 1 6

RX_DET/

SEL1/SEL2 EN DESCRIPTION

X 0 Receiver detection inactive

0 1 Following a rising or falling edge; indefinite retry until receiver detected

Rising or falling edge 1 Initiate receiver detection

1 1 Following a rising or falling edge; indefinite retry until receiver detected

PCIe, Single Lane, 2:1/1:2 Multiplexer and

Redriver with Equalization

MAX4969

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.

Maxim reserves the right to change the circuitry and specifications without notice at any time.

10 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Applications Information

Layout

Circuit board layout and design can significantly affect

the performance of the MAX4969. Use good high-fre-

quency design techniques, including minimizing ground

inductance and using controlled-impedance transmis-

sion lines on data signals. It is recommended to run

receive and transmit on different layers to minimize

crosstalk and to place 1FF and 0.01FF power-supply

bypass capacitors in parallel as close to VCC as possible

on each VCC pin. Always connect VCC to a power plane.

Exposed Pad Package

The exposed-pad, 42-pin TQFN package incorporates

features that provide a very low thermal resistance path

for heat removal from the IC. The exposed pad on the

MAX4969 must be soldered to the circuit board ground

plane for proper thermal performance. For more informa-

tion on exposed-pad packages, refer to Application Note

862: HFAN-08.1: Thermal Considerations of QFN and

Other Exposed-Paddle Packages.

Power-Supply Sequencing

Caution: Do not exceed the absolute maximum rat-

ings because stresses beyond the listed ratings may

cause permanent damage to the device.

Proper power-supply sequencing is recommended for

all devices. Always apply GND then VCC before apply-

ing signals, especially if the signal is not current limited.

Chip Information

PROCESS: BiCMOS

Package Information

For the latest package outline information and land pat-

terns, go to www.maxim-ic.com/packages. Note that

a “+”, “#”, or “-” in the package code indicates RoHS

status only. Package drawings may show a different suf-

fix character, but the drawing pertains to the package

regardless of RoHS status.

Typical Application Circuit

MAX4969

OUT

OUTA

OUTB

INA

INB

PCIe

HOST

PCIe

DEVICE B

PCIe

DEVICE A

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

42 TQFN-EP T423590+1 21-0181