_______________General Description
The MAX517/MAX518/MAX519 are 8-bit voltage output
digital-to-analog converters (DACs) with a simple 2-wire
serial interface that allows communication between
multiple devices. They operate from a single 5V supply
and their internal precision buffers allow the DAC out-
puts to swing rail-to-rail.
The MAX517 is a single DAC and the MAX518/MAX519
are dual DACs. The MAX518 uses the supply voltage
as the reference for both DACs. The MAX517 has a ref-
erence input for its single DAC and each of the
MAX519’s two DACs has its own reference input.
The MAX517/MAX518/MAX519 feature a serial interface
and internal software protocol, allowing communication
at data rates up to 400kbps. The interface, combined
with the double-buffered input configuration, allows the
DAC registers of the dual devices to be updated indi-
vidually or simultaneously. In addition, the devices can
be put into a low-power shutdown mode that reduces
supply current to 4µA. Power-on reset ensures the DAC
outputs are at 0V when power is initially applied.
The MAX517/MAX518 are available in space-saving 8-
pin DIP and SO packages. The MAX519 comes in 16-
pin DIP and SO packages.
________________________Applications
Minimum Component Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Automatic Test Equipment
Programmable Attenuators
____________________________Features
♦Single +5V Supply
♦Simple 2-Wire Serial Interface
♦I2C Compatible
♦Output Buffer Amplifiers Swing Rail-to-Rail
♦Space-Saving 8-pin DIP/SO Packages
(MAX517/MAX518)
♦Reference Input Range Includes Both Supply Rails
(MAX517/MAX519)
♦Power-On Reset Clears All Latches
♦4µA Power-Down Mode
______________Ordering Information
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
________________________________________________________________ Maxim Integrated Products 1
1
2
3
4
8
7
6
5
OUT1 (REF0)
VDD
AD0
AD1
SDA
SCL
GND
OUT0
MAX517
MAX518
DIP/SO
TOP VIEW
_________________Pin Configurations
INPUT
LATCH 0 OUTPUT
LATCH 0
START/STOP
DETECTOR
DAC0
INPUT
LATCH 1
8-BIT
SHIFT
REGISTER
OUT0
REF
REF
OUT1
MAX518
8
1
DECODE
ADDRESS
COMPARATOR
DAC1
OUTPUT
LATCH 1
VDD
7
SCL
SDA
AD0 AD1
3
4
65
GND
2
________________Functional Diagram
19-0393; Rev 1; 9/02
PART
MAX517ACPA
MAX517BCPA
MAX517ACSA 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP RANGE PIN-PACKAGE
8 Plastic DIP
8 Plastic DIP
8 SO
TUE
(LSB)
1
1.5
1
MAX517BCSA
MAX517BC/D 0°C to +70°C
0°C to +70°C 8 SO
Dice*
1.5
1.5
Ordering Information continued at end of data sheet.
*Dice are specified at TA= +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.
( ) ARE FOR MAX517
Pin Configurations continued at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 5V ±10%, VREF_ = 4V (MAX517, MAX519), RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.
Typical values are TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
OUT_ ..........................................................-0.3V to (VDD + 0.3V)
REF_ (MAX517, MAX519)...........................-0.3V to (VDD + 0.3V)
AD_.............................................................-0.3V to (VDD + 0.3V)
SCL, SDA to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) ...727mW
8-Pin SO (derate 5.88mW/°C above +70°C)................471mW
8-Pin CERDIP (derate 8.00mW/°C above +70°C)........640mW
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)..842mW
16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ...696mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C) ......800mW
Operating Temperature Ranges
MAX51_C_ _ .......................................................0°C to +70°C
MAX51_E_ _.....................................................-40°C to +85°C
MAX51_MJB ..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
±1MAX51 _BM
±1MAX51 _E
MAX51 _C
Full-Scale-Error Temperature Coefficient
Full-Scale-Error Supply Rejection
±1
mV
±10 µV/°C
MAX517, MAX519
Code = FF hex
VDD = +5V ±10%
Code = FF hex
±20MAX51 _E mV
MAX51 _C
±1MAX51 _BM
±1MAX51 _E
MAX51 _C
20MAX51 _BM
20MAX51 _E
MAX51 _C
MAX51 _A
PARAMETER SYMBOL MIN TYP MAX UNITS
Resolution 8Bits
TUE ±1
Differential Nonlinearity (Note 1) DNL ±1 LSB
Zero-Code Error ZCE
18
mV
Zero-Code-Error Supply Rejection
±1
Zero-Code-Error Temperature Coefficient ±10 µV/°C
Full-Scale Error
±18
CONDITIONS
Guaranteed monotonic
Code = 00 hex
Code = 00 hex
Code = 00 hex
Code = FF hex,
MAX518 unloaded
mV
MAX51 _B ±1.5
Total Unadjusted Error (Note 1) LSB
±20
MAX51 _BM
STATIC ACCURACY
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±10%, VREF_ = 4V (MAX517, MAX519), RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.
Typical values are TA= +25°C.)
0.6ISINK = 6mA
ISINK = 3mA
0.3VDD
Input High Voltage VIH 0.7VDD V
Input Leakage Current IIN ±10 µA
Output Low Voltage VOL
0.4 V
Three-State Leakage Current IL±10 µA
Three-State Output Capacitance COUT 10
0V ≤VIN ≤VDD
VIN = 0V to VDD
(Note 6)
PARAMETER SYMBOL MIN TYP MAX UNITS
Output Leakage Current ±10 µA
CONDITIONS
OUT_ = 0V to VDD, power-down mode
pF
LSB
1.5
VIL
Input Hysteresis VHYST 0.05VDD V
Input Capacitance CIN 10 pF(Note 6)
Input High Voltage VIH 2.4 V
Input Low Voltage VIL 0.8 V
Input Leakage Current IIN ±10 µAVIN = 0V to VDD
Voltage Output Slew Rate
2.0
Positive and negative V/µs
MAX51 _C
Output Settling Time µs
Digital Feedthrough 5Code = 00 hex, all digital inputs from 0V to VDD nV-s
1.4MAX51 _E
1.0MAX51 _M
Input Voltage Range 0V
DD V
Input Resistance RIN 16 24 kΩCode = 55 hex (Note 2)
Input Current ±10 µAPower-down mode
Input Capacitance 30 pFCode = FF hex (Note 3)
Channel-to-Channel Isolation
(MAX519) -60(Note 4)
MAX51 _M, REF_ = VDD
(MAX517, MAX519), code = FF hex,
0µA to 500µA
2.0
AC Feedthrough -70
dB
(Note 5)
MAX51 _C/E, REF_ = VDD
(MAX517, MAX519), code = FF hex,
0µA to 500µA
Full-Scale Output Voltage 0V
DD V
Output Load Regulation
0.25OUT_ = 4V, 0mA to 2.5mA
6To 1/2 LSB, 10kΩand 100pF load (Note 8)
DAC OUTPUTS
DIGITAL INPUTS SCL, SDA
DIGITAL INPUTS AD0, AD1, AD2, AD3
DIGITAL OUTPUT SDA (Note 7)
DYNAMIC PERFORMANCE
REFERENCE INPUTS (MAX517, MAX519)
dB
Input Low Voltage V
mA
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
4 _______________________________________________________________________________________
Note 1: For the MAX518 (full-scale = VDD) the last three codes are excluded from the TUE and DNL specifications, due to the limited
output swing when loaded with 10kΩto GND.
Note 2: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 3: Input capacitance is code dependent. The highest input capacitance occurs at code FF hex.
Note 4: VREF_ = 4VP-P, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
code of all other DACs to 00 hex.
Note 5: VREF_ = 4Vp-p, 10kHz, DAC code = 00 hex.
Note 6: Guaranteed by design.
Note 7: I2C compatible mode. RPULLUP = 1.7kΩ.
Note 8: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
Note 9: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 10: Cb = total capacitance of one bus line in pF. tRand tFmeasured between 0.3VDD and 0.7VDD.
Note 11: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Hold Time, (Repeated) Start Condition tHD, STA 0.6 µs
Low Period of the SCL Clock tLOW 1.3 µs
High Period of the SCL Clock tHIGH 0.6
PARAMETER SYMBOL MIN TYP MAX UNITS
Serial Clock Frequency fSCL 0400kHz
Bus Free Time Between a STOP and a
START Condition tBUF 1.3 µs
CONDITIONS
µs
Setup Time for a Repeated START Condition tSU, STA 0.6 µs
Data Hold Time tHD, DAT 0 0.9 µs
Data Setup Time tSU, DAT 100
(Note 9)
ns
Fall Time of SDA Transmitting tF20 + 0.1Cb 250 ns
Setup Time for STOP Condition tSU, STO 0.6 µs
Capacitive Load for Each Bus Line Cb 400
ISINK ≤6mA (Notes 7, 10)
pF
Rise Time of Both SDA and SCL Signals, Receiving tR20 + 0.1Cb 300 ns
Fall Time of Both SDA and SCL Signals, Receiving tF20 + 0.1Cb 300
(Note 10)
(Note 10) ns
Pulse Width of Spike Suppressed tSP 050(Notes 6, 11) ns
TIMING CHARACTERISTICS
(VDD = 5V ±10%, TA= TMIN to TMAX, unless otherwise noted. Typical values are TA= +25°C.)
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±10%, VREF_ = 4V (MAX517, MAX519), RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.
Typical values are TA= +25°C.)
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
Digital-Analog Glitch Impulse 12Code 128 to 127 nV-s
Signal to Noise + Distortion
Ratio (MAX517, MAX519) SINAD 87
VREF_ = 4Vp-p at 1kHz, VDD = 5V,
Code = FF hex dB
Multiplying Bandwidth
(MAX517, MAX519) 1MHz
Wideband Amplifier Noise 60 µVRMS
Supply Voltage VDD 4.5 5.5 V
1.5 3.0
MAX517E/M
MAX517C
2.5 5
1.5 3.5
VREF_ = 4Vp-p, 3dB bandwidth
Supply Current
Normal mode, output(s)
unloaded, all digital inputs
at 0V or VDD
2.5 6
MAX518C, MAX519C
MAX518E/M, MAX519E/M
IDD
Power-down mode 420µA
POWER REQUIREMENTS
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 5
10
0
0 0.5 1.5 2.5 3.0 3.5 4.0
FULL-SCALE ERROR vs. SOURCE CURRENT
(VREF = VDD)
2
8
MAX517-01
OUTPUT SOURCE CURRENT (mA)
FULL-SCALE ERROR (LSB)
1.0 2.0
6
4
VDD = VREF = 5V
DAC CODE = FF HEX
LOAD TO AGND
10
0
0 0.5 2.0
ZERO-CODE ERROR
vs. SINK CURRENT
2
8
MAX517-02
OUTPUT SINK CURRENT (mA)
ZERO-CODE ERROR (LSB)
1.0 1.5
6
4
VDD = VREF = 5V
DAC CODE = 00 HEX
LOAD to VDD
3.0
0
-55 -15 5-35 65 125
MAX517/MAX519 SUPPLY CURRENT
vs. TEMPERATURE
0.5
2.0
2.5
MAX517-03
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
4525 85 105
1.5
1.0
VDD = 5.5V
REF_ INPUTS = 0.6V
ALL DIGITAL INPUTS to VDD
MAX519, DAC CODE = FF HEX
MAX517, MAX519
DAC CODE = 00 HEX
MAX517, DAC CODE = FF HEX
3.0
3.5
0
-55 -35 -15 56545 125105
MAX518 SUPPLY CURRENT
vs. TEMPERATURE
0.5
2.0
2.5
MAX517-04
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
25 85
1.5
1.0
VDD = 5.5V
AD0, AD1 = VDD
DAC CODE = FF HEX
DAC CODE = 1B HEX
DAC CODE = 00 HEX
6
0
-55 -15-35 45 65 125
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
1
4
5
MAX517-07
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (µA)
255 85 105
3
2
VDD = 5.5V
ALL DIGITAL INPUTS to VDD
MAX518 SUPPLY CURRENT
vs. DAC CODE
MAX517-05
DAC CODE (DECIMAL)
SUPPLY CURRENT (mA)
VDD = 5.5V
BOTH DACS SET
0
0
0.5
1.0
1.5
2.0
2.5
3.0
32 64 96 128 160 192 224 256
2.5
0
010.5 32.5 54.5
MAX517/MAX519 SUPPLY CURRENT
vs. REFERENCE VOLTAGE
0.5
1.5
2.0
MAX517-08
REFERENCE VOLTAGE (V)
SUPPLY CURRENT (mA)
21.5 43.5
1.0
VDD = 5V
DAC CODE(S) FF HEX
MAX519
MAX517
0
1k 100k10k 1M 10M
MAX517/MAX519 REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
-16
MAX517-09
FREQUENCY (Hz)
RELATIVE OUTPUT (dB)
-12
-8
-4
VDD = 5V
VREF = SINE WAVE
CENTERED AT 2.5V
4VP-P SINE
2VP-P SINE
1VP-P SINE
0.5VP-P SINE
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
OUT0 LOADED WITH 10kΩ II 100pF
REF0 = 4V (MAX517/MAX519)
DAC CODE = 00 HEX to FF HEX
1µs/div
POSITIVE FULL-SCALE STEP RESPONSE
OUT0
1V/div
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
6 _______________________________________________________________________________________
A = REF0, 1V/div (4VP-P)
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 10kHz to 1MHz
DAC CODE = 00 HEX
MAX517/MAX519
REFERENCE FEEDTHROUGH AT 100kHz
B
A
______________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
A = SCL, 400kHz, 5V/div
B = OUT0, 5mV/div
DAC CODE = 7F HEX
REF0 = 5V (MAX517/MAX519)
CLOCK FEEDTHROUGH
B
A
A = REF0, 1V/div (4VP-P)
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 100Hz to 10kHz
DAC CODE = 00 HEX
MAX517/MAX519
REFERENCE FEEDTHROUGH AT 1kHz
B
A
A = REF0, 1V/div (4VP-P)
B = OUT0, 50µV/div, UNLOADED
FILTER PASSBAND = 1kHz to 100kHz
DAC CODE = 00 HEX
MAX517/MAX519
REFERENCE FEEDTHROUGH AT 10kHz
B
A
OUT0 LOADED WITH 10kΩ II 100pF
REF0 = 4V (MAX517/MAX519)
DAC CODE = FF HEX to 00 HEX
1µs/div
NEGATIVE FULL-SCALE STEP RESPONSE
OUT0
1V/div
REF0 = 5V (MAX517/MAX519)
DAC CODE = 80 HEX to 7F HEX
500ns/div
WORST-CASE 1LSB STEP CHANGE
OUT0
20mV/div
AC COUPLED
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 7
Figure 1. MAX517/MAX519 Functional Diagram
_______________Detailed Description
Serial Interface
The MAX517/MAX518/MAX519 use a simple 2-wire
serial interface requiring only two I/O lines (2-wire bus)
of a standard microprocessor (µP) port. Figure 2 shows
the timing diagram for signals on the 2-wire bus.
Figure 3 shows a typical application. The 2-wire bus can
have several devices (in addition to the MAX517/
MAX518/MAX519) attached. The two bus lines (SDA and
SCL) must be high when the bus is not in use. When in
use, the port bits are toggled to generate the appropriate
signals for SDA and SCL. External pull-up resistors are
not required on these lines. The MAX517/MAX518/
MAX519 can be used in applications where pull-up resis-
tors are required (such as in I2C systems) to maintain
compatibility with existing circuitry.
The MAX517/MAX518/MAX519 are receive-only devices
and must be controlled by a bus master device. They
operate at SCL rates up to 400kHz. A master device
sends information to the devices by transmitting their
address over the bus and then transmitting the desired
information. Each transmission consists of a START
condition, the MAX517/MAX518/MAX519’s programm-
able slave-address, one or more command-byte/out-
put-byte pairs (or a command byte alone, if it is the last
byte in the transmission), and finally, a STOP condition
(Figure 4).
______________________________________________________________Pin Description
PIN
MAX517 MAX518 MAX519 NAME FUNCTION
1 1 1 OUT0 DAC0 Voltage Output
2 2 4 GND Ground
— — 5 AD3 Address Input 3; sets IC’s slave address
3 3 6 SCL Serial Clock Input
4 4 8 SDA Serial Data Input
— — 9 AD2 Address Input 2; sets IC’s slave address
5 5 10 AD1 Address Input 1; sets IC’s slave address
6 6 11 AD0 Address Input 0; sets IC’s slave address
7 7 12 VDD Power Supply, +5V; used as reference for MAX518
— — 13 REF1 Reference Voltage Input for DAC1
8 — 15 REF0 Reference Voltage Input for DAC0
— 8 16 OUT1 DAC1 Voltage Output
— — 2, 3, 7, 14 N.C. No Connect—not internally connected.
INPUT
LATCH 0 OUTPUT
LATCH 0
START/STOP
DETECTOR
DAC0
INPUT
LATCH 1
8-BIT
SHIFT
REGISTER
OUT0
REF0 (REF1)
(OUT1)
MAX517/MAX519
DECODE
ADDRESS
COMPARATOR
DAC1
OUTPUT
LATCH 1
VDD
SCL
SDA
AD0 (AD2)
AD1 (AD3)
GND
MAX519 ONLY
( ) ARE FOR MAX519
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
8 _______________________________________________________________________________________
The address byte and pairs of command and output
bytes are transmitted between the START and STOP con-
ditions. The SDA state is allowed to change only while
SCL is low, with the exception of START and STOP condi-
tions. SDA’s state is sampled, and therefore must remain
stable while SCL is high. Data is transmitted in 8-bit
bytes. Nine clock cycles are required to transfer the data
bits to the MAX517/MAX518/MAX519. Set SDA low dur-
ing the 9th clock cycle as the MAX517/MAX518/MAX519
pull SDA low during this time. RC(see Figure 3) limits the
current that flows during this time if SDA stays high for
short periods of time.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high (Figure 5). When the mas-
ter has finished communicating with the slave, it issues
a STOP condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another
transmission.
The Slave Address
The MAX517/MAX518/MAX519 each have a 7-bit long
slave address (Figure 6). The first three bits (MSBs) of
the slave address have been factory programmed and
are always 010. In addition, the MAX517 and MAX518
have the next two bits factory programmed to 1s. The
logic state of the address inputs (AD0 and AD1 on the
MAX517/MAX518; AD0, AD1, AD2, and AD3 on the
MAX519) determine the LSB bits of the 7-bit slave
address. These input pins may be connected to VDD or
DGND, or they may be actively driven by TTL or CMOS
logic levels. The MAX517/MAX518 have four possible
slave addresses and therefore a maximum of four of
MAX518
SDA SCL
µC
SDA
SCL
+5V
AD1
AD0
DUAL
DAC
MAX519
AD0
SDA
REF1
REF0
RC
1kΩSCL
+4V
+1V
AD2
AD1
DUAL
DAC
SDA
SCL
AD1
AD0
SINGLE
DAC
MAX517
AD3
OUT0 OFFSET ADJUSTMENT
OUT1 GAIN ADJUSTMENT
OUT0 BRIGHTNESS ADJUSTMENT
OUT1 CONTRAST ADJUSTMENT
REF0 +2.5V
OUT0 THRESHOLD ADJUSTMENT
Figure 3. MAX517/MAX518/MAX519 Application Circuit
SCL
SDA
tLOW
tHIGH
tF
tR
tHD, STA
tHD, DAT
tHD, STA
tSU, DAT tSU, STA
tBUF
tSU, STO
START CONDITIONSTOP CONDITIONREPEATED START CONDITIONSTART CONDITION
Figure 2. Two-Wire Serial Interface Timing Diagram
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
_______________________________________________________________________________________ 9
these devices may share the bus. The MAX519 has 16
possible slave addresses. The eighth bit (LSB) in the
slave address byte should be low when writing to the
MAX517/MAX518/MAX519.
The MAX517/MAX518/MAX519 monitor the bus continu-
ously, waiting for a START condition followed by their
slave address. When a device recognizes its slave
address, it is ready to accept data.
The Command Byte and Output Byte
A command byte follows the slave address. Figure 7
shows the format for the command byte. A command
byte is usually followed by an output byte unless it is
the last byte in the transmission. If it is the last byte, all
bits except PD (power-down) and RST (reset) are
ignored. If an output byte follows the command byte,
A0 of the command byte indicates the digital address
of the DAC whose input data latch receives the digital
output data. Set this bit to 0 when writing to the
MAX517. The data is transferred to the DAC’s output
latch during the STOP condition following the transmis-
sion. This allows both DACs of the MAX518/MAX519 to
be updated simultaneously (Figure 8).
Setting the PD bit high powers down the MAX517/
MAX518/MAX519 following a STOP condition (Figure
9a). If a command byte with PD set high is followed by
an output byte, the addressed DAC’s input latch will be
updated and the data will be transferred to the DAC’s
output latch following the STOP condition (Figure 9b).
SCL
SDA
00 1 or
AD3
1 or
AD2
10AD1 AD0
LSB
ACK
SLAVE ADDRESS
Figure 6. Address Byte
SLAVE ADDRESS BITS AD0, AD1, AD2, AND AD3 CORRESPOND TO THE LOGIC
STATE OF THE ADDRESS INPUT PINS.
LSBMSB
SDA
SCL
R2 R1 R0 RST PD
XX
A0/0 ACK
Figure 7. Command Byte
R2, R1, R0: RESERVED BITS. SET TO 0.
RST: RESET BIT, SET TO 1 TO RESET ALL DAC REGISTERS.
PD: POWER-DOWN BIT. SET TO 1 TO PLACE THE DEVICE IN THE 4µA SHUTDOWN
MODE. SET TO 0 TO RETURN TO THE NORMAL OPERATIONAL STATE.
A0: ADDRESS BIT. DETERMINES WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS
OF DATA IN THE NEXT BYTE. SET TO 0 FOR MAX517.
ACK: ACKNOWLEDGE BIT. THE MAX517/MAX518/MAX519 PULLS SDA LOW DURING
THE 9TH CLOCK PULSE.
X: DON’T CARE.
START CONDITION STOP CONDITION
OUTPUT BYTECOMMAND BYTESLAVE ADDRESS BYTE
SCL
SDA
MSB MSB MSBLSB LSB LSBACK ACK ACK
Figure 4. A Complete Serial Transmission
SCL
SDA
START CONDITION STOP CONDITION
Figure 5. All communications begin with a START condition and
end with a STOP condition, both generated by a bus master.
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
10 ______________________________________________________________________________________
( )
SDA
0
START
CONDITION
ADDRESS BYTE ACK
10
1
or
AD3
1
or
AD2AD1 AD0 0 0000000000 0
111
11111
STOP
CONDITION
COMMAND BYTE
(ADDRESSING DAC0)
ACK OUTPUT BYTE
(FULL SCALE)
ACK
DAC OUTPUT CHANGES HERE:
DAC0 GOES TO FULL SCALE.
DAC0 INPUT LATCH
SET TO FULL SCALE
( )
Figure 8a. Setting One DAC Output (MAX517/MAX518/MAX519)
( )
SDA
SDA
0
START
CONDITION
ADDRESS BYTE ACK
ACK
10
1
or
AD3
1
or
AD2AD1 AD0 0 0000000000
11 1111110
0000000001
111
11111
STOP
CONDITION
OUTPUT BYTE
(FULL SCALE)
COMMAND BYTE
(ADDRESSING DAC0)
ACK OUTPUT BYTE
(FULL SCALE)
ACK COMMAND BYTE
(ADDRESSING DAC1)
ACK
DAC OUTPUTS CHANGE HERE:
DAC0 AND DAC1 GO TO FULL SCALE.
DAC0 INPUT LATCH
SET TO FULL SCALE
( )
( )
DAC1 INPUT LATCH
SET TO FULL SCALE
Figure 8b. Setting Both DAC Outputs (MAX518/MAX519)
SDA
0
START
CONDITION
ADDRESS BYTE ACK
10
1
or
AD3
1
or
AD2 AD1 AD0 0 0 000001
(PD)
(PD)
STOP
CONDITION
COMMAND BYTE ACK
DEVICE ENTERS
POWER-DOWN STATE
( )
SDA
0
START
CONDITION
ADDRESS BYTE ACK
10
1
or
AD3
1
or
AD2 AD1AD0 0 0 0 0
00001 0 1111
1111
STOP
CONDITION
COMMAND BYTE
(ADDRESSING DAC0)
ACK OUTPUT BYTE
(FULL SCALE)
ACK
(a)
(b)
DEVICE ENTERS POWER-DOWN STATE.
DAC0 OUTPUT LATCH SET TO FULL SCALE.
NOTE: X = DON'T CARE
DAC0 INPUT LATCH
SET TO FULL SCALE.
X X X
X X
( )( )
Figure 9. Entering the Power-Down State
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
______________________________________________________________________________________ 11
Furthermore if the transmission’s last command byte
has PD high, the output latches are updated, but volt-
age outputs will not reflect the newly entered data
because the DAC enters power-down mode when the
STOP condition is detected. When in power-down, the
DAC outputs float. In this mode, the supply current is a
maximum of 20µA. A command byte with the PD bit low
returns the MAX517/MAX518/MAX519 to normal opera-
tion following a STOP condition, with the voltage out-
puts reflecting the output-latch contents (Figures 10a
and 10b). Because each subsequent command byte
overwrites the previous PD bit, only the last command
byte of a transmission affects the power-down state.
Setting the RST bit high clears the DAC input latches.
The DAC outputs remain unchanged until a STOP con-
dition is detected (Figure 11a). If a reset is issued, the
following output byte is ignored. Subsequent pairs of
command/output bytes overwrite the input latches
(Figure 11b).
All changes made during a transmission affect the
MAX517/MAX518/MAX519’s outputs only when the
transmission ends and a STOP has been recognized.
The R0, R1, and R2 bits are reserved and must be set
to zero.
I2C Compatibility
The MAX517/MAX518/MAX519 are fully compatible
with existing I2C systems. SCL and SDA are high-
impedance inputs; SDA has an open drain that pulls
the data line low during the 9th clock pulse. Figure 12
shows a typical I2C application.
( ) ( )
( )
SDA
0
START
CONDITION
ADDRESS BYTE ACK
10
1
or
AD3
1
or
AD2 AD1AD000 00010 0
(RST)
(RST)
STOP
CONDITION
COMMAND BYTE ACK
ALL OUTPUTS
SET TO 0.
( )
ALL INPUT LATCHES
SET TO 0.
ALL INPUT LATCHES
SET TO 0.
SDA
0
START
CONDITION
ADDRESS BYTE ACK
10
1
or
AD3
1
or
AD2 AD1AD00000010 0 0
STOP
CONDITION
COMMAND BYTE ACK "DUMMY"
OUTPUT BYTE
ACK
(a)
(b)
DAC OUTPUTS SET TO 0 UNLESS
CHANGED BY ADDITIONAL COMMAND
BYTE/OUTPUT BYTE PAIRS.
NOTE: X = DON'T CARE
ADDITIONAL
COMMAND BYTE/
OUTPUT BYTE PAIRS
X X X
X X X X X X X X X X X
Figure 11. Resetting DAC Outputs
( )
SDA
0
START
CONDITION
ADDRESS BYTE ACK
10
1
or
AD3
1
or
AD2 AD1AD0 0 0 000000
(PD)
(PD)
STOP
CONDITION
COMMAND BYTE ACK
DEVICE RETURNS TO
NORMAL OPERATION
( )
DAC0 INPUT
LATCH SET TO 0.
SDA
0
START
CONDITION
ADDRESS BYTE ACK
10
1
or
AD3
1
or
AD2AD1 AD0 0 00 0000 0
000 0000000
STOP
CONDITION
COMMAND BYTE
(ADDRESSING DAC0)
ACK OUTPUT BYTE
(SET TO 0)
ACK
(a)
(b)
DEVICE RETURNS TO NORMAL OPERATION.
DAC0 SET TO 0.
NOTE: X = DON'T CARE
X X X
X X
( )
Figure 10. Returning to Normal Operation from Power-Down
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
12 ______________________________________________________________________________________
Additional START Conditions
It is possible to interrupt a transmission to a device with
a new START (repeated start) condition (perhaps
addressing another device), which leaves the input
latches with data that has not been transferred to the
output latches (Figure 13). Only the currently addressed
device will recognize a STOP condition and transfer
data to its output latches. If the device is left with data in
its input latches, the data can be transferred to the out-
put latches the next time the device is addressed, as
long as it receives at least one command byte and a
STOP condition.
Early STOP Conditions
The addressed device recognizes a STOP condition at
any point in a transmission. If the STOP occurs during a
command byte, all previous uninterrupted command
and output byte pairs are accepted, the interrupted
command byte is ignored, and the transmission ends
(Figure 14a). If the STOP occurs during an output byte,
all previous uninterrupted command and output byte
pairs are accepted, the final command byte
’
s PD and
RST bits are accepted, the interrupted output byte is
ignored, and the transmission ends (Figure 14b).
Analog Section
DAC Operation
The MAX518 and MAX519 contain two matched volt-
age-output DACs. The MAX517 contains a single DAC.
The DACs are inverted R-2R ladder networks that con-
vert 8-bit digital words into equivalent analog output
voltages in proportion to the applied reference volt-
ages. The MAX518 has both DAC’s reference inputs
connected to VDD. Figure 15 shows a simplified dia-
gram of one DAC.
MAX517/MAX519 Reference Inputs
The MAX517 and MAX519 can be used for multiplying
applications. The reference accepts a 0V to VDD volt-
( )
( )( )
SDA
0
START
CONDITION
ADDRESS BYTE
(DEVICE 0)
ACK
10110000 0 0
00000 000 0101101001
REPEATED START
CONDITION
STOP
CONDITION
COMMAND BYTE
ADDRESSING DAC0
COMMAND BYTE
(ADDRESSING DAC0)
ACK
OUTPUT BYTE
(FULL SCALE)
ACK
ADDRESS BYTE
(DEVICE 1)
ACK
DEVICE 0's
DAC0 INPUT LATCH
SET TO FULL SCALE.
DEVICE 1's DAC0
INPUT LATCH SET
TO FULL SCALE.
SDA
ACK ACK
OUTPUT BYTE
(FULL SCALE)
ONLY DEVICE 1's DAC0 OUTPUT LATCH SET TO FULL
SCALE. DEVICE 0's OUTPUT LATCH UNCHANGED.
1111 111
0000 00 00 0011111 111
Figure 13. Repeated START Conditions
MAX518
SDA SCL
µC
SDA
SCL
E2 PROM
XICOR
X24C04
SDA
SCL
AD1
AD0
DUAL
DAC
SDA
SCL
AD1
AD0
SINGLE
DAC
+5V
MAX517
OUT0
OUT1
OUT0
Figure 12. MAX517/MAX518/MAX519 Used in a Typical I2C
Application Circuit
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
______________________________________________________________________________________ 13
age, both DC and AC signals. The voltage at each REF
input sets the full-scale output voltage for its respective
DAC. The reference voltage must be positive. The
DAC’s input impedance is code dependent, with the
lowest value occurring when the input code is 55 hex or
0101 0101, and the maximum value occurring when the
input code is 00 hex. Since the REF input resistance
(RIN) is code dependent, it must be driven by a circuit
with low output impedance (no more than RIN ÷ 2000)
to maintain output linearity. The REF input capacitance
is also code dependent, with the maximum value
occurring at code FF hex (typically 30pF). The output
voltage for any DAC can be represented by a digitally
programmable voltage source as: VOUT = (N x VREF) /
256, where N is the numerical value of the DAC’s binary
input code.
Output Buffer Amplifiers
The DAC voltage outputs are internally buffered preci-
sion unity-gain followers that slew up to 1V/µs. The out-
puts can swing from 0V to VDD. With a 0V to 4V (or 4V
to 0V) output transition, the amplifier outputs typically
settle to 1/2LSB in 6µs when loaded with 10kΩin paral-
lel with 100pF. The buffer amplifiers are stable with any
combination of resistive loads ≥2kΩand capacitive
loads ≤300pF.
The MAX517/MAX518/MAX519 are designed for unipo-
lar-output, single-quadrant multiplication where the out-
put voltages and the reference inputs are positive with
respect to AGND. Table 1 shows the unipolar code.
Table 1. Unipolar Code Table
2R
RRR
2R 2R 2R 2R 2R
D0 D5 D6 D7
REF_*
GND
SHOWN FOR ALL 1s ON DAC
OUT_
*REF = VDD FOR THE MAX518
Figure 15. DAC Simplified Circuit Diagram
( )
SDA
0
START
CONDITION
ADDRESS BYTE ACK
10
1
or
AD3
1
or
AD2 AD1AD0 0 0 0 0 0011
(RST) (PD)
(PD)
EARLY
STOP CONDITION
INTERRUPTED
COMMAND BYTE MAX517/MAX518/MAX519's
STATE REMAINS UNCHANGED.
( )
SDA
0
START
CONDITION
ADDRESS BYTE ACK
10
1
or
AD3
1
or
AD2 AD1AD000000 000011100RST 1
COMMAND BYTE
(POWER DOWN)
ACK INTERRUPTED
OUTPUT BYTE
(a)
(b)
MAX517/MAX518/MAX519
POWER DOWN; INPUT LATCH
UNCHANGED IF RST = 0,
DAC OUTPUT(S) RESET IF RST = 1.
EARLY
STOP CONDITION
X X
Figure 14. Early STOP Conditions
DAC CONTENTS ANALOG OUTPUT
11111111 255
+ VREF (———)
256
10000001 129
+ VREF (———)
256
10000000 128 VREF
+ VREF (———)= ——
256 2
01111111 127
+ VREF (———)
256
00000001 1
+ VREF (———)
256
00000000 0V
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
14 ______________________________________________________________________________________
__________Applications Information
Power-Supply Bypassing and
Ground Management
Bypass VDD with a 0.1µF capacitor, located as close to
VDD and GND as possible. Careful PC board layout
minimizes crosstalk among DAC outputs, reference
inputs, and digital inputs. Figure 16 shows the suggest-
ed PC board layout to minimize crosstalk.
When using the MAX518 (or the MAX517/MAX519 with
VDD as the reference), you may want to add a noise fil-
ter to the VDD supply (Figure 17) or to the reference
input(s) (Figure 18), especially in noisy environments.
The reference input’s bandwidth exceeds 1MHz for AC
signals, so disturbances on the reference input can
easily affect the DAC output(s).
The maximum input current for a single reference input
is VREF/16kΩ= IREF (max). In Figure 17, choose RFso
that changes in the reference input current will have lit-
tle effect on the reference voltage. For example, with RF
= 6Ω, the maximum output error due to RFis given by:
6Ωx IREF (max) = 1.9mV or 0.1LSB
In Figure 18, there is a voltage drop across RFthat
adds to the TUE. This voltage drop is due to the sum of
the reference input current (VREF/16kΩmaximum), sup-
ply current (6mA maximum), and the amplifier output
current (VREF/RLOAD). Choose RFto limit this voltage
drop to an acceptable value. For example, with a 10kΩ
load, you can limit the error due to RFto 0.5LSB
(9.8mV) by selecting RFso that:
RF= VRF / IRF≤9.8mV / (5V / 16kΩ+ 6mA +
5V / 10kΩ)
RF≤1.4Ω
OUT1
REF0
N.C.
REF1
OUT0
N.C.
N.C.
GND
SYSTEM GND
Figure 16. PC Board Layout for Minimizing MAX519 Crosstalk
(bottom view)
Figure 17. Reference Filter When Using VDD as a Reference
MAX518
RF
CF0.1µF
VDD
+5V
MAX517
MAX519
REF_
RF
CF
0.1µF
VDD
+5V
Figure 18. VDD Filter When Using VDD as a Reference
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
______________________________________________________________________________________ 15
__Ordering Information (continued)
*Dice are specified at TA= +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.
MAX517BMJA -55°C to +125°C 8 CERDIP** 1.5
MAX517BEPA -40°C to +85°C 8 Plastic DIP 1.5
MAX517AEPA -40°C to +85°C 8 Plastic DIP 1
MAX518ACPA 0°C to +70°C 8 Plastic DIP 1
1.516 CERDIP**-55°C to +125°C
1.516 Narrow SO-40°C to +85°CMAX519BESE
116 Narrow SO-40°C to +85°CMAX519AESE
1.516 Plastic DIP-40°C to +85°CMAX519BEPE
116 Plastic DIP-40°C to +85°CMAX519AEPE
1.5Dice*0°C to +70°CMAX519BC/D
1.516 Narrow SO0°C to +70°CMAX519BCSE
116 Narrow SO0°C to +70°CMAX519ACSE
1.516 Plastic DIP0°C to +70°CMAX519BCPE
116 Plastic DIP0°C to +70°C
MAX519ACPE
1.58 CERDIP**-55°C to +125°CMAX518BMJA
1.58 SO-40°C to +85°CMAX518BESA
18 SO-40°C to +85°CMAX518AESA
PART TEMP RANGE PIN-PACKAGE TUE
(LSB)
MAX518BCPA
MAX518ACSA 0°C to +70°C
0°C to +70°C 8 Plastic DIP
8 SO
1.5
1
MAX518BCSA
MAX518BC/D
MAX518AEPA -40°C to +85°C
0°C to +70°C
0°C to +70°C 8 SO
Dice*
8 Plastic DIP
1.5
1.5
1
MAX518BEPA -40°C to +85°C 8 Plastic DIP 1.5
MAX519BMJE
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OUT1
REF0
N.C.
REF1
GND
N.C.
N.C.
OUT0
MAX519
VDD
AD0
AD1
AD2
SDA
N.C.
SCL
AD3
DIP/SO
_____Pin Configurations (continued)
MAX517BESA -40°C to +85°C 8 SO 1.5
MAX517AESA -40°C to +85°C 8 SO 1
TOP VIEW
TRANSISTOR COUNT: 1797
SUBSTRATE CONNECTED TO VDD
____________________Chip Topography
REF0
(MAX517/
MAX519)
REF1
(MAX519)
VDD
AD0
OUT0
OUT1
(MAX518/MAX519)
SDA AD2
(MAX519)
AD1
0.135"
(3.429mm)
0.078"
(1.981mm)
AD3
(MAX519)
SCL
GND
PDIPN.EPS
SOICN .EPS
PACKAGE OUTLINE, .150" SOIC
1
1
21-0041 B
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
MAX
0.010
0.069
0.019
0.157
0.010
INCHES
0.150
0.007
E
C
DIM
0.014
0.004
B
A1
MIN
0.053A
0.19
3.80 4.00
0.25
MILLIMETERS
0.10
0.35
1.35
MIN
0.49
0.25
MAX
1.75
0.050
0.016L0.40 1.27
0.3940.386D
D
MINDIM
D
INCHES
MAX
9.80 10.00
MILLIMETERS
MIN MAX
16 AC
0.337 0.344 AB8.758.55 14
0.189 0.197 AA5.004.80 8
N MS012
N
SIDE VIEW
H 0.2440.228 5.80 6.20
e 0.050 BSC 1.27 BSC
C
HE
eBA1
A
D
0-8
L
1
VARIATIONS:
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX517/MAX518/MAX519
2-Wire Serial 8-Bit DACs with
Rail-to-Rail Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
