10-Bit, 170 MSPS, DAC
AD9731
1.0 SCOPE
This specification documents the detail requirements for space qualified product manufactured on
Analog Devices, Inc.'s QML certified line per MIL-PRF-38535 Level V except as modified herein.
The manufacturing flow described in the STANDARD SPACE LEVEL PRODUCTS PROGRAM
brochure is to be considered a part of this specification. http://www.analog.com/aerospace
This data sheet specifically details the space grade version of this product. A more detailed
operational description and a complete data sheet for commercial product grades can be found at
www.analog.com/AD9731
2.0 Part Number. The complete part numbers per Table I of this specification follow:
Part Number Description
AD9731-703D 10-bit, 170 MSPS, DAC
AD9731-713D Radiation tested, 10-bit, 170 MSPS, DAC
AD9731-703F 10-bit, 170 MSPS, DAC
AD9731-713F Radiation tested, 10-bit, 170 MSPS, DAC
2.1 Case Outline.
Letter
D
F
Descriptive designator
1
CDIP2-T28
CDFP3-F28
Case Outline (Lead Finish per MIL-PRF-38535)
28-Lead Ceramic Side Brazed DIP package
28-Lead Ceramic Bottom Brazed Flatpack
¹ See MIL-STD-1835
3.0 Absolute Maximum Ratings. (TA = 25°C, unless otherwise noted)
+VS................................................................................................................................. +6V
-VS................................................................................................................................... -7V
Analog Output...................................................................................................... -VS to +VS
Digital Inputs ....................................................................................................-0.7V to +VS
Analog Output Current ...............................................................................................30 mA
Control Amplifier Input Voltage Range ............................................................... 0V to -4V
Control Amplifier Output Current .......................................................................... ±2.5 mA
Reference Input Voltage Range.............................................................................0V to -VS
Operating Temperature Range................................................................... -55°C to +125°C
Storage Temperature Range....................................................................... -65°C to +150°C
Lead Temperature (Soldering, 10 sec.).....................................................................+300°C
Maximum Junction Temperature (TJ).......................................................................+150°C
ASD0011259 Rev. I
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibilit y is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may One Technology Wa y, P.O. Box 9106, Norwood, MA 02062-9106,
result from its use. Specifications subj ect to chang e without notice. No license U.S.A.
is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of Tel: 781.329.4700 www.analog.com
their respective companies. Fax: 781.326.8703 © 2009 Analog Devices, Inc. All rights reserved.
AD9731
3.1 Thermal Characteristics:
Thermal Resistance, SIDEBRAZED (D) Package
Junction-to-Case (ΘJC) = 12 °C/W Max
Junction-to-Ambient (ΘJA) = 40 °C/W Max
Thermal Resistance, BOTTOMBRAZED (F) Package
Junction-to-Case (ΘJC) = 22 °C/W Max
Junction-to-Ambient (ΘJA) = 66 °C/W Max
4.0 Electrical Table: TABLE I
Parameter
See notes at end of table Symbol Conditions
Note 1 Sub-
group Limit
Min Limit
Max Units
Differential Nonlinearity DNL 1 1 LSB
2, 3 1.5
Integral Nonlinearity INL 1 1 LSB
2, 3 1.5
Zero Scale Offset Error IOS 1 70
μA
2, 3 100
Full Scale Gain Error (Note 2) Ae 1, 2, 3 ±5 % FS
Internal Reference Voltage VREF IREF = -50 μA to 500 μA 1 -1.35 -1.15 V
2, 3 -1.37 -1.13
Input Logic “1” Voltage VIH 1, 2, 3 2 V
Input Logic “0” Voltage VIL 1, 2, 3 0.8
Input Logic “1” Current IIH 1, 2, 3 50
μA
Input Logic “0” Current IIL 1, 2, 3 100
Positive Digital Supply Current +IDIG 1 20 mA
2, 3 22
Negative Digital Supply Current -IDIG 1 42 mA
2, 3 47
Negative Analog Supply Current -IANA 1 53 mA
2, 3 66
NOTES:
1 +VS = +5V, -VS = -5.2V, Clock = 125 MHz, RSET = 1.96 KΩ for 20.4 mA IOUT, VREF =
-1.25V, unless otherwise specified.
2 Measured as an error in ratio of full-scale current to current through RSET (640 μA nominal); ratio
is nominally 32. DAC load is virtual ground.
ASD0011259 Rev. I | Page 2 of 5
AD9731
4.1 Electrical Test Requirements:
Table II
Test Requirements
Interim Electrical Parameters
Final Electrical Parameters
Group A Test Requirements
Group C end-point electrical parameters
Group D end-point electrical parameters
Group E end-point electrical parameters
Subgroups (in accordance
with MIL-PRF-38535,
Table III)
1
1, 2, 3 1/ 2/
1, 2, 3
1 2/
1
1
1/
2/
4.2
PDA applies to Subgroup 1. Deltas excluded from PDA
See table III for delta parameters and limits.
Table III. Burn-in test delta limits.
Table III
TEST
TITLE
ENDPOINT
LIMIT
DELTA
LIMIT UNITS
-IDIG
IANA
+IDIG
IOS
Ae
42
53
20
±70
±5.0
±4.2
±5.3
±2.0
±35
±2.0
mA
mA
mA
μA
%FS
ASD0011259 Rev. I | Page 3 of 5
AD9731
5.0 Package Pin-out:
6.0 Microcircuit Technology Group: The microcircuit is covered by technology group 80.
7.0 Life Test/Burn-In Circuit: Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per
MIL-STD-883 Method 1015 test condition B.
8.0 MIL-STD-38535 QMLV exceptions:
8.1 Full WLA per MIL-STD-883 TM 5007 is not available for this product fabricated in a QMLQ wafer
process facility. SEM Inspection only is available per MIL-STD-883, TM2018.
ASD0011259 Rev. I | Page 4 of 5
AD9731
Rev Description of Change Date
A Initiate June 30, 2000
B Delete output compliance from Table I - guaranteed by design Nov. 28, 2000
C Update paragraph 1.0, added web address Feb. 7, 2002
D Update web address. Mar. 18, 2003
E Delete Burn-In circuit. Aug. 5, 2003
F Add AD9731-703F & AD9731-713F (flatpack version) Oct. 27, 2003
G Clarify SEM vs. WLA availability for QMLQ fab process Sep. 21, 2007
H Update header/footer & add to 1.0 Scope description Feb. 22,2008
I Add descriptive designator to 2.1- Case Outline Aug. 18, 2009
© 2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective
companies.
Printed in the U.S.A. 08/09
ASD0011259 Rev. I | Page 5 of 5
