10-Bit, 170 MSPS, DAC AD9731 1.0 SCOPE This specification documents the detail requirements for space qualified product manufactured on Analog Devices, Inc.'s QML certified line per MIL-PRF-38535 Level V except as modified herein. The manufacturing flow described in the STANDARD SPACE LEVEL PRODUCTS PROGRAM brochure is to be considered a part of this specification. http://www.analog.com/aerospace This data sheet specifically details the space grade version of this product. A more detailed operational description and a complete data sheet for commercial product grades can be found at www.analog.com/AD9731 2.0 2.1 Part Number. The complete part numbers per Table I of this specification follow: Part Number Description AD9731-703D 10-bit, 170 MSPS, DAC AD9731-713D Radiation tested, 10-bit, 170 MSPS, DAC AD9731-703F 10-bit, 170 MSPS, DAC AD9731-713F Radiation tested, 10-bit, 170 MSPS, DAC Case Outline. 1 Letter D F Descriptive designator CDIP2-T28 CDFP3-F28 Case Outline (Lead Finish per MIL-PRF-38535) 28-Lead Ceramic Side Brazed DIP package 28-Lead Ceramic Bottom Brazed Flatpack See MIL-STD-1835 3.0 Absolute Maximum Ratings. (TA = 25C, unless otherwise noted) +VS ................................................................................................................................. +6V -VS ................................................................................................................................... -7V Analog Output...................................................................................................... -VS to +VS Digital Inputs ....................................................................................................-0.7V to +VS Analog Output Current ...............................................................................................30 mA Control Amplifier Input Voltage Range ............................................................... 0V to -4V Control Amplifier Output Current .......................................................................... 2.5 mA Reference Input Voltage Range .............................................................................0V to -VS Operating Temperature Range................................................................... -55C to +125C Storage Temperature Range....................................................................... -65C to +150C Lead Temperature (Soldering, 10 sec.)..................................................................... +300C Maximum Junction Temperature (TJ)....................................................................... +150C ASD0011259 Rev. I Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2009 Analog Devices, Inc. All rights reserved. AD9731 3.1 Thermal Characteristics: Thermal Resistance, SIDEBRAZED (D) Package Junction-to-Case (JC) = 12 C/W Max Junction-to-Ambient (JA) = 40 C/W Max Thermal Resistance, BOTTOMBRAZED (F) Package Junction-to-Case (JC) = 22 C/W Max Junction-to-Ambient (JA) = 66 C/W Max 4.0 Electrical Table: TABLE I Parameter See notes at end of table Differential Nonlinearity Integral Nonlinearity Zero Scale Offset Error Symbol Conditions Note 1 DNL INL IOS Full Scale Gain Error (Note 2) Ae Internal Reference Voltage VREF IREF = -50 A to 500 A Sub group 1 Limit Min Limit Max 1 1.5 1 1 2, 3 1.5 1 70 2, 3 100 1, 2, 3 5 % FS V 1 -1.35 -1.15 2, 3 -1.37 -1.13 2 VIH 1, 2, 3 Input Logic "0" Voltage VIL 1, 2, 3 0.8 Input Logic "1" Current IIH 1, 2, 3 50 Input Logic "0" Current IIL 1, 2, 3 100 Positive Digital Supply Current +IDIG 1 20 2, 3 22 1 42 2, 3 47 1 53 2, 3 66 Negative Analog Supply Current -IDIG -IANA LSB 2, 3 Input Logic "1" Voltage Negative Digital Supply Current Units LSB A V A mA mA mA NOTES: 1 +VS = +5V, -VS = -5.2V, Clock = 125 MHz, RSET = 1.96 K for 20.4 mA IOUT, VREF = -1.25V, unless otherwise specified. 2 Measured as an error in ratio of full-scale current to current through RSET (640 A nominal); ratio is nominally 32. DAC load is virtual ground. ASD0011259 Rev. I | Page 2 of 5 AD9731 4.1 Electrical Test Requirements: Table II Test Requirements 1/ 2/ 4.2 Subgroups (in accordance with MIL-PRF-38535, Table III) Interim Electrical Parameters 1 Final Electrical Parameters 1, 2, 3 1/ 2/ Group A Test Requirements 1, 2, 3 Group C end-point electrical parameters 1 2/ Group D end-point electrical parameters 1 Group E end-point electrical parameters 1 PDA applies to Subgroup 1. Deltas excluded from PDA See table III for delta parameters and limits. Table III. Burn-in test delta limits. TEST TITLE Table III ENDPOINT DELTA LIMIT LIMIT UNITS -IDIG 42 4.2 mA IANA 53 5.3 mA +IDIG 20 2.0 mA IOS 70 35 A Ae 5.0 2.0 %FS ASD0011259 Rev. I | Page 3 of 5 AD9731 5.0 Package Pin-out: 6.0 Microcircuit Technology Group: The microcircuit is covered by technology group 80. 7.0 Life Test/Burn-In Circuit: Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition B. 8.0 MIL-STD-38535 QMLV exceptions: 8.1 Full WLA per MIL-STD-883 TM 5007 is not available for this product fabricated in a QMLQ wafer process facility. SEM Inspection only is available per MIL-STD-883, TM2018. ASD0011259 Rev. I | Page 4 of 5 AD9731 Rev A B C D E F G H I Description of Change Initiate Delete output compliance from Table I - guaranteed by design Update paragraph 1.0, added web address Update web address. Delete Burn-In circuit. Add AD9731-703F & AD9731-713F (flatpack version) Clarify SEM vs. WLA availability for QMLQ fab process Update header/footer & add to 1.0 Scope description Add descriptive designator to 2.1- Case Outline (c) 2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. 08/09 ASD0011259 Rev. I | Page 5 of 5 Date June 30, 2000 Nov. 28, 2000 Feb. 7, 2002 Mar. 18, 2003 Aug. 5, 2003 Oct. 27, 2003 Sep. 21, 2007 Feb. 22,2008 Aug. 18, 2009