General Description
The MAX17030/MAX17036 are 3/2-phase interleaved
Quick-PWM™ step-down VID power-supply controllers
for IMVP-6.5 notebook CPUs. Two integrated drivers and
the option to drive a third phase using an external driver
such as the MAX8791 allow for a flexible 3/2-phase con-
figuration depending on the CPU being supported.
True out-of-phase operation reduces input ripple-current
requirements and output-voltage ripple while easing
component selection and layout difficulties. The Quick-
PWM control provides instantaneous response to fast
load-current steps. Active voltage positioning reduces
power dissipation and bulk output capacitance require-
ments and allows ideal positioning compensation for tan-
talum, polymer, or ceramic bulk output capacitors.
The MAX17030/MAX17036 are intended for bucking
down the battery directly to create the core voltage.
The single-stage conversion method allows this device
to directly step down high-voltage batteries for the
highest possible efficiency.
A slew-rate controller allows controlled transitions
between VID codes. A thermistor-based temperature
sensor provides programmable thermal protection. An
output current monitor provides an analog current out-
put proportional to the sum of the inductor currents,
which in steady state is the same as the current con-
sumed by the CPU.
Applications
IMVP-6.5 SV and XE Core Power Supplies
High-Current Voltage-Positioned Step-Down
Converters
3 to 4 Li+ Cells Battery to CPU Core Supply
Converters
Notebooks/Desktops/Servers
Features
oTriple/Dual-Phase Quick-PWM Controllers
o2 Internal Drivers + 1 External Driver
o±0.5% VOUT Accuracy Over Line, Load, and
Temperature
o7-Bit IMVP-6.5 DAC
oDynamic Phase Selection Optimizes Active/Sleep
Efficiency
oTransient Phase Overlap Reduces Output
Capacitance
oTransient Suppression Feature (MAX17036 Only)
oIntegrated Boost Switches
oActive Voltage Positioning with Adjustable Gain
oAccurate Lossless Current Balance and
Current Limit
oRemote Output and Ground Sense
oAdjustable Output Slew-Rate Control
oPower-Good (IMVPOK), Clock Enable (CLKEN),
and Thermal-Fault (VRHOT) Outputs
oIMVP-6.5 Power Sequencing and Timing
Compliant
oOutput Current Monitor (IMON)
oDrives Large Synchronous Rectifier FETs
o7V to 26V Battery Input Range
oAdjustable Switching Frequency (600kHz max)
oUndervoltage, Overvoltage, and Thermal-Fault
Protection
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
________________________________________________________________
Maxim Integrated Products
1
BST1
LX1
DL1
VDD
DH2
LX2
BST2
VRHOT
DL2
DH1
THRM
IMON
ILIM
TIME
VCC
FB
FBAC
GNDS
CSP3
CSN3
SHDN
TON
DRSKP
PWM3
DPRSLPVR
PSI
CSP2
CSN2
CSP1
D6
D5
D4
D3
D2
D1
D0
PGD_IN
CSN1
PWRGD
MAX17030
MAX17036
THIN QFN
5mm x 5mm
+
TOP VIEW
35
36
34
33
12
11
13
14
12 4 567
27282930 26 24 23 22
3
25
37
38
39
40
32
15
31
16
17
18
19
20
8910
21
CLKEN
Pin Configuration
Ordering Information
19-4577; Rev 1; 8/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX17030GTL+ -40°C to +105°C 40 TQFN-EP*
MAX17036GTL+ -40°C to +105°C 40 TQFN-EP*
+
Denotes a lead-free(Pb)/RoHS-compliant package.
*
EP = Exposed pad.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
(Note 1)
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGD_IN = VPSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ =
1.0000V, FB = FBAC, RFBAC = 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA= 0°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, VDD to GND .....................................................-0.3V to +6V
D0–D6, PGD_IN, PSI, DPRSLPVR to GND ...............-0.3V to +6V
CSP_, CSN_, THRM, ILIM to GND............................-0.3V to +6V
PWRGD, CLKEN, VR_HOT to GND..........................-0.3V to +6V
FB, FBAC, IMON, TIME to GND .................-0.3V to (VCC + 0.3V)
SHDN to GND (Note 2)...........................................-0.3V to +30V
TON to GND ...........................................................-0.3V to +30V
GNDS to GND .......................................................-0.3V to +0.3V
DL1, DL2, PWM3, DRSKP to GND .............-0.3V to (VDD + 0.3V)
BST1, BST2 to GND ...............................................-0.3V to +36V
BST1, BST2 to VDD.................................................-0.3V to +30V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V)
DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V)
Continuous Power Dissipation (40-pin, 5mm x 5mm TQFN)
Up to +70°C ..............................................................1778mW
Derating above +70°C ..........................................22.2mW/°C
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWM CONTROLLER
VCC, VDD 4.5 5.5
Input Voltage Range VIN 7 26
V
DAC codes from
0.8125V to 1.5000V -0.5 +0.5 %
DAC codes from
0.3750V to 0.8000V -7 +7
FB Output Voltage Accuracy VFB
Measured at FB
with respect to
GNDS;
includes load-
regulation error
(Note 3) DAC codes from
0 to 0.3625V -20 +20
mV
Boot Voltage VBOOT 1.094 1.100 1.106 V
Line Regulation Error VCC = 4.5V to 5.5V, VIN = 4.5V to 26V 0.1 %
FB Input Bias Current TA = +25°C -0.1 +0.1 μA
GNDS Input Range -200 +200 mV
GNDS Gain AGNDS VOUT/VGNDS 0.97 1.00 1.03 V/V
GNDS Input Bias Current IGNDS T
A = +25°C -0.5 +0.5 μA
TIME Regulation Voltage VTIME R
TIME = 147k 1.985 2.000 2.015 V
RTIME = 147k (6.08mV/μs nominal) -10 +10
RTIME = 35.7k (25mV/μs nominal) to
178k (5mV/μs nominal) -15 +15
TIME Slew-Rate Accuracy
Soft-start and soft-shutdown:
RTIME = 35.7k (6.25mV/μs nominal) to
178k (1.25mV/μs nominal)
-20 +20
%
Note 1: Absolute Maximum Ratings valid using 20MHz bandwidth limit.
Note 2: SHDN might be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode. Internal
BST switches are disabled as well. Use external BST diodes when SHDN is forced to 12V.
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RTON = 96.75k (600kHz
per phase), 167ns nominal -15 +15
RTON = 200k (300kHz
per phase), 333ns nominal -10 +10
On-Time Accuracy tON
VIN = 10V,
VFB = 1.0V,
measured at
DH1, DH2,
and PWM3
(Note 4) RTON = 303.25k (200kHz
per phase), 500ns nominal -15 +15
%
Minimum Off-Time tOFF(MIN) Measured at DH1, DH2, and PWM3 (Note 4) 300 375 ns
TON Shutdown Input Current ITON,SDN
SHDN = GND, VIN = 26V, VCC = VDD = 0
or 5V, TA = +25°C 0.01 0.1 μA
BIAS CURRENTS
Quiescent Supply Current (VCC) ICC Measured at VCC, VDPRSLPVR = 5V, FB
forced above the regulation point 3.5 7 mA
Quiescent Supply Current (VDD) IDD Measured at VDD, VDPRSLPVR = 0, FB forced
above the regulation point, TA = +25°C 0.02 1 μA
Shutdown Supply Current (VCC) ICC,SDN Measured at VCC,SHDN = GND, TA = +25°C 0.01 1 μA
Shutdown Supply Current (VDD) IDD,SDN Measured at VDD,SHDN = GND, TA = +25°C 0.01 1 μA
FAULT PROTECTION
Skip mode after output reaches the
regulation voltage or PWM mode;
measured at FB with respect to the voltage
target set by the VID code (see Table 4)
250 300 350 mV
Soft-start, soft-shutdown, skip mode, and
output have not reached the regulation
voltage; measured at FB
1.45 1.50 1.55
Output Overvoltage-Protection
Threshold VOVP
Minimum OVP threshold; measured at FB 0.8
V
Output Overvoltage-
Propagation Dela y tOVP FB forced 25mV above trip threshold 10 μs
Output Undervoltage-
Protection Threshold VUVP Measured at FB with respect to the voltage
target set by the VID code (see Table 4) -450 -400 -350 mV
Output Undervoltage-
Propagation Dela y tUVP FB forced 25mV below trip threshold 10 μs
CLKEN Startup Delay and
Boot Time Period tBOOT Measured from the time when FB reaches
the boot target voltage (Note 3) 20 60 100 μs
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGD_IN = VPSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ =
1.0000V, FB = FBAC, RFBAC = 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA= 0°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.)
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGD_IN = VPSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ =
1.0000V, FB = FBAC, RFBAC = 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA= 0°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWRGD Startup Delay Measured at startup from the time when
CLKEN goes low 3 6.5 10 ms
Lower threshold,
falling edge
(undervoltage)
-350 -300 -250
CLKEN and PWRGD Threshold
Measured at FB
with respect to the
voltage target set
by the VID code
(see Table 4), 20mV
hysteresis (typ)
Upper threshold,
rising edge
(overvoltage)
+150 +200 +250
mV
CLKEN and PWRGD Delay FB forced 25mV outside the PWRGD trip
thresholds 10 μs
CLKEN and PWRGD Transition
Blanking Time (VID Transitions) tBLANK Measured from the time when FB reaches
the target voltage (Note 3) 20 μs
CLKEN, PWRGD Output
Low Voltage Low state, ISINK = 3mA 0.4 V
CLKEN, PWRGD Leakage
Current High-Z state, pin forced to 5V, TA = +25°C 1 μA
CSN1 Pulldown Resistance in
UVLO and Shutdown
SHDN = GND, measured after soft-
shutdown completed (DL = low) 8
VCC Undervoltage-Lockout
Threshold VUVLO(VCC) Rising edge, 65mV typical hysteresis,
controller disabled below this level 4.05 4.27 4.48 V
THERMAL PROTECTION
VRHOT Trip Threshold Measured at THRM with respect to VCC;
falling edge, typical hysteresis = 75mV 29 30 31 %
VRHOT Delay tVRHOT THRM forced 25mV below the VRHOT trip
threshold, falling edge 10 μs
VRHOT Output On-Resistance RON(VRHOT)Low state 2 8
VRHOT Leakage Current High-Z state, VRHOT forced to 5V, TA = +25°C 1 μA
THRM Input Leakage ITHRM V
THRM = 0 to 5V, TA = +25°C -0.1 +0.1 μA
Thermal-Shutdown Threshold TSHDN Typical hysteresis = 15°C +160 °C
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR
VTIME - VILIM = 100mV 7 10 13
VTIME - VILIM = 500mV 45 50 55
Current-Limit Threshold Voltage
(Positive) VLIMIT VCSP_ - VCSN_
ILIM = VCC 20 22.5 25
mV
Current-Limit Threshold Voltage
(Negative) Accuracy VLIMIT(NEG) VCSP_ - VCSN_, nominally -125% of VLIMIT -4 +4 mV
Current-Limit Threshold Voltage
(Zero Crossing) VZX VGND - VLX_, VDPRSLPVR = 5V 0 mV
CSP_, CSN_ Common-Mode
Input Range 0 2 V
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGD_IN = VPSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ =
1.0000V, FB = FBAC, RFBAC = 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA= 0°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Phases 2, 3 Disable Threshold Measured at CSP2, CSP3 3 VCC -
1
VCC -
0.4 V
CSP_, CSN_ Input Current ICSP, ICSN TA = +25°C -0.2 +0.2 μA
ILIM Input Current IILIM TA = +25°C -0.1 +0.1 μA
TA = +25°C -0.5 +0.5
Droop Amplifier Offset
(1/N) x (VCSP_ -
VCSN_) at IFBAC = 0;
indicates
summation over all
power-up enabled
phases from 1 to N,
N = 3
TA = 0°C to +85°C -0.75 +0.75
mV/
phase
Droop Amplifier
Transconductance Gm(FBAC)
IFBAC/[(VCSP_ - VCSN_)];
indicates summation over all power-up
enabled phases from 1 to N, N = 3,
VFBAC = VCSN_ = 0.45V to 1.5V
393 400 406 μS
Current-Monitor Offset
(1/N) x (VCSP_ - VCSN_) at IIMON = 0,
indicates summation over all power-up
enabled phases from 1 to N, N = 3
-1.1 +1
mV/
phase
Current-Monitor
Transconductance Gm(IMON)
IIMON/[(VCSP_ - VCSN_)];
indicates summation over all power-up
enabled phases from 1 to N, N = 3,
VCSN_ = 0.45V to 1.5V
1.552 1.6 1.648 mS
GATE DRIVERS
High state (pullup) 0.9 2.5
DH_ Gate-Driver On-Resistance RON(DH) BST_ - LX_ forced
to 5V Low state (pulldown) 0.7 2
High state (pullup) 0.7 2
DL_ Gate-Driver On-Resistance RON(DL) Low state (pulldown) 0.25 0.7
DH_ Gate-Driver Source Current IDH(SOURCE) DH_ forced to 2.5V,
BST_ - LX_ forced to 5V 2.2 A
DH_ Gate-Driver Sink Current IDH(SINK) DH_ forced to 2.5V,
BST_ - LX_ forced to 5V 2.7 A
DL_ Gate-Driver Source Current IDL(SOURCE) DL_ forced to 2.5V 2.7 A
DL_ Gate-Driver Sink Current IDL(SINK) DL_ forced to 2.5V 8 A
DL_ falling, CDL_ = 3nF 20
DL_ Transition Time DL rising, CDL_ = 3nF 20 ns
DH_ falling, CDH_ = 3nF 20
DH_ Transition Time DH_ rising, CDH_ = 3nF 20 ns
Internal BST_ Switch
On-Resistance RON(BST) IBST_ = 10mA 10 20
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGD_IN = VPSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ =
1.0000V, FB = FBAC, RFBAC = 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA= 0°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWM3, DRSKP OUTPUTS
PWM3, DRSKP Output
High Voltages ISOURCE = 3mA VDD -
0.4V V
PWM3, DRSKP Output
Low Voltages ISINK = 3mA 0.4 V
LOGIC AND I/O
Logic-Input High Voltage VIH SHDN, PGD_IN 2.3 V
Logic-Input Low Voltage VIL SHDN, PGD_IN 1.0 V
Low-Voltage Logic-Input
High Voltage VIHLV PSI, D0–D6, DPRSLPVR 0.67 V
Low-Voltage Logic-Input
Low Voltage VILLV PSI, D0–D6, DPRSLPVR 0.33 V
Logic Input Current TA = +25°C; SHDN, DPRSLPVR, PGD_IN,
PSI, D0–D6 = 0 or 5V -1 +1 μA
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGD_IN = VPSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ =
1.0000V, FB = FBAC, RFBAC = 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA= -40oC to +105°C, unless otherwise noted.)
(Note 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWM CONTROLLER
VCC, VDD 4.5 5.5
Input Voltage Range VIN 7 26
V
DAC codes from
0.8125V to 1.5000V -0.75 +0.75 %
DAC codes from
0.3750V to 0.8000V -10 +10
FB Output-Voltage Accuracy VFB
Measured at
FB with
respect to
GNDS,
includes load-
regulation
error (Note 3)
DAC codes from
0 to 0.3625V -25 +25
mV
Boot Voltage VBOOT 1.085 1.115 V
GNDS Input Range -200 +200 mV
GNDS Gain AGNDS VOUT/VGNDS 0.95 1.05 V/V
TIME Regulation Voltage VTIME R
TIME = 147k 1.985 2.015 V
RTIME = 147k (6.08mV/μs nominal) -10 +10
RTIME = 35.7k (25mV/μs nominal) to
178k (5mV/μs nominal) -15 +15
TIME Slew-Rate Accuracy
Soft-start and soft-shutdown:
RTIME = 35.7k (6.25mV/μs nominal) to
178k (1.25mV/μs nominal)
-20 +20
%
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGD_IN = VPSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ =
1.0000V, FB = FBAC, RFBAC = 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA= -40oC to +105°C, unless otherwise noted.)
(Note 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RTON = 96.75k (600kHz
per phase), 167ns nominal -15 +15
RTON = 200k (300kHz
per phase), 333ns nominal -10 +10
On-Time Accuracy tON
VIN = 10V,
VFB = 1.0V,
measured at
DH1, DH2,
and PWM3
(Note 4) RTON = 303.25k (200kHz
per phase), 500ns nominal -15 +15
%
Minimum Off-Time tOFF(MIN) Measured at DH1, DH2, and PWM3 (Note 4) 400 ns
BIAS CURRENTS
Quiescent Supply Current (VCC) ICC Measured at VCC, DPRSLPVR = 5V, FB
forced above the regulation point 7 mA
FAULT PROTECTION
Skip mode after output reaches the
regulation voltage or PWM mode;
measured at FB with respect to the voltage
target set by the VID code (see Table 4)
250 350 mV
Output Overvoltage-Protection
Threshold VOVP
Soft-start, soft-shutdown, skip mode, and
output have not reached the regulation
voltage; measured at FB
1.45 1.55 V
Output Undervoltage-Protection
Threshold VUVP Measured at FB with respect to the voltage
target set by the VID code (see Table 4) -450 -350 mV
CLKEN Startup Delay and Boot
Time Period tBOOT Measured from the time when FB reaches
the boot target voltage (Note 3) 20 100 μs
PWRGD Startup Delay Measured at startup from the time when
CLKEN goes low 3 10 ms
Lower threshold,
falling edge
(undervoltage)
-350 -250
CLKEN and PWRGD Threshold
Measured at FB
with respect to the
voltage target set
by the VID code
(see Table 4),
20mV hysteresis
(typ)
Upper threshold,
rising edge
(overvoltage)
+150 +250
mV
CLKEN, PWRGD Output
Low Voltage Low state, ISINK = 3mA 0.4 V
VCC Undervoltage-Lockout
Threshold VUVLO(VCC) Rising edge, 65mV typical hysteresis,
controller disabled below this level 4.05 4.5 V
THERMAL PROTECTION
VRHOT Trip Threshold Measured at THRM with respect to VCC,
falling edge, typical hysteresis = 75mV 29 31 %
VRHOT Output On-Resistance RON(VRHOT)Low state 8
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
8 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR
VTIME - VILIM = 100mV 7 13
VTIME - VILIM = 500mV 45 55
Current-Limit Threshold Voltage
(Positive) VLIMIT VCSP_ - VCSN_
ILIM = VCC 20 25
mV
Current-Limit Threshold Voltage
(Negative) Accuracy VLIMIT(NEG) VCSP_ - VCSN_, nominally -125% of VLIMIT -4 +4 mV
CSP_, CSN_ Common-Mode
Input Range 0 2 V
Phases 2, 3 Disable Threshold Measured at CSP2, CSP3 3 VCC -
0.4 V
Droop Amplifier Offset
(1/N) x (VCSP_ - VCSN_) at IFBAC = 0;
indicates summation over all power-up
enabled phases from 1 to N, N = 3
-1 +1
mV/
phase
Droop Amplifier
Transconductance Gm(FBAC)
IFBAC/[(VCSP_ - VCSN_)]; indicates
summation over all power-up enabled
phases from 1 to N, N = 3,
VFBAC = VCSN_ = 0.45V to 1.5V
390 407 μS
Current-Monitor Offset
(1/N) x (VCSP_ - VCSN_) at IFBAC = 0;
indicates summation over all power-up
enabled phases from 1 to N, N = 3
-1.5 +1.5
mV/
phase
Current-Monitor
Transconductance Gm(IMON)
IIMON/[(VCSP_ - VCSN_)]; indicates
summation over all power-up enabled phases
from 1 to N, N = 3, VCSN_ = 0.45V to 1.5V
1.536 1.664 mS
GATE DRIVERS
High state (pullup) 2.5
DH_ Gate-Driver On-Resistance RON(DH) BST_ – LX_
forced to 5V Low state (pulldown) 2
High state (pullup) 2
DL_ Gate-Driver On-Resistance RON(DL) Low state (pulldown) 0.7
Internal BST_ Switch
On-Resistance RON(BST) IBST- = 10mA 20
PWM3, DRSKP OUTPUTS
PWM3, DRSKP Output
High Voltages ISOURCE = 3mA VDD -
0.4V V
PWM3, DRSKP Output
Low Voltages ISINK = 3mA 0.4 V
LOGIC AND I/O
Logic-Input High Voltage VIH SHDN, PGD_IN 2.3 V
Logic-Input Low Voltage VIL SHDN, PGD_IN 1.0 V
Low-Voltage Logic-Input
High Voltage VIHLV PSI, D0–D6, DPRSLPVR 0.67 V
Low-Voltage Logic-Input
Low Voltage VILLV PSI, D0–D6, DPRSLPVR 0.33 V
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 10V, VCC = VDD = VSHDN = VPGD_IN = VPSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ =
1.0000V, FB = FBAC, RFBAC = 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA= -40oC to +105°C, unless otherwise noted.)
(Note 5)
Note 3: The equation for the target voltage VTARGET is:
VTARGET = The slew-rate-controlled version of VDAC, where VDAC = 0 for shutdown
VDAC = VBOOT during IMVP-6.5 startup
VDAC = VVID otherwise (the VVID voltages for all possible VID codes are given in Table 4).
In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Note 4: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ pin, with LX_ forced to 0V, BST_
forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-circuit times
might be different due to MOSFET switching speeds.
Note 5: Specifications to -40°C and +105°C are guaranteed by design, not production tested.
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
_______________________________________________________________________________________ 9
EFFICIENCY vs. LOAD CURRENT
(VOUT(HFM) = 0.95V)
MAX17030 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
101
30
40
50
60
70
80
90
100
20
0.1 100
12V
20V
7V
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT(HFM) = 0.95V)
MAX17030 toc02
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
50 6020 30 40
0.85
0.90
0.95
1.00
0.80
010 70
EFFICIENCY vs. LOAD CURRENT
(VOUT(LFM) = 0.875V)
MAX17030 toc03
LOAD CURRENT (A)
EFFICIENCY (%)
101
60
70
80
90
50
0.1 100
12V
20V
7V
SKIP MODE
PWM MODE
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT(LFM) = 0.875V)
MAX17030 toc04
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
15510
0.84
0.85
0.87
0.86
0.88
0.89
0.90
0.83
020
2-PHASE PWM MODE
1-PHASE SKIP MODE
SWITCHING FREQUENCY
vs. LOAD CURRENT
MAX17030 toc05
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)
3010 20
100
50
150
250
200
300
350
400
0
05040
VOUT(HFM) = 0.95V
VOUT(LFM) = 0.875V
DPRSLPVR = VCC
DPRSLPVR = GND
VOUT(HFM) = 0.95V NO-LOAD
SUPPLY CURRENT vs. INPUT VOLTAGE
MAX17030 toc06
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
15912
0.1
1
10
100
1000
0.01
62118
IIN
IIN
ICC + IDD
ICC + IDD
DPRSLPVR = VCC
DPRSLPVR = GND
Typical Operating Characteristics
(Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 0.95V, TA= +25°C, unless otherwise specified.)
ELECTRICAL CHARACTERISTICS (continued)
MAX17030/MAX17036
1/2/3-Phase-Quick-PWM
IMVP-6.5 VID Controllers
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 0.95V, TA= +25°C, unless otherwise specified.)
CURRENT BALANCE
vs. LOAD CURRENT
MAX17030 toc07
LOAD CURRENT (A)
SENSE VOLTAGE (mV)
SENSE VOLTAGE DIFFERENCE (mV)
30 4010 20
5
10
15
20
0
-0.1
0
0.1
0.2
-0.2
0706050
VOUT = 0.95V
VCSP1 - VCSN1
VCSP2 - VCSN2
VCS3 - VCS1
VCS2 - VCS1
VCSP3 -
VCSN3
IIMON
vs. LOAD CURRENT
MAX17030 toc08
∑VCSP - CSN (mV)
IMON (μA)
3010 20
20
40
60
80
100
0
0605040
VOUT = 0.95V
DPRSLPVR = GND
0.8125V OUTPUT
VOLTAGE DISTRIBUTION
MAX17030 toc09
OUTPUT VOLTAGE (V)
SAMPLE PERCENTAGE (%)
0.8085
0.8095
0.8105
0.8115
0.8125
0.8135
0.8145
0.8155
0.8165
0.8175
0.8075
20
10
30
40
50
60
70
0
+85°C
+25°C
SAMPLE SIZE = 100
Gm(FB) TRANSCONDUCTANCE
DISTRIBUTION
MAX17030 toc10
TRANCONDUCTANCE (μs)
SAMPLE PERCENTAGE (%)
392
394
396
398
400
402
404
406
408
410
390
20
10
30
40
50
60
70
0
+85°C
+25°C
SAMPLE SIZE = 100
Gm(IMON) TRANSCONDUCTANCE
DISTRIBUTION
MAX17030 toc11
TRANCONDUCTANCE (μs)
SAMPLE PERCENTAGE (%)
1560
1570
1580
1590
1600
1610
1620
1630
1640
1650
1550
15
5
10
20
25
30
35
40
0
+85°C
+25°C
SAMPLE SIZE = 100
MAX17030/MAX17036
1/2/3-Phase-Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________
11
SOFT-START WAVEFORM
(UP TO CLKEN)
MAX17030 toc12
200μs/div
A. SHDN, 5V/div
B. CLKEN, 10V/div
C. VOUT, 500mV/div
0
0
0
0
0
0
E
D
C
B
A
F
3.3V
0.95V
3.3V
D. ILX1, 10A/div
E. ILX2, 10A/div
F. ILX3, 10A/div
IOUT, 15A
SOFT-START WAVEFORM
(UP TO PWRGD)
MAX17030 toc13
1ms/div
A. SHDN, 5V/div
B. CLKEN, 6.6V/div
C. PWRGD, 10V/div
D. VOUT, 1V/div
0
0
0
0
0
0
0
E
D
C
B
A
F
G
3.3V
0.95V
3.3V
3.3V
E. DL1, 10V/div
F. DL2, 10V/div
G. DL3, 10V/div
IOUT, 15A
SHUTDOWN WAVEFORM
MAX17030 toc14
200μs/div
A. SHDN, 5V/div
B. PWRGD, 10V/div
C. CLKEN, 10V/div
D. VOUT, 500mV/div
0
0
0
0
0
0
0
E
D
C
B
A
F
G
3.3V
0.95V
3.3V
3.3V
E. DL1, 10V/div
F. DL2, 10V/div
G. DL3, 10V/div
LOAD-TRANSIENT RESPONSE
(HFM MODE)
MAX17030 toc15
20μs/div
A. IOUT = 7A - 59A
B. VOUT, 50mV/div
E
D
C
B
A
59A
0.84V
7A
0.935V
C. ILX1, 20A/div
D. ILX2, 20A/div
E. ILX3, 20A/div
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 0.95V, TA= +25°C, unless otherwise specified.)
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
12 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1CSN3
Negative Input of the Output Current Sense of Phase 3. This pin should be connected to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing.
2CSP3
Positive Input of the Output Current Sense of Phase 3. This pin should be connected to the positive
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the
output inductor is utilized for current sensing.
To disable phase 3, connect CSP3 to VCC and CSN3 to GND.
3 THRM
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC
and GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of
VCC) at the desired high temperature.
4 IMON
Current Monitor Output Pin. The output current at this pin is:
IIMON = GM(IMON) x V(CSP_,CSN_)
where GM(IMON) = 1.6mS typical and denotes summation over all enabled phases.
An external resistor RIMON between IMON and GNDS sets the current-monitor output voltage:
VIMON = ILOAD x RSENSE x GM(IMON) x RIMON
where RSENSE is the value of the effective current-sense resistance.
Choose RIMON such that VIMON does not exceed 900mV at the maximum expected load current IMAX.
IMON is high impedance when the MAX17030/MAX17036 are in shutdown.
5 ILIM
Current-Limit Adjust Input. The valley positive current-limit threshold voltages at V(CSP_,CSN_) are
precisely 1/10 the differential voltage V(TIME,ILIM) over a 0.1V to 0.5V range of V(TIME,ILIM). The
valley negative current-limit thresholds are typically -125% of the corresponding valley positive
current-limit thresholds. Connect ILIM to VCC to get the default current-limit threshold setting of
22.5mV typ.
6 TIME
Slew-Rate Adjustment Pin. The total resistance RTIME from TIME to GND sets the internal slew rate:
Slew rate = (12.5mV/μs) x (71.5k/RTIME)
where RTIME is between 35.7k and 178k.
This “normal” slew rate applies to transitions into and out of the low-power pulse-skipping modes
and to the transition from boot mode to VID. The slew rate for startup and for entering shutdown is
always 1/4 of normal. If the VID DAC inputs are clocked, the slew rate for all other VID transitions
is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew
rate defined above.
7 VCC Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1μF minimum.
8 FB
Feedback Voltage Input. The voltage at the FB pin is compared with the slew-rate-controlled target
voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator
(slow, accurate regulation loop). Having sufficient ripple signal at FB that is in phase with the sum
of the inductor currents is essential for cycle-by-cycle stability.
The external connections and compensation at FB depend on the desired DC and transient (AC)
droop values. If DC droop = AC droop, then short FB to FBAC. To disable DC droop, connect FB to the
remote-sensed output voltage through a resistor R and feed forward the FBAC ripple to FB through
capacitor C, where the R x C time constant should be at least 3x the switching period per phase.
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 13
Pin Description (continued)
PIN NAME FUNCTION
9 FBAC
Output of the Voltage-Positioning Transconductance Amplifier. Connect a resistor RFBAC between
FBAC and the positive side of the feedback remote sense to set the transient (AC) droop based on
the stability, load-transient response, and voltage-positioning gain requirements:
RFBAC = RDROOP,AC/[RSENSE x Gm(FBAC)]
where RDROOP,AC is the transient (AC) voltage-positioning slope that provides an acceptable
tradeoff between stability and load-transient response, Gm(FBAC) = 400μS typ, and RSENSE is the
effective current-sense resistance that is used to provide the (CSP_, CSN_) current-sense voltages.
A minimum RDROOP,AC value is required for stability, but if there are no ceramic output capacitors
used, then the minimum requirement applies to RESR + RDROOP,AC, where RESR is the effective
ESR of the output capacitors.
If lossless sensing (inductor DCR sensing) is used, use a thermistor-resistor network to minimize
the temperature dependence of the voltage-positioning slope.
FBAC is high impedance in shutdown.
10 GNDS
Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the load.
GNDS internally connects to a transconductance amplifier that fine tunes the output voltage
compensating for voltage drops from the regulator ground to the load ground.
11 CSN2
Negative Input of the Output Current Sense of Phase 2. This pin should be connected to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing.
12 CSP2
Positive Input of the Output Current Sense of Phase 2. This pin should be connected to the positive
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output
inductor is utilized for current sensing.
To disable phase 2, connect CSP2 to VCC and CSN2 to GND.
13 SHDN
Shutdown Control Input. Connect to VCC for normal operation. Connect to ground to put the IC into
the 1μA (max at TA = +25°C) shutdown state. During startup, the output voltage is ramped up at 1/4
the slew rate set by the TIME resistor to the boot voltage or to the target voltage.
During the transition from normal operation to shutdown, the output voltage is ramped down at 1/4
the slew rate set by the TIME resistor. Forcing SHDN to 11V~13V to enter no-fault test mode clears
the fault latches, disables transient phase overlap, and turns off the internal BST_-to-VDD switches.
However, internal diodes still exist between BST_ and VDD in this state.
Deeper Sleep VR Control Input. This low-voltage logic input indicates power usage and sets the
operating mode together with PSI as shown in the truth table below. When DPRSLPVR is forced high, the
controller is immediately set to 1-phase automatic pulse-skipping mode. The controller returns to forced-
PWM mode when DPRSLPVR is forced low and the output is in regulation. The PWRGD upper threshold
is blanked during any downward output-voltage transition that happens when the controller is in skip
mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period
is complete and the output reaches regulation. During this blanking period, the overvoltage fault
threshold is changed from a tracking [VID + 300mV] threshold to a fixed 1.5V threshold.
The controller is in N-phase skip mode during startup including boot mode, but is in N-phase
forced-PWM mode during the transition from boot mode to VID mode, during soft-shutdown,
irrespective of the DPRSLPVR and PSI logic levels. However, if phases 2 and 3 are disabled by
connecting CSP2, CSP3 to VCC, then only phase 1 is active in the above modes.
DPRSLPVR PSI MODE
14 DPRSLPVR
1
0
0
X
0
1
Very low current (1-phase skip)
Intermediate power potential (N-1-phase PWM)
Max power potential (full-phase PWM: N-phase or 1 phase as set by user
at CSP2, CSP3)
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
14 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
This low-voltage logic input indicates power usage and sets the operating mode together
with DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if P SI is forced low, the
controller is immediately set to (N-1)-phase forced-PWM mode. The controller returns to N-phase
forced-PWM mode when P SI is forced high.
The controller is in N-phase skip mode during startup including boot mode, but is in N-phase forced-
PWM mode during the transition from boot mode to VID mode, during soft-shutdown, irrespective of
the DPRSLPVR and P SI logic levels. However, if phases 2 and 3 are disabled by connecting CSP2,
CSP3 to VCC, then only phase 1 is active in the above modes.
DPRSLPVR PSI MODE
15 PSI
1
0
0
X
0
1
Very low current (1-phase skip)
Intermediate power potential (N-1-phase PWM)
Max power potential (full-phase PWM: N-phase or 1 phase as set by user
at CSP2, CSP3)
16 TON
Switching Frequency Setting Input. An external resistor between the input power source and this pin
sets the switching frequency according to the following equation:
fSW = 1/(CTON x (RTON + 6.5kΩ))
where CTON = 16.26pF.
The external resistor must also satisfy the requirement [VIN(MIN)/RTON] ≥ 10μA where VIN(MIN) is the
minimum VIN value expected in the application.
TON is high impedance in shutdown.
17 CLKEN
C l ock E nab l e Op en- D r ai n Log i c O utp ut P ow er ed b y V
3 P 3
. Thi s i nver ted l og i c outp ut i nd i cates w hen the
outp ut vol tag e sensed at FB i s i n r eg ul ati on. C LKEN i s for ced hi g h i n shutd ow n and d ur i ng soft- star t and
soft- stop tr ansi ti ons. C LKEN i s for ced l ow d ur i ng d ynam i c V ID tr ansi ti ons and for an ad d i ti onal 20μs after
the tr ansi ti on i s com p l eted . C LKEN i s the i nver se of P WRGD , excep t for the 5m s P WRG D star tup d el ay
p er i od after C LKEN i s p ul l ed l ow . S ee the star tup ti m i ng d i ag r am ( Fi g ur e 9) . The C LKEN up p er thr eshol d
i s b l anked d ur i ng any d ow nw ar d outp ut- vol tag e tr ansi ti on that hap p ens w hen the contr ol l er i s i n ski p
m od e, and stays b l anked unti l the sl ew - r ate- contr ol l ed i nter nal - tr ansi ti on- r el ated P W RG D b l anki ng p er i od
i s com p l ete and the outp ut r eaches r eg ul ati on.
18 PWRGD
Open-Drain Power-Good Output. After output-voltage transitions, except during power-up and power-
down, if FB is in regulation, then PWRGD is high impedance.
PWRGD is low during startup, continues to be low while the output is at the boot voltage, and stays
low until 5ms (typ) after CLKEN goes low, after which it starts monitoring the FB voltage and goes
high if FB is within the PWRGD threshold window.
PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high impedance
whenever the slew-rate controller is active (output-voltage transitions), and continues to be forced
high impedance for an additional 20μs after the transition is completed.
The PWRGD upper threshold is blanked during any downward output-voltage transition that happens
when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-
related PWRGD blanking period is complete and the output reaches regulation.
A pullup resistor on PWRGD causes additional finite shutdown current.
19 DRSKP
Driver Skip Control Output. Push/pull logic output that controls the operating mode of the skip-mode
driver IC. DRSKP swings from VDD to GND. When DRSKP is high, the driver ICs operate in forced-
PWM mode. When DRSKP is low, the driver ICs enable their zero-crossing comparators and operate
in pulse-skipping mode. DRSKP goes low at the end of the soft-shutdown sequence, instructing the
external drivers to shut down.
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 15
Pin Description (continued)
PIN NAME FUNCTION
20 PWM3
PWM Signal Output for Phase 3. Swings from GND to VDD. Three-state whenever phase 3 is disabled
(in shutdown, when CSP3 is connected to VCC, and when operating with fewer than all phases).
21 BST2
Phase 2 Boost Flying Capacitor Connection. BST2 is the internal upper supply rail for the DH2 high-
side gate driver. An internal switch between VDD and BST2 charges the BST2-LX2 flying capacitor
while the low-side MOSFET is on (DL2 pulled high).
22 LX2 Phase 2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
Also used as an input to phase 2’s zero-crossing comparator.
23 DH2 Phase 2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.
24 DL2
Phase 2 Low-Side Gate-Driver Output. DL2 swings from GND to VDD. DL2 is forced low in shutdown.
DL2 is forced high when an output overvoltage fault is detected, overriding any negative current-
limit condition that might be present. DL2 is forced low in skip mode after detecting an inductor
current zero crossing.
25 VRHOT Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes
below 1.5V (30% of VCC). VRHOT is high impedance in shutdown.
26 VDD
Supply Voltage Input for the DL_ Drivers. VDD is also the supply voltage used to internally recharge
the BST_-LX_ flying capacitor during the times the respective DL_s are high. Connect VDD to the
4.5V to 5.5V system supply voltage. Bypass VDD to GND with a 1μF or greater ceramic capacitor.
27 DL1
Phase 1 Low-Side Gate-Driver Output. DL1 swings from GND to VDD. DL1 is forced low in shutdown.
DL1 is forced high when an output overvoltage fault is detected, overriding any negative current-
limit condition that might be present. DL1 is forced low in skip mode after detecting an inductor
current zero crossing.
28 DH1 Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.
29 LX1 Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to phase 1’s zero-crossing comparator.
30 BST1
Phase 1 Boost Flying Capacitor Connection. BST1 is the internal upper supply rail for the DH1 high-
side gate driver. An internal switch between VDD and BST1 charges the BST1-LX1 flying capacitor
while the low-side MOSFET is on (DL1 pulled high).
31 PGD_IN
Power-Good Logic Input Pin that Indicates the Power Status of Other System Rails and Used for Supply
Sequencing. During startup, after soft-starting to the boot voltage, the output voltage remains at VBOOT,
and the CLKEN and PWRGD outputs remain high and low, respectively, as long as the PGD_IN input
stays low. When PGD_IN later goes high, the output is allowed to transition to the voltage set by the VID
code, and CLKEN is allowed to go low. During normal operation, if PGD_IN goes low, the controller
immediately forces CLKEN high and PWRGD low, and slews the output to the boot voltage while in skip
mode at 1/4 the normal slew rate set by the TIME resistor. The output then stays at the boot voltage until
the controller is turned off or power cycled, or until PGD_IN goes high again.
32–38 D0–D6
Low-Voltage (1.0V Logic) VID DAC Code Inputs. The D0–D6 inputs do not have internal pullups. These
1.0V logic inputs are designed to interface directly with the CPU. The output voltage is set by the VID
code indicated by the logic-level voltages on D0–D6 (see Table 4).
The 1111111 code corresponds to a shutdown mode. When this code is detected, The
MAX17030/MAX17036 initiate a soft-shutdown transition identical to the shutdown transition for a
SHDN falling edge. After slewing the output to 0V, it forces DH_, DL_, and DRSKP low, and three-states
PWM3. The IC remains active and its VCC quiescent current consumption stays the same as in normal
operation. If D6–D0 is changed from 1111111 to a different code, the MAX17030/MAX17036 initiate a
startup sequence identical to the startup sequence for a SHDN rising edge.
39 CSP1
Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output
inductor is utilized for current sensing.
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
16 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
40 CSN1
Negative Input of the Output Current Sense of Phase 1. This pin should be connected to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing. A 10 discharge FET is turned on in UVLO event
or thermal shutdown, or at the end of soft-shutdown.
—PAD (GND) Exposed Backplate (Pad) of Package. Internally connected to both analog ground and power
(driver) grounds. Connect to the ground plane through a thermally enhanced via.
MAX8791
CBST
R2
2ΩRNTC1
RILIM1 RILIM2
RTON
200kΩ
TON
BST1 CIN
NH
SHDN
DPRSLPVR
PGDIN
PSI
DPRSLPVR
PGDIN
PSI
VDD
5V BIAS
VCC
32 16
30
28
29
27
39
40
21
23
22
24
12
11
20
19
2
1
9
8
10
33
34
35
36
37
38
13
14
31
15
26
7
5
6
18
25
17
4
3
D1
D0
D2
D3
D4
D5
D6
8V TO 20V
PWR INPUT
OUTPUT
(IMVP-6.5 CORE)
ON OFF (VRON)
PWRGD
VCC
VCCP
VSS_SENSE
VID INPUTS
DH1
LX1
NL
DL1
L1
R1
RCATCHGND
10Ω
CSN1
CCS1
CSP1
COUT
ILIM
TIME
RTHRM
13kΩ
THRM
RPWRGD
1.9kΩ
RCLKEN
1.9kΩ
RVRHOT
56Ω
VRHOT
CLKEN
RFB
RFBS
10ΩRCATCHCORE
10Ω
RGNDS
10Ω
IMONIMON
NTC
100kΩ
β = 4250
PAD
RIMON
FB
FBAC
GNDS
CFBS
1000pF
CGNDS
4700pF
CPU REMOTE
SENSE
3.3V
RVCC
20Ω
CVDD
2.2μF
CVCC
1.0μF
CBST
R5 RNTC2
BST2 CIN
NH
8V TO 20V
PWR INPUT
DH2
LX2
NL
DL2
L2
R4
CSN2
CCS2
CSP2
COUT
CBST
R8 RNTC3
BST CIN
NH
8V TO 20V
PWR INPUT
5V BIAS
DH
LX
NL
DL
L3
R7
CSN3
CCS3
CSP3
COUT
GND
VCC
CVCC1
1.0μF
PWM3
DRSKP
PWM
SKIP
MAX17030
MAX17036
R3
R6
2Ω
R9
2Ω
VSS_SENSE
VCC_SENSE
Figure 1. Standard 3-Phase IMVP-6.5 Application Circuit
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 17
DESIGN PARAMETERS IMVP-6.5 XE CORE
3-PHASE
IMVP-6.5 SV CORE
3-PHASE
IMVP-6.5 SV CORE
2-PHASE
Circuit Figure 1 Figure 1 Figure 2
Input Voltage Range 8V to 20V 8V to 20V 8V to 20V
Maximum Load Current 65A (48A TDC) 52A (38A TDC) 52A (38A TDC)
Transient Load Current 49A
(100A/μs)
39A
(100A/μs)
39A
(100A/μs)
Load Line -1.9mV/A -1.9mV/A -1.9mV/A
POC Setting 110 101 101
TON Resistance (RTON) 200k (fSW = 300kHz) 200k (fSW = 300kHz) 200k (fSW = 300kHz)
Inductance (L)
0.36μH, 36A, 0.82m
(10mm x 10mm)
Panasonic ETQP4LR36ZFC
0.42μH, 20A, 1.55m
(7mm x 7mm)
NEC/TOKIN MPC0740LR42C
0.36μH, 36A, 0.82m
(10mm x 10mm)
Panasonic ETQP4LR36ZFC
High-Side MOSFET (NH)
Fairchildsemi
1x FDS6298
9.4m/12m (typ/max)
Toshiba
1x TPCA8030-H
9.6m/13.4m (typ/max)
Fairchildsemi
1x FDS6298
9.4m/12m (typ/max)
Toshiba
1x TPCA8030-H
9.6m/13.4m (typ/max
Fairchildsemi
1x FDS6298
9.4m/12m (typ/max)
Toshiba
1x TPCA8030-H
9.6m/13.4m (typ/max)
Low-Side MOSFET (NL)
Fairchildsemi
2x FDS8670
4.2m/5m (typ/max)
Toshiba
2x TPCA8019-H
Fairchildsemi
1x FDS8670
4.2m/5m (typ/max)
Toshiba
1x TPCA8019-H
Fairchildsemi
2x FDS8670
4.2m/5m (typ/max)
Toshiba
2x TPCA8019-H
Output Capacitors (COUT)
(MAX17030 Only)
Contact Maxim for MAX17036
reference design
4x 330μF, 2V, 4.5m
Panasonic EEFSXOD331E4 or
NEC/Tokin PSGVOE337M4.5
27x 22μF, 6.3V X5R
ceramic capacitor (0805)
3x 330μF, 2V, 4.5m
Panasonic EEFSXOD331E4 or
NEC/Tokin PSGVOE337M4.5
27x 22μF, 6.3V X5R
ceramic capacitor (0805)
4x 330μF, 6m, 2.5V
Panasonic EEFSX0D0D331XR
28x 10μF, 6V ceramic (0805)
Input Capacitors (CIN) 6x 10μF 25V ceramic (1210) 4x 10μF 25V ceramic (1210) 4x 10μF 25V ceramic (1210)
TIME-ILIM Resistance (RILIM2) 14k 14k 16.9k
ILIM-GND Resistance (RILIM1) 137k 137k 133k
FB Resistance (RFB) 6.04k 453k 6.04k
IMON Resistance (RIMON) 12.1k 10.2k 14k
LX-CSP Resistance 2.21k (R1, R4, R7) 1.4k (R1, R4, R7) 2.21k (R1, R7)
CSP-CSN Resistance 3.24k (R2, R5, R8)
40.2k (R3, R6, R9)
2k (R2, R5, R8)
40.2k (R3, R6, R9)
3.24k (R2, R8)
40.2k (R3, R9)
DCR Sense NTC (RNTC)10k NTC B = 3380
TDK NTCG163JH103F
10k NTC B = 3380
TDK NTCG163JH103F
10k NTC B = 3380
TDK NTCG163JH103F
DCR Sense Capacitance
(CSENSE)0.22μF, 6V ceramic (0805) 0.22μF, 6V ceramic (0805) 0.22μF, 6V ceramic (0805)
Table 1. Component Selection for Standard Applications
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
18 ______________________________________________________________________________________
MANUFACTURER WEBSITE
AVX Corp. www.avxcorp.com
Fairchild Semiconductor www.fairchildsemi.com
NEC/TOKIN America, Inc. www.nec-tokinamerica.com
Panasonic Corp. www.panasonic.com
SANYO Electric Co., Ltd. www.sanyodevice.com
MANUFACTURER WEBSITE
Siliconix (Vishay) www.vishay.com
Taiyo Yuden www.t-yuden.com
TDK Corp. www.component.tdk.com
TOKO America, Inc. www.tokoam.com
Toshiba America Electronic
Components, Inc. www.toshiba.com/taec
Table 2. Component Suppliers
MAX17030
MAX17036
CBST
R2 RNTC1
RILIM1 RILIM2
RTON
200kΩ
TON
BST1 CIN
NH
SHDN
DPRSLPVR
PGDIN
PSI
DPRSLPVR
PGDIN
PSI
VDD
5V BIAS
VCC
D0
D1
D2
D3
D4
D5
D6
8V TO 20V
PWR INPUT
OUTPUT
(IMVP-6.5 CORE)
ON OFF (VRON)
PWRGD
VCC
VCCP
VID INPUTS DH1
LX1
NL
DL1
L1
R1
RCATCHGND
10Ω
CSN1
CCS1
CSP1
COUT
ILIM
TIME
RTHRM
13kΩ
THRM
RPWRGD
1.9kΩ
RCLKEN
1.9kΩ
RVRHOT
56Ω
VRHOT
CLKEN
RFB
RFBS
10Ω
RCATCHCORE
10Ω
RGNDS
10Ω
IMONIMON
VSS_SENSE
NTC
100kΩ
β = 4250
PAD
RIMON
FB
FBAC
GNDS
CFBS
1000pF CPU REMOTE
SENSE
3.3V
RVCC
20Ω
CVDD
2.2μF
CVCC
1.0μFCBST
R8 RNTC3
BST2 CIN
NH
8V TO 20V
PWR INPUT
5V BIAS
DH2
LX2
NL
DL2
L2
R7
CSN2
CCS2
CSP2
COUT
CSN3
CSP3
PWM3
DRSKP
32
33
34
35
36
37
38
13
14
31
15
26
7
5
6
18
25
17
4
3
16
30
28
29
27
39
40
21
23
22
24
12
19
20
11
2
9
1
8
10
R3
2Ω
2Ω
R9
VCC_SENSE
VSS_SENSE
Figure 2. Standard 2-Phase IMVP-6.5 Application Circuit
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 19
THRM
0.3 x VCC
VRHOT
CSN3
CSP3
10x
CSN2
CSP2
10x
CSN1
ILIM
TIME
VCC
CSP1
10x
REF
(2.0V)
GND
D0–D6 DAC R-TO-I
CONVERTER
FAULT
SHDN
PGDIN
TARGET
SEL
PHASE
FB
GNDS
FBAC
CSN
CSP
Gm(FB)
x3 MAX17030
MAX17036
PWM3
DRSKP
ONE-SHOT
PHASE 3
ON-TIME
Q TRIG3
TON
CC13
CCI2
TRIG
PHASE 3 DRIVER
CONTROL
CSP1
CSN1
Gm(CCI3)
CSN3
CSP3
Gm(CCI)
CSP1
CSN1
Gm(CCI)
CSN2
CSP2
Gm(CCI)
BST2
DH2
LX2
DL2
GND
ONE-SHOT
PHASE 2
ON-TIME
Q TRIG
PHASE 2 DRIVERS
SLEW
MINIMUM
OFF-TIME
ONE SHOT
Q TRIG TRIG 3
S
R
Q
PGND1
PHASE 1
ON-TIME
ONE-SHOT
LX1
0mV
R
S
Q
Q TRIG
SKIP
DL1
PWRGD
GND
VDD
BST1
TON
FB
MAIN PHASE
DRIVERS
DH1
LX1
SKIP
BLANK
TARGET
+ 200mV
TARGET
- 300mV
PGDIN DPRSLPVR PSI
CLKEN
IMON
60μs
MODE/PHASE/SLEW-
RATE CONTROL
5ms
STARTUP
DELAY
CSP
CSN Gm(IMON)
x3
Figure 3. Functional Diagram
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
20 ______________________________________________________________________________________
Detailed Description
Free-Running, Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-time, current-mode regulator with
voltage feed-forward (Figure 3). This architecture relies on
the output filter capacitor’s ESR to act as the current-
sense resistor, so the output ripple voltage provides the
PWM ramp signal. The control algorithm is simple: the
high-side switch on-time is determined solely by a one-
shot whose period is inversely proportional to input volt-
age, and directly proportional to output voltage or the
difference between the main and secondary inductor cur-
rents (see the
On-Time One-Shot
section
)
. Another one-
shot sets a minimum off-time. The on-time one-shot
triggers when the error comparator goes low, the inductor
current of the selected phase is below the valley current-
limit threshold, and the minimum off-time one-shot times
out. The controller maintains 120° out-of-phase operation
by alternately triggering the three phases after the error
comparator drops below the output-voltage set point.
Triple 120° Out-of-Phase Operation
The three phases in the MAX17030/MAX17036 operate
120°out-of-phase to minimize input and output filtering
requirements, reduce electromagnetic interference (EMI),
and improve efficiency. This effectively lowers component
count—reducing cost, board space, and component
power requirements—making the MAX17030/MAX17036
ideal for high-power, cost-sensitive applications.
The MAX17030/MAX17036 share the current between
three phases that operate 120°out-of-phase, so the
high-side MOSFETs never turn on simultaneously dur-
ing normal operation. The instantaneous input current
of each phase is effectively reduced, resulting in
reduced input voltage ripple, ESR power loss, and RMS
ripple current (see the
Input Capacitor Selection
sec-
tion). Therefore, the same performance can be
achieved with fewer or less-expensive input capacitors.
+5V Bias Supply (VCC and VDD)
The Quick-PWM controller requires an external +5V
bias supply in addition to the battery. Typically, this
+5V bias supply is the notebook’s 95% efficient +5V
system supply. The +5V bias supply must provide VCC
(PWM controller) and VDD (gate-drive power), so the
maximum current drawn is:
where ICC is provided in the
Electrical Characteristics
table, fSW is the switching frequency, and QG(LOW) and
QG(HIGH) are the MOSFET data sheet’s total gate-
charge specification limits at VGS = 5V.
VIN and VDD can be connected together if the input
power source is a fixed +4.5V to +5.5V supply. If the
+5V bias supply is powered up prior to the battery sup-
ply, the enable signal (SHDN going from low to high)
must be delayed until the battery voltage is present to
ensure startup.
Switching Frequency (TON)
Connect a resistor (RTON) between TON and VIN to set
the switching period TSW = 1/fSW, per phase:
TSW = 16.26pF x (RTON + 6.5kΩ)
A 96.75kΩto 303.25kΩcorresponds to switching peri-
ods of 167ns (600kHz) to 500ns (200kHz), respectively.
High-frequency (600kHz) operation optimizes the appli-
cation for the smallest component size, trading off effi-
ciency due to higher switching losses. Low-frequency
(200kHz) operation offers the best overall efficiency at
the expense of component size and board space.
TON Open-Circuit Protection
The TON input includes open-circuit protection to avoid
long, uncontrolled on-times that could result in an over-
voltage condition on the output. The MAX17030/
MAX17036 detect an open-circuit fault if the TON current
drops below 10μA for any reason—the TON resistor
(RTON) is unpopulated, a high resistance value is used,
the input voltage is low, etc. Under these conditions, the
MAX17030/MAX17036 stop switching (DH and DL pulled
low) and immediately set the fault latch. Toggle SHDN or
cycle the VCC power supply below 0.5V to clear the fault
latch and reactivate the controller.
On-Time One-Shot
The MAX17030/MAX17036 contain a fast, low-jitter,
adjustable one-shot that sets the high-side MOSFETs
on-time. It is shared among the three phases. The one-
shot for the main phase varies the on-time in response
to the input and feedback voltages. The main high-side
switch on-time is inversely proportional to the input volt-
age as measured by the V+ input, and proportional to
the feedback voltage (VFB):
The one-shot for the second phase and third phase
varies the on-time in response to the input voltage and
the difference between the main and the other inductor
currents. Two identical transconductance amplifiers
integrate the difference between the master and each
slave’s current-sense signals. The summed output is
connected to an internal integrator for each master-
slave pair, which serves as the input to the respective
slave’s high-side MOSFET TON timer.
tTV V
V
ON SW FB
IN
=+
()
0 075.
IIfQ Q
BIAS CC SW G LOW G HIGH
=+ +
()
() ( )
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 21
When the main and other phase current-sense signals
(VCM = VCMP - VCMN and VCS = VCSP - VCSM) become
unbalanced, the transconductance amplifiers adjust the
other phase’s on-time, which increases or decreases
the phase inductor current until the current-sense sig-
nals are properly balanced:
where VCCI is the internal integrator node for each
slave’s current-balance integrator, and ZCCI is the
effective impedance at that node.
During phase overlap, tON is calculated based on
phase 1’s on-time requirements, but reduced by 33%
when operating with three phases.
For a 3-phase regulator, each phase cannot be
enabled until the other 2 phases have completed their
on-time and the minimum off-times have expired. As
such, the minimum period is limited by 3 x (tON +
tOFF(MIN)). Maximum tON is dependent on minimum VIN
and maximum output voltage:
TSW(MIN) = NPH x (tON(MAX) + tOFF(MIN))
where:
tON(MAX) = VFB(MAX)/VIN(MIN x TSW(MIN)
so:
TSW(MIN) = tOFF(MIN)/[1/NPH – VIN(MAX)/VIN(MIN)]
Hence, for a 7V input and 1.1V output, 500kHz is the
maximum switching frequency. Running at this limit is
not desirable as there is no room to allow the regulator
to make adjustments without triggering phase overlap.
For a 3-phase, high-current application with minimum
8V input, the practical switching frequency is 300kHz.
On-times translate only roughly to switching frequen-
cies. The on-times guaranteed in the
Electrical
Characteristics
are influenced by parasitics in the con-
duction paths and propagation delays. For loads above
the critical conduction point, where the dead-time effect
(LX flying high and conducting through the high-side
FET body diode) is no longer a factor, the actual
switching frequency (per phase) is:
where VDIS and VCHG are the sum of the parasitic volt-
age drops in the inductor discharge and charge paths,
including MOSFET, inductor, and PCB resistances;
VCHG is the sum of the parasitic voltage drops in the
inductor charge path, including high-side switch,
inductor, and PCB resistances; and tON is the on-time
as determined above.
Current Sense
The MAX17030/MAX17036 sense the output current of
each phase allowing the use of current-sense resistors
on inductor DCR as the current-sense element. Low-
offset amplifiers are used for current balance, voltage-
positioning gain, and current limit.
Using the DC resistance (RDCR) of the output inductor
allows higher efficiency. The initial tolerance and tem-
perature coefficient of the inductor’s DCR must be
accounted for in the output-voltage droop-error budget
and current monitor. This current-sense method uses
an RC filtering network to extract the current information
from the output inductor (see Figure 4). The RC network
should match the inductor’s time constant (L/RDCR):
and:
where RCS is the required current-sense resistance,
and RDCR is the inductor’s series DC resistance. Use
the typical inductance and RDCR values provided by
the inductor manufacturer. To minimize the current-
sense error due to the current-sense inputs’ bias current
(ICSP_ and ICSN_), choose R1//R2 to be less than 2kΩ
and use the above equation to determine the sense
capacitance (CEQ). Choose capacitors with 5% toler-
ance and resistors with 1% tolerance specifications.
Temperature compensation is recommended for this
current-sense method. See the
Voltage Positioning and
Loop Compensation
section for detailed information.
When using a current-sense resistor for accurate out-
put-voltage positioning, the circuit requires a differential
RC filter to eliminate the AC voltage step caused by the
equivalent series inductance (LESL) of the current-
sense resistor (see Figure 4). The ESL induced voltage
step might affect the average current-sense voltage.
The RC filter’s time constant should match the LESL/
RSENSE time constant formed by the current-sense
resistor’s parasitic inductance:
L
RCR
ESL
SENSE EQ EQ
=
RL
CRR
CS EQ
=+
⎡
⎣
⎢⎤
⎦
⎥
1
1
1
2
RR
RRR
CS DCR
=+
⎛
⎝
⎜⎞
⎠
⎟
2
12
fVV
tVV V
SW OUT DIS
ON IN DIS CHG
=+
()
+−
()
tT
VV
V
TV
ON SEC SW CCI
IN
SW FB
()
.
.
=+
⎛
⎝
⎜⎞
⎠
⎟
=+
0 075
00
775V
VTIZ
V
IN SW CCI CCI
IN
⎛
⎝
⎜⎞
⎠
⎟+⎛
⎝
⎜⎞
⎠
⎟
=Main On-ttime Secondary Current Balance Correctio
()
+nn
()
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
22 ______________________________________________________________________________________
where LESL is the equivalent series inductance of the cur-
rent-sense resistor, RSENSE is current-sense resistance
value, and CEQ and REQ are the time-constant matching
components.
Current Balance
The MAX17030/MAX17036 integrate the difference
between the current-sense voltages and adjust the on-
time of the secondary phase to maintain current bal-
ance. The current balance relies on the accuracy of the
current-sense signals across the current-sense resistor
or inductor DCR. With active current balancing, the cur-
rent mismatch is determined by the current-sense resis-
tor or inductor DCR values and the offset voltage of the
transconductance amplifiers:
where RSENSE = RCM = RCS and VOS(IBAL) is the
current balance offset specification in the
Electrical
Characteristics
table.
The worst-case current mismatch occurs immediately
after a load transient due to inductor value mismatches
resulting in different di/dt for the two phases. The time it
takes the current-balance loop to correct the transient
imbalance depends on the mismatch between the
inductor values and switching frequency.
III
V
R
OS IBAL LMAIN LSEC OS IBAL
SENSE
() ()
=−=
A) OUTPUT SERIES RESISTOR SENSING
DH_
INPUT (VIN)
DL_
LX_
CIN
NL
NH
DL
CSP_
CSN_
L
B) LOSSLESS INDUCTOR SENSING
DH_
INPUT (VIN)
DL_
LX_
CIN
NL
NH
DL
CSP_
CSN_
COUT
INDUCTOR
R1
CEQ
LRDCR
SENSE RESISTOR
LESL RSENSE
COUT
REQ CEQ
R2
RSENSE
LESL
CEQREQ =
RDCR
R1 + R2
R2
RCS =
11
R1 R2CEQ
L
RDCR =[ + ]
FOR THERMAL COMPENSATION:
R2 SHOULD CONSIST OF AN NTC RESISTOR IN
SERIES WITH A STANDARD THIN-FILM RESISTOR
MAX17030
MAX17036
MAX17030
MAX17036
Figure 4. Current-Sense Methods
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 23
Current Limit
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that senses the voltage across
the current-sense resistors or inductor DCR at the cur-
rent-sense inputs (CSP_ to CSN_). If the current-sense
signal of the selected phase is above the current-limit
threshold, the PWM controller does not initiate a new
cycle until the inductor current of the selected phase
drops below the valley current-limit threshold. When
any one phase exceeds the current limit, all phases are
effectively current limited since the interleaved con-
troller does not initiate a cycle with the next phase.
Since only the valley current is actively limited, the actu-
al peak current is greater than the current-limit thresh-
old by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and
maximum load capability are a function of the current-
sense resistance, inductor value, and battery voltage.
The positive valley current-limit threshold voltage at
CSP to CSN equals precisely 1/10 of the differential
TIME to ILIM voltage over a 0.1V to 0.5V range (10mV
to 50mV current-sense range). Connect ILIM directly to
VCC to set the default current-limit threshold setting of
22.5mV (typ).
The negative current-limit threshold (forced-PWM mode
only) is nominally -125% of the corresponding valley
current-limit threshold. When the inductor current drops
below the negative current limit, the controller immedi-
ately activates an on-time pulse—DL turns off, and DH
turns on—allowing the inductor current to remain above
the negative current threshold.
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signals seen by the current-sense inputs (CSP_, CSN_).
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier
(Steady-State Droop)
The MAX17030/MAX17036 include a transconductance
amplifier for adding gain to the voltage-positioning sense
path. The amplifier’s input is generated by summing the
current-sense inputs, which differentially sense the volt-
age across either current-sense resistors or the induc-
tor’s DCR. The amplifier’s output connects directly to the
regulator’s voltage-positioned feedback input (FB), so
the resistance between FB and the output-voltage sense
point determines the voltage-positioning gain:
where the target voltage (VTARGET) is defined in the
Nominal Output Voltage Selection
section, and the FB
amplifier’s output current (IFB) is determined by the
sum of the current-sense voltages:
where VCSX = VCSP - VCSN is the differential current-
sense voltage, and Gm(FB) is typically 400μS as
defined in the
Electrical Characteristics
.
Differential Remote Sense
The MAX17030/MAX17036 include differential, remote-
sense inputs to eliminate the effects of voltage drops
along the PCB traces and through the processor’s
power pins. The feedback-sense node connects to the
voltage-positioning resistor (RFB). The ground-sense
(GNDS) input connects to an amplifier that adds an off-
set directly to the target voltage, effectively adjusting
the output voltage to counteract the voltage drop in the
ground path. Connect the voltage-positioning resistor
(RFB) and ground sense (GNDS) input directly to the
processor’s remote sense outputs as shown in Figure 1.
Integrator Amplifier
An internal integrator amplifier forces the DC average of
the FB voltage to equal the target voltage, allowing
accurate DC output-voltage regulation regardless of the
output ripple voltage.
The MAX17030/MAX17036 disable the integrator by
connecting the amplifier inputs together at the begin-
ning of all VID transitions done in pulse-skipping mode
(DPRSLPVR = high). The integrator remains disabled
until 20μs after the transition is completed (the internal
target settles) and the output is in regulation (edge
detected on the error comparator).
Transient Overlap Operation
When a transient occurs, the response time of the con-
troller depends on how quickly it can slew the inductor
current. Multiphase controllers that remain 120°out-of-
phase when a transient occurs actually respond slower
than an equivalent single-phase controller. In order to
provide fast transient response, the MAX17030/
MAX17036 support a phase overlap mode, which
allows the triple regulators to operate in-phase when
heavy load transients are detected, effectively reducing
the response time. After any high-side MOSFET turns
off, if the output voltage does not exceed the regulation
voltage when the minimum off-time expires, the con-
troller simultaneously turns on all high-side MOSFETs
with the same on-time during the next on-time cycle.
The phases remain overlapped until the output voltage
exceeds the regulation voltage after the minimum
IG V
FB m FB CSX
X
PH
=∑
=
() 1
η
VV RI
OUT TARGET FB FB
=−
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
24 ______________________________________________________________________________________
*
Multiphase operation = All enabled phases active.
off-time expires. The on-time for each phase is based
on the input voltage to FB ratio (i.e., follows the master
on-time), but reduced by 33% in a 3-phase configura-
tion, and not reduced in a 2-phase configuration. This
maximizes the total inductor current slew rate.
After the phase-overlap mode ends, the controller auto-
matically begins with the next phase. For example, if
phase 2 provided the last on-time pulse before overlap
operation began, the controller starts switching with
phase 3 when overlap operation ends.
Nominal Output Voltage Selection
The nominal no-load output voltage (VTARGET) is
defined by the selected voltage reference (VID DAC)
plus the remote ground-sense adjustment (VGNDS) as
defined in the following equation:
where VDAC is the selected VID voltage. On startup, the
MAX17030/MAX17036 slew the target voltage from
ground to the preset boot voltage. Table 3 is the operating
mode truth table.
DAC Inputs (D0–D6)
The digital-to-analog converter (DAC) programs the out-
put voltage using the D0–D6 inputs. D0–D6 are low-volt-
age (1.0V) logic inputs, designed to interface directly with
the CPU. Do not leave D0–D6 unconnected. Changing
D0–D6 initiates a transition to a new output-voltage level.
Change D0–D6 together, avoiding greater than 20ns
skew between bits. Otherwise, incorrect DAC readings
might cause a partial transition to the wrong voltage level
followed by the intended transition to the correct voltage
level, lengthening the overall transition time. The available
DAC codes and resulting output voltages are compatible
with the IMVP-6.5 (Table 4) specifications.
OFF Code
VID = 1111111 is defined as an OFF code. When the
OFF code is set, the MAX17030/MAX17036 go through
the same shutdown sequence as though SHDN has
been pulled low—output discharged to zero, CLKEN
high, and PWRGD low. Only the IC supply currents
remain at the operating levels rather than the shutdown
level. When exiting from the OFF code, the MAX17030/
MAX17036 go through the boot sequence, similar to the
sequence when SHDN is first pulled high.
VVVV
TARGET FB DAC GNDS
== +
INPUTS
SHDN DPRSLPVR PSI
PHASE
OPERATION* OPERATING MODE
GND X X Disabled Low-Power Shutdown Mode. DL1 and DL2 forced low, and the
controller is disabled. The supply current drops to 1μA (max).
Rising X X Multiphase Pulse Skipping
1/4 RTIME Slew Rate
Startup/Boot. When SHDN is pulled high, the MAX17030/
MAX17036 begin the startup sequence. Once the REF is above 1.84V,
the controller enables the PWM controller and ramps the output
voltage up to the boot voltage. See Figure 9.
High Low High M ul ti p hase For ced - P W M
N om i nal RT IM E
S l ew Rate
Full Power. The no-load output voltage is determined by the selected
VID DAC code (D0–D6, Table 4).
High Low Low (N-1)-Phase Forced-PWM
N om i nal RT IM E
S l ew Rate
Intermediate Power. The no-load output voltage is determined by the
selected VID DAC code (D0–D6, Table 4). When PSI is pulled low, the
MAX17030/MAX17036 immediately disable phase 3, PWM3 is three-
state, and DRSKP is low.
High High X 1-Phase Pulse Skipping
N om i nal RT IM E
S l ew Rate
Deeper Sleep Mode. The no-load output voltage is determined by the
selected VID DAC code (D0–D6, Table 4). When DPRSLPVR is pulled
high, the MAX17030/MAX17036 immediately enter 1-phase pulse-
skipping operation allowing automatic PWM/PFM switchover under
light loads. The PWRGD and CLKEN upper thresholds are blanked.
DH2 and DL2 are pulled low, PWM3 is three-state and DRSKP is low.
Table 3. Operating Mode Truth Table
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 25
INPUTS
SHDN DPRSLPVR PSI
PHASE
OPERATION* OPERATING MODE
Falling X X Multiphase Forced-PWM
1/4 RTIME Slew Rate
Shutdown. When SHDN is pulled low, the MAX17030/MAX17036
immediately pull PWRGD low, CLKEN becomes high impedance, all
enabled phases are activated, and the output voltage is ramped down
to 12.5mV; then DH and DL are pulled low and CSN1 discharge FET is
turned on.
High X X Disabled
Faul t M od e. The faul t l atch has b een set b y the M AX 17030/M AX 17036
UVP or thermal-shutdown protection, or by the OVP protection. The
controller remains in fault mode until VCC power is cycled or SHDN
toggled.
Table 3. Operating Mode Truth Table (continued)
*
Multiphase operation = All enabled phases active.
D6 D5 D4 D3 D2 D1 D0
OUTPUT
VOLTAGE
(V)
D6 D5 D4 D3 D2 D1 D0
OUTPUT
VOLTAGE
(V)
0 0 0 0 0 0 0 1.5000 1 0 0 0 0 0 0 0.7000
0 0 0 0 0 0 1 1.4875 1 0 0 0 0 0 1 0.6875
0 0 0 0 0 1 0 1.4750 1 0 0 0 0 1 0 0.6750
0 0 0 0 0 1 1 1.4625 1 0 0 0 0 1 1 0.6625
0 0 0 0 1 0 0 1.4500 1 0 0 0 1 0 0 0.6500
0 0 0 0 1 0 1 1.4375 1 0 0 0 1 0 1 0.6375
0 0 0 0 1 1 0 1.4250 1 0 0 0 1 1 0 0.6250
0 0 0 0 1 1 1 1.4125 1 0 0 0 1 1 1 0.6125
0 0 0 1 0 0 0 1.4000 1 0 0 1 0 0 0 0.6000
0 0 0 1 0 0 1 1.3875 1 0 0 1 0 0 1 0.5875
0 0 0 1 0 1 0 1.3750 1 0 0 1 0 1 0 0.5750
0 0 0 1 0 1 1 1.3625 1 0 0 1 0 1 1 0.5625
0 0 0 1 1 0 0 1.3500 1 0 0 1 1 0 0 0.5500
0 0 0 1 1 0 1 1.3375 1 0 0 1 1 0 1 0.5375
0 0 0 1 1 1 0 1.3250 1 0 0 1 1 1 0 0.5250
0 0 0 1 1 1 1 1.3125 1 0 0 1 1 1 1 0.5125
0 0 1 0 0 0 0 1.3000 1 0 1 0 0 0 0 0.5000
0 0 1 0 0 0 1 1.2875 1 0 1 0 0 0 1 0.4875
0 0 1 0 0 1 0 1.2750 1 0 1 0 0 1 0 0.4750
0 0 1 0 0 1 1 1.2625 1 0 1 0 0 1 1 0.4625
0 0 1 0 1 0 0 1.2500 1 0 1 0 1 0 0 0.4500
0 0 1 0 1 0 1 1.2375 1 0 1 0 1 0 1 0.4375
0 0 1 0 1 1 0 1.2250 1 0 1 0 1 1 0 0.4250
0 0 1 0 1 1 1 1.2125 1 0 1 0 1 1 1 0.4125
0 0 1 1 0 0 0 1.2000 1 0 1 1 0 0 0 0.4000
0 0 1 1 0 0 1 1.1875 1 0 1 1 0 0 1 0.3875
Table 4. IMVP-6.5 Output Voltage VID DAC Codes
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
26 ______________________________________________________________________________________
D6 D5 D4 D3 D2 D1 D0
OUTPUT
VOLTAGE
(V)
D6 D5 D4 D3 D2 D1 D0
OUTPUT
VOLTAGE
(V)
0 0 1 1 0 1 0 1.1750 1 0 1 1 0 1 0 0.3750
0 0 1 1 0 1 1 1.1625 1 0 1 1 0 1 1 0.3625
0 0 1 1 1 0 0 1.1500 1 0 1 1 1 0 0 0.3500
0 0 1 1 1 0 1 1.1375 1 0 1 1 1 0 1 0.3375
0 0 1 1 1 1 0 1.1250 1 0 1 1 1 1 0 0.3250
0 0 1 1 1 1 1 1.1125 1 0 1 1 1 1 1 0.3125
0 1 0 0 0 0 0 1.1000 1 1 0 0 0 0 0 0.3000
0 1 0 0 0 0 1 1.0875 1 1 0 0 0 0 1 0.2875
0 1 0 0 0 1 0 1.0750 1 1 0 0 0 1 0 0.2750
0 1 0 0 0 1 1 1.0625 1 1 0 0 0 1 1 0.2625
0 1 0 0 1 0 0 1.0500 1 1 0 0 1 0 0 0.2500
0 1 0 0 1 0 1 1.0375 1 1 0 0 1 0 1 0.2375
0 1 0 0 1 1 0 1.0250 1 1 0 0 1 1 0 0.2250
0 1 0 0 1 1 1 1.0125 1 1 0 0 1 1 1 0.2125
0 1 0 1 0 0 0 1.0000 1 1 0 1 0 0 0 0.2000
0 1 0 1 0 0 1 0.9875 1 1 0 1 0 0 1 0.1875
0 1 0 1 0 1 0 0.9750 1 1 0 1 0 1 0 0.1750
0 1 0 1 0 1 1 0.9625 1 1 0 1 0 1 1 0.1625
0 1 0 1 1 0 0 0.9500 1 1 0 1 1 0 0 0.1500
0 1 0 1 1 0 1 0.9375 1 1 0 1 1 0 1 0.1375
0 1 0 1 1 1 0 0.9250 1 1 0 1 1 1 0 0.1250
0 1 0 1 1 1 1 0.9125 1 1 0 1 1 1 1 0.1125
0 1 1 0 0 0 0 0.9000 1 1 1 0 0 0 0 0.1000
0 1 1 0 0 0 1 0.8875 1 1 1 0 0 0 1 0.0875
0 1 1 0 0 1 0 0.8750 1 1 1 0 0 1 0 0.0750
0 1 1 0 0 1 1 0.8625 1 1 1 0 0 1 1 0.0625
0 1 1 0 1 0 0 0.8500 1 1 1 0 1 0 0 0.0500
0 1 1 0 1 0 1 0.8375 1 1 1 0 1 0 1 0.0375
0 1 1 0 1 1 0 0.8250 1 1 1 0 1 1 0 0.0250
0 1 1 0 1 1 1 0.8125 1 1 1 0 1 1 1 0.0125
0 1 1 1 0 0 0 0.8000 1 1 1 1 0 0 0 0
0 1 1 1 0 0 1 0.7875 1 1 1 1 0 0 1 0
0 1 1 1 0 1 0 0.7750 1 1 1 1 0 1 0 0
0 1 1 1 0 1 1 0.7625 1 1 1 1 0 1 1 0
0 1 1 1 1 0 0 0.7500 1 1 1 1 1 0 0 0
0 1 1 1 1 0 1 0.7375 1 1 1 1 1 0 1 0
0 1 1 1 1 1 0 0.7250 1 1 1 1 1 1 0 0
0 1 1 1 1 1 1 0.7125 1 1 1 1 1 1 1 Off
Table 4. IMVP-6.5 Output Voltage VID DAC Codes (continued)
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 27
Suspend Mode
When the processor enters low-power deeper sleep
mode, the IMVP-6.5 CPU sets the VID DAC code to a
lower output voltage and drives DPRSLPVR high. The
MAX17030/MAX17036 respond by slewing the internal
target voltage to the new DAC code, switching to single-
phase operation, and letting the output voltage gradual-
ly drift down to the deeper sleep voltage. During the
transition, the MAX17030/MAX17036 blank both the
upper and lower PWRGD and CLKEN thresholds until
20μs after the internal target reaches the deeper sleep
voltage. Once the 20μs timer expires, the MAX17030/
MAX17036 reenable the lower PWRGD and CLKEN
threshold, but keep the upper threshold blanked.
Output-Voltage-Transition Timing
At the beginning of an output-voltage transition, the
MAX17030/MAX17036 blank both PWRGD thresholds,
preventing the PWRGD open-drain output from chang-
ing states during the transition. The controller enables
the lower PWRGD threshold approximately 20μs after
the slew-rate controller reaches the target output volt-
age, but the upper PWRGD threshold is enabled only if
the controller remains in forced-PWM operation. If the
controller enters pulse-skipping operation, the upper
PWRGD threshold remains blanked. The slew rate (set
by resistor RTIME) must be set fast enough to ensure
that the transition can be completed within the maxi-
mum allotted time.
The MAX17030/MAX17036 automatically control the cur-
rent to the minimum level required to complete the transi-
tion. The total transition time depends on RTIME, the
voltage difference, and the accuracy of the slew-rate
controller (CSLEW accuracy). The slew rate is not depen-
dent on the total output capacitance, as long as the
surge current is less than the current limit. For all dynam-
ic VID transitions, the transition time (tTRAN) is given by:
where dVTARGET/dt = 12.5mV/μs ×71.5kΩ/RTIME is the
slew rate, VOLD is the original output voltage, and VNEW
is the new target voltage. See TIME Slew-Rate
Accuracy in the
Electrical Characteristics
for slew-rate
limits. For soft-start and shutdown, the controller auto-
matically reduces the slew rate to 1/4.
The average inductor current per phase required to
make an output-voltage transition is:
where dVTARGET/dt is the required slew rate, COUT is
the total output capacitance, and ηTOTAL is the number
of active phases.
Deeper Sleep Transitions
When DPRSLPVR goes high, the MAX17030/MAX17036
immediately disable phases 2 and 3 (DH2, DL2 forced
low, PWM3 three-state, DRSKP low), and enter pulse-
skipping operation (see Figures 5 and 6). If the VIDs are
set to a lower voltage setting, the output drops at a rate
determined by the load and the output capacitance. The
internal target still ramps as before, and PWRGD
remains blanked high impedance until 20μs after the
output voltage reaches the internal target. Once this
time expires, PWRGD monitors only the lower threshold:
•Fast C4E Deeper Sleep Exit: When exiting deeper
sleep (DPRSLPVR pulled low) while the output volt-
age still exceeds the deeper sleep voltage, the
MAX17030/MAX17036 quickly slew (50mV/μs min
regardless of RTIME setting) the internal target volt-
age to the DAC code provided by the processor as
long as the output voltage is above the new target.
The controller remains in skip mode until the output
voltage equals the internal target. Once the internal
target reaches the output voltage, phase 2 is
enabled. The controller blanks PWRGD and CLKEN
(forced high impedance) until 20μs after the transi-
tion is completed. See Figure 5.
•Standard C4 Deeper Sleep Exit: When exiting
deeper sleep (DPRSLPVR pulled low) while the out-
put voltage is regulating to the deeper sleep volt-
age, the MAX17030/MAX17036 immediately
activate all enabled phases and ramp the output
voltage to the LFM DAC code provided by the
processor at the slew rate set by RTIME. The con-
troller blanks PWRGD and CLKEN (forced high
impedance) until 20μs after the transition is com-
pleted. See Figure 6.
ICdV dt
LOUT
TOTAL TARGET
≅×
()
η
tVV
dV dt
TRAN NEW OLD
TARGET
=−
()
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
28 ______________________________________________________________________________________
CPU CORE
VOLTAGE
INTERNAL
PWM CONTROL
VID (D0–D6)
DPRSLPVR
ACTUAL VOUT
INTERNAL TARGET
DEEPER SLEEP VID
BLANK HIGH-Z
tBLANK
20μs typ
tBLANK
20μs typ
BLANK HI-ZBLANK HIGH THRESHOLD ONLY
BLANK LOW BLANK LOBLANK HIGH THRESHOLD ONLY
SET TO 1.5V MIN TRACKS INTERNAL TARGET
DO NOT CARE (DPRSLPVR DOMINATES STATE)
1-PHASE SKIP (DH1 ACTIVE, DH2, DL2 FORCED LOW, PWM3 THREE-STATE)
NO PULSES: VOUT > VTARGET
FORCED-PWM
OVP
DH2
DH1
PWM3
PWRGD
PSI
CLKEN
Figure 5. C4E (C4 Early Exit) Transition
DPRSLPVR
INTERNAL
PWM CONTROL
DH1
OVP
CPU CORE
VOLTAGE INTERNAL
TARGET
ACTUAL VOUT
PSI
VID (D0–D6)
ACTIVE VID
LFM VID
DPRSLP VID
DH2
PWM3
tBLANK
20μs TYP
tBLANK
20μs TYP
SET TO 1.5V MIN TRACKS INTERNAL TARGET
NO PULSES: VOUT > VTARGET
1-PHASE SKIP (DH1 ACTIVE, DH2, DL2 FORCED LOW, PWM3 THREE-STATE)
DO NOT CARE (DPRSLPVR DOMINATES STATE)
FORCED-PWM
DEEPER SLEEP VID LFM VID
PWRGD
CLKEN BLANK LOW
BLANK HIGH THRESHOLD ONLY
BLANK HIGH THRESHOLD ONLY
BLANK HIGH-Z
BLANK LOW
BLANK HIGH-Z
Figure 6. Standard C4 Transition
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 29
PSI Transitions
When PSI is pulled low, the MAX17030/MAX17036
immediately disable phase 3 (PWM3 three-state,
DRSKP forced low) and enter 2-phase PWM operation
(see Figure 7). When PSI is pulled high, the MAX17030/
MAX17036 enable phase 3.
Forced-PWM Operation (Normal Mode)
During soft-shutdown and normal operation—when the
CPU is actively running (DPRSLPVR = low, Table 5)—
the MAX17030/MAX17036 operate with the low-noise,
forced-PWM control scheme. Forced-PWM operation
disables the zero-crossing comparators of all active
phases, forcing the low-side gate-drive waveforms to
constantly be the complement of the high-side gate-
drive waveforms. This keeps the switching frequency
constant and allows the inductor current to reverse
under light loads, providing fast, accurate negative out-
put-voltage transitions by quickly discharging the output
capacitors.
Forced-PWM operation comes at a cost: the no-load
+5V bias supply current remains between 10mA to
50mA per phase, depending on the external MOSFETs
and switching frequency. To maintain high efficiency
under light-load conditions, the processor can switch
the controller to a low-power pulse-skipping control
scheme by entering suspend mode.
PSI determines how many phases are active when oper-
ating in forced-PWM mode (DPRSLPVR = low). When PSI
is pulled low, phases 1 and 2 remain active but phase 3
is disabled (PWM3 three-state, DRSKP forced low).
Light-Load Pulse-Skipping Operation
(Deeper Sleep)
During soft-start and normal operation when
DPRSLPVR is pulled high, the MAX17030/MAX17036
operate with a single-phase pulse-skipping mode. The
pulse-skipping mode enables the driver’s zero-crossing
comparator, so the controller pulls DL1 low when its cur-
rent-sense inputs detect “zero” inductor current. This
keeps the inductor from discharging the output capaci-
tors and forces the controller to skip pulses under light-
load conditions to avoid overcharging the output.
CPU FREQ
CPU LOAD
CPU CORE
VOLTAGE
VID (D0–D6)
PWRGD
PWM3
DH2
DH1
PSI
CLKEN
tBLANK
20μs typ
tBLANK
20μs typ
BLANK HIGH-Z
PWM3 THREE-STATE
180° OUT-OF-PHASE
BLANK LOW
BLANK HIGH-Z
BLANK LOW
Figure 7. PSI Transition
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
30 ______________________________________________________________________________________
When pulse-skipping, the controller blanks the upper
PWRGD and CLKEN thresholds. Upon entering pulse-
skipping operation, the controller temporarily sets the
OVP threshold to 1.5V, preventing false OVP faults
when the transition to pulse-skipping operation coin-
cides with a VID code change. Once the error amplifier
detects that the output voltage is in regulation, the OVP
threshold tracks the selected VID DAC code. The
MAX17030/MAX17036 automatically use forced-PWM
operation during soft-start and soft shutdown, regard-
less of the DPRSLPVR and PSI configuration.
Automatic Pulse-Skipping Switchover
In skip mode (DPRSLPVR = high), an inherent automatic
switchover to PFM takes place at light loads (Figure 8).
This switchover is affected by a comparator that trun-
cates the low-side switch on-time at the inductor cur-
rent’s zero crossing. The zero-crossing comparator
senses the inductor current across the low-side
MOSFETs. Once VLX drops below the zero-crossing
comparator threshold (see the
Electrical Characteristics
),
the comparator forces DL low. This mechanism causes
the threshold between pulse-skipping PFM and non-
skipping PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current
operation. The PFM/PWM crossover occurs when the
load current of each phase is equal to 1/2 the peak-to-
peak ripple current, which is a function of the inductor
value (Figure 8). For a battery input range of 7V to 20V,
this threshold is relatively constant, with only a minor
dependence on the input voltage due to the typically
low duty cycles. The total load-current at the PFM/PWM
crossover threshold (ILOAD(SKIP)) is approximately:
Power-Up Sequence (POR, UVLO)
The MAX17030/MAX17036 are enabled when SHDN is
driven high (Figure 9). The reference powers up first.
Once the reference exceeds its undervoltage-lockout
(UVLO) threshold, the internal analog blocks are turned
on and masked by a 150μs one-shot delay. The PWM
controller then begins switching.
ITV
L
VV
V
LOAD SKIP SW OUT IN OUT
IN
()
=⎛
⎝
⎜⎞
⎠
⎟×
⎛
⎝
⎜⎞
-
2⎠⎠
⎟
IPEAK
ILOAD = IPEAK/2
INDUCTOR CURRENT
TIME
0
L
VIN – VOUT
Δt
ΔI
=
ON-TIME
Figure 8. Pulse-Skipping/Discontinuous Crossover Point
FORCED-PWM
tBLANK
20μs TYP
tBLANK
60μs TYP
tBLANK
5ms TYP tBLANK
20μs TYP
VID (D0–D6)
VCORE
IMVPOK
INTERNAL
PWM CONTROL
VCC
SOFT-START
1/4 SLEW RATE SET
BY RTIME
SHDN
IGNORE
VID
IGNORE
VID
PULSE-SKIPPING
CLKEN
SOFT-SHUTDOWN
1/4 SLEW RATE SET
BY RTIME
Figure 9. Power-Up and Shutdown Sequence Timing Diagram
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 31
Power-on reset (POR) occurs when VCC rises above
approximately 2V, resetting the fault latch and prepar-
ing the controller for operation. The VCC UVLO circuitry
inhibits switching until VCC rises above 4.25V. The con-
troller powers up the reference once the system
enables the controller, VCC is above 4.25V, and SHDN
driven high. With the reference in regulation, the con-
troller ramps the output voltage to the boot voltage
(1.1V) at 1/4 the slew rate set by RTIME:
where dVTARGET/dt = 12.5mV/μs x 71.5kΩ/RTIME is the
slew rate. The soft-start circuitry does not use a variable
current limit, so full output current is available immedi-
ately. CLKEN is pulled low approximately 60μs after the
MAX17030/MAX17036 reach the boot voltage. At the
same time, the MAX17030/MAX17036 slew the output
to the voltage set at the VID inputs at the programmed
slew rate. PWRGD becomes high impedance approxi-
mately 5ms after CLKEN is pulled low. The MAX17030/
MAX17036 automatically operate in pulse-skipping
mode during soft-start, and use forced-PWM operation
during soft-shutdown, regardless of the DPRSLPVR and
PSI configuration.
If the VCC voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to make
valid decisions, and shuts down immediately. DH and DL
are forced low, and CSN1 10Ωdischarge FET is
enabled.
Shutdown
When SHDN goes low, the MAX17030/MAX17036
enters low-power shutdown mode. PWRGD is pulled
low immediately, and the output voltage ramps down at
1/4 the slew rate set by RTIME:
where dVTARGET/dt = 12.5mV/μs x 71.5kΩ/RTIME is the
slew rate. After the output voltage drops to 12.5mV, the
MAX17030/MAX17036 shut down completely—the dri-
vers are disabled (DL1 and DL2 driven low, PWM3 is
three-state, and DRSKP low), the reference turns off,
10ΩCSN1 discharge FET is turned on, and the supply
current drops below 1μA.
When an undervoltage fault condition activates the shut-
down sequence, the protection circuitry sets the fault
latch to prevent the controller from restarting. To clear
the fault latch and reactivate the controller, toggle SHDN
or cycle VCC power below 0.5V.
Current Monitor (IMON)
The MAX17030/MAX17036 include a unidirectional
transconductance amplifier that sources current pro-
portional to the positive current-sense voltage. The
IMON output current is defined by:
IIMON = Gm(IMON) x Σ(VCSP - VCSN)
where Gm(IMON) = 1.6mS (typ) and the IMON current is
unidirectional (sources current out of IMON only) for
positive current-sense values. For negative current-
sense voltages, the IMON current is zero.
Connect an external resistor between IMON and GNDS
to create the desired IMON gain based on the following
equation:
RIMON = 0.9V/(IMAX x RSENSE(MIN) x Gm(IMON_MIN))
where IMAX is defined in the Current Monitor section of
the Intel IMVP-6.5 specification and based on discrete
increments (10A, 20A, 30A, 40A, etc.), RSENSE(MIN) is
the minimum effective value of the current-sense ele-
ment (sense resistor or inductor DCR) that is used to
provide the current-sense voltage, and Gm(IMON_MIN)
is the minimum transconductance amplifier gain as
defined in the
Electrical Characteristics
.
The IMON voltage is internally clamped to a maximum
of 1.1V (typ), preventing the IMON output from exceed-
ing the IMON voltage rating even under overload or
short-circuit conditions. When the controller is disabled,
IMON is pulled to ground.
The transconductance amplifier and voltage clamp are
internally compensated, so IMON cannot directly drive
large capacitance values. To filter the IMON signal, use
an RC filter as shown in Figure 1.
Temperature Comparator (
VRHOT
)
The MAX17030/MAX17036 also feature an independent
comparator with an accurate threshold (VHOT) that
tracks the analog supply voltage (VHOT = 0.3VCC). This
makes the thermal trip threshold independent of the VCC
supply voltage tolerance. Use a resistor- and thermistor-
divider between VCC and GND to generate a voltage-
regulator overtemperature monitor. Place the thermistor
as close to the MOSFETs and inductors as possible.
Fault Protection (Latched)
Output Overvoltage Protection
The overvoltage-protection (OVP) circuit is designed to
protect the CPU against a shorted high-side MOSFET
by drawing high current and blowing the battery fuse.
The MAX17030/MAX17036 continuously monitor the
output for an overvoltage fault. An OVP fault is detected
if the output voltage exceeds the set VID DAC voltage
by more than 300mV, or the fixed 1.5V (typ) threshold
tV
dV dt
TRAN SHDN OUT
TARGET
()
=
()
4
tV
dV dt
TRAN START BOOT
TARGET
()
=
()
4
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
32 ______________________________________________________________________________________
during a downward VID transition in skip mode. During
pulse-skipping operation (DPRSLPVR = high), the OVP
threshold tracks the VID DAC voltage as soon as the
output is in regulation; otherwise, the fixed 1.5V (typ)
threshold is used.
When the OVP circuit detects an overvoltage fault while
in multiphase mode (DPRSLPVR = low, PSI = high), the
MAX17030/MAX17036 immediately force DL1 and DL2
high, PWM3 low, and DRSKP high; and pull DH1 and
DH2 low. This action turns on the synchronous-rectifier
MOSFETs with 100% duty and, in turn, rapidly dis-
charges the output filter capacitor and forces the output
low. If the condition that caused the overvoltage (such
as a shorted high-side MOSFET) persists, the battery
fuse blows. Toggle SHDN or cycle the VCC power supply
below 0.5V to clear the fault latch and reactivate the con-
troller.
When an overvoltage fault occurs while in 1-phase
operation (DPRSLPVR = high, or PSI = low), the
MAX17030/MAX17036 immediately force DL1 high and
pull DH1 low. DL2 and DH2 remain low as phase 2 was
disabled. DL2 does not react.
Overvoltage protection can be disabled through the no-
fault test mode (see the
No-Fault Test Mode
section).
Output Undervoltage Protection
If the MAX17030/MAX17036 output voltage is 400mV
below the target voltage, the controller activates the
shutdown sequence and sets the fault latch. Once the
output voltage ramps down to 12.5mV, it forces the DL1
and DL2 low and pulls DH1 and DH2 low, three-states
PWM3, and sets DRSKP low 10ΩCSN1 discharge FET
is turned on. Toggle SHDN or cycle the VCC power
supply below 0.5V to clear the fault latch and reactivate
the controller.
UVP can be disabled through the no-fault test mode
(see the
No-Fault Test Mode
section).
Thermal-Fault Protection
The MAX17030/MAX17036 feature a thermal fault-pro-
tection circuit. When the junction temperature rises
above +160°C, a thermal sensor sets the fault latch and
forces the DL1 and DL2 low and pulls DH1 and DH2
low, three-states PWM3, sets DRSKP low, and enables
10ΩCSN1 discharge FET on. Toggle SHDN or cycle
the VCC power supply below 0.5V to clear the fault
latch and reactivate the controller after the junction tem-
perature cools by 15°C.
Thermal shutdown can be disabled through the no-fault
test mode (see the
No-Fault Test Mode
section).
No-Fault Test Mode
The latched fault-protection features can complicate
the process of debugging prototype breadboards since
there are (at most) a few milliseconds in which to deter-
mine what went wrong. Therefore, a “no-fault” test
mode is provided to disable the fault protection—over-
voltage protection, undervoltage protection, and ther-
mal shutdown. Additionally, the test mode clears the
fault latch if it has been set. The no-fault test mode is
entered by forcing 11V to 13V on SHDN.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moder-
ate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large VIN -
VOUT differential exists. The high-side gate drivers (DH)
source 2.7A and sink 2.2A, and the low-side gate dri-
vers (DL) source 2.7A and sink 8A. This ensures robust
gate drive for high-current applications. The DH_ float-
ing high-side MOSFET drivers are powered by internal
boost switch charge pumps at BST_, while the DL_ syn-
chronous-rectifier drivers are powered directly by the
5V bias supply (VDD).
Adaptive dead-time circuits monitor the DL and DH dri-
vers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
A low-resistance, low-inductance path from the DL and
DH drivers to the MOSFET gates is required for the
adaptive dead-time circuits to work properly; otherwise,
the sense circuitry in the MAX17030/MAX17036 inter-
prets the MOSFET gates as “off” while charge actually
remains. Use very short, wide traces (50 mils to 100
mils wide if the MOSFET is 1in from the driver).
The DL low on-resistance of 0.25Ω(typ) helps prevent
DL from being pulled up due to capacitive coupling from
the drain to the gate of the low-side MOSFETs when the
inductor node (LX) quickly switches from ground to VIN.
The capacitive coupling between LX and DL created by
the MOSFET’s gate-to-drain capacitance (CRSS), gate-
to-source capacitance (CISS - CRSS), and additional
board parasitics should not exceed the following mini-
mum threshold to prevent shoot-through currents:
Adding a 4700pF between DL and power ground (CNL
in Figure 10), close to the low-side MOSFETs, greatly
reduces coupling. Do not exceed 22nF of total gate
capacitance to prevent excessive turn-off delays.
VVC
C
GS TH IN MAX RSS
ISS
() ( )
>⎛
⎝
⎜⎞
⎠
⎟
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 33
Shoot-through currents can also be caused by a com-
bination of fast high-side MOSFETs and slow low-side
MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5Ωin series with BST
slows down the high-side MOSFET turn-on time, elimi-
nating the shoot-through currents without degrading the
turn-off time (RBST in Figure 10). Slowing down the
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
Multiphase Quick-PWM
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency and
inductor operating point (ripple-current ratio). The pri-
mary design trade-off lies in choosing a good switching
frequency and inductor operating point, and the following
four factors dictate the rest of the design:
•Input voltage range: The maximum value
(VIN(MAX)) must accommodate the worst-case high
AC adapter voltage. The minimum value (VIN(MIN))
must account for the lowest input voltage after
drops due to connectors, fuses, and battery selec-
tor switches. If there is a choice at all, lower input
voltages result in better efficiency.
•Maximum load current: There are two values to
consider. The peak load current (ILOAD(MAX)) deter-
mines the instantaneous component stresses and
filtering requirements, and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continu-
ous load current (ILOAD) determines the thermal
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components. Modern notebook CPUs gen-
erally exhibit ILOAD = ILOAD(MAX) x 80%.
For multiphase systems, each phase supports a
fraction of the load, depending on the current bal-
ancing. When properly balanced, the load current is
evenly distributed among each phase:
where ηTOTAL is the total number of active phases.
•Switching frequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
are proportional to frequency and VIN2. The opti-
mum frequency is also a moving target, due to
rapid improvements in MOSFET technology that are
making higher frequencies more practical.
•Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output noise. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency and higher
output noise due to increased ripple current. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduc-
tion (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction bene-
fit. The optimum operating point is usually found
between 30% and 50% ripple current. for a multi-
phase core regulator, select an LIR value of ~0.4.
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
where ηTOTAL is the total number of phases.
LVV
fI LIR
V
V
TOTAL IN OUT
SW LOAD MAX
OUT
=−
⎛
⎝
⎜⎞
⎠
⎟
η
() IIN
⎛
⎝
⎜⎞
⎠
⎟
II
LOAD PHASE LOAD
TOTAL
()
=η
BST_
DH_
LX_
(RBST)*
INPUT (VIN)
CBST
NH
CBYP
L
(RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE
SWITCHING NODE RISE TIME.
(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENT.
DL_
PGND
NL
(CNL)*
VDD
MAX17030/MAX17036
Figure 10. Gate Drive Circuit
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
34 ______________________________________________________________________________________
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. The core
must not to saturate at the peak inductor current (IPEAK):
Output Capacitor Selection
Output capacitor selection is determined by the con-
troller stability requirements, and the transient soar and
sag requirements of the application.
Output Capacitor ESR
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
In CPU VCORE converters and other applications where
the output is subject to large load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low under a
load transient. Ignoring the sag due to finite capacitance:
The output ripple voltage of a step-down controller
equals the total inductor ripple current multiplied by the
output capacitor’s ESR. When operating multiphase
systems out-of-phase, the peak inductor currents of
each phase are staggered, resulting in lower output rip-
ple voltage by reducing the total inductor ripple current.
For multiphase operation, the maximum ESR to meet
ripple requirements is:
where ηTOTAL is the total number of active phases and
fSW is the switching frequency per phase. The actual
capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry
of the capacitor technology. Thus, the capacitor is usu-
ally selected by ESR and voltage rating rather than by
capacitance value (this is true of polymer types).
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent VSAG and VSOAR from causing prob-
lems during load transients. Generally, once enough
capacitance is added to meet the overshoot require-
ment, undershoot at the rising load edge is no longer a
problem (see the VSAG and VSOAR equations in the
Transient Response
section).
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
where:
and:
where COUT is the total output capacitance, RESR is the
total equivalent series resistance, RDROOP is the volt-
age-positioning gain, and RPCB is the parasitic board
resistance between the output capacitors and sense
resistors.
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum, SANYO POSCAP, and Panasonic SP
capacitors in widespread use at the time of publication
have typical ESR zero frequencies below 50kHz. In the
standard application circuit, the ESR needed to support
a 30mVP-P ripple is 30mV/(40A x 0.3) = 2.5mΩ. Four
330μF/2.5V Panasonic SP (type SX) capacitors in paral-
lel provide 1.5mΩ(max) ESR. With a 2mΩdroop and
0.5mΩPCB resistance, the typical combined ESR
results in a zero at 30kHz.
Ceramic capacitors have a high ESR zero frequency, but
applications with significant voltage positioning can take
advantage of their size and low ESR. When using only
ceramic output capacitors, output overshoot (VSOAR)
typically determines the minimum output capacitance
requirement. Their relatively low capacitance value
favors high switching-frequency operation with small
inductor values to minimize the energy transferred from
inductor to capacitor during load-step recovery.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feedback
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is not
enough voltage ramp in the output-voltage signal. This
“fools” the error comparator into triggering a new cycle
immediately after the minimum off-time period has
expired. Double pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
RRR R
EFF ESR DROOP PCB
=+ +
fRC
ESR EFF OUT
=1
2π
ff
ESR SW
≤π
RVf L
VVV
V
ESR IN SW
IN TOTAL OUT OUT RI
≤−
()
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
ηPPPLE
RR V
I
ESR PCB STEP
LOAD MAX
+
()
≤Δ()
IILIR
PEAK LOAD MAX
TOTAL
=⎛
⎝
⎜⎞
⎠
⎟+
⎛
⎝
⎜⎞
⎠
⎟
()
η12
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 35
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
cause the output voltage to rise above or fall below the
tolerance limits.
The easiest method for checking stability is to apply a
very fast 10% to 90% max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Transient Response
The inductor ripple current impacts transient-response
performance, especially at low VIN - VOUT differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output fil-
ter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty fac-
tor, which can be calculated from the on-time and mini-
mum off-time. For a dual-phase controller, the
worst-case output sag voltage can be determined by:
and:
where tOFF(MIN) is the minimum off-time (see the
Electrical Characteristics
), TSW is the programmed
switching period, and ηTOTAL is the total number of
active phases. K = 66% when NPH = 3, and K = 100%
when NPH = 2. VSAG must be less than the transient
droop ΔILOAD(MAX) x RDROOP.
The capacitive soar voltage due to stored inductor
energy can be calculated as:
where ηTOTAL is the total number of active phases. The
actual peak of the soar voltage is dependent on the
time where the decaying ESR step and rising capaci-
tive soar is at its maximum. This is best simulated or
measured. For the MAX17036 with transient suppres-
sion, contact Maxim directly for application support to
determine the output capacitance requirement.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
The multiphase Quick-PWM controllers operate out-of-
phase, reducing the RMS input. For duty cycles less
than 100%/ηOUTPH per phase, the IRMS requirements
can be determined by the following equation:
where ηTOTAL is the total number of out-of-phase
switching regulators. The worst-case RMS current
requirement occurs when operating with VIN =
2ηTOTALVOUT. At this point, the above equation simpli-
fies to IRMS = 0.5 x ILOAD/ηTOTAL. Choose an input
capacitor that exhibits less than +10°C temperature rise
at the RMS input current for optimal circuit longevity.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters.
High-Side MOSFET Power Dissipation
The conduction loss in the high-side MOSFET (NH) is a
function of the duty factor, with the worst-case power
dissipation occurring at the minimum input voltage:
where ηTOTAL is the total number of phases.
Calculating the switching losses in the high-side
MOSFET (NH) is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source
inductance, and PCB layout characteristics. The follow-
ing switching-loss calculation provides only a very
rough estimate and is no substitute for breadboard
evaluation, preferably including verification using a
thermocouple mounted on NH:
where COSS is the NHMOSFET’s output capacitance,
QG(SW) is the charge needed to turn on the NH
MOSFET, and IGATE is the peak gate-drive source/sink
current (2.2A typ).
PD (NH Switching) = VI f
IN LOAD SW
TOTAL
η
⎛
⎝
⎜⎞
⎠
⎟
QQ
I
GSW
GATE
()
⎛
⎝
⎜⎞
⎠
⎟
+CVf
OSS IN SW
2
2
PD (NH Resistive) = V
V
I
OUT
IN
LOAD
TOTA
⎛
⎝
⎜⎞
⎠
⎟ηLL DS ON
R
⎛
⎝
⎜⎞
⎠
⎟
2
()
II
VVV
RMS LOAD
TOTAL IN TOTAL OUT IN TOT
=⎛
⎝
⎜⎞
⎠
⎟−
ηηη
AAL OUT
V
()
VIL
CV
SOAR
LOAD MAX
TOTAL OUT OUT
≈
()
Δ()
2
2η
Ttt
MIN ON OFF MIN
=+()
VCV
T
KT
SAG TOTAL OUT OUT
MIN
≈
()
×
LI
LOAD(MAX)
2
Δ
2ηSSW MIN
T−
⎡
⎣⎤
⎦
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
36 ______________________________________________________________________________________
The optimum high-side MOSFET trades the switching
losses with the conduction (RDS(ON)) losses over the
input voltage range. Ideally, the losses at VIN(MIN)
should be roughly equal to losses at VIN(MAX) , with
lower losses in between. If VIN does not vary over a
wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
Low-Side MOSFET Power Dissipation
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than ILOAD(MAX)
but are not quite high enough to exceed the current limit
and cause the fault latch to trip. To protect against this
possibility, the circuit can be overdesigned to tolerate:
where IVALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-size heatsink to handle the overload
power dissipation.
Choose a low-side MOSFET that has the lowest possible
on-resistance (RDS(ON)), comes in a moderate-sized
package (i.e., one or two thermally enhanced 8-pin SOs),
and is reasonably priced. Make sure that the DL gate dri-
ver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-to-
drain capacitor caused by the high-side MOSFET turning
on; otherwise, cross-conduction problems might occur
(see the
MOSFET Gate Drivers
section).
The optional Schottky diode (DL) should have a low for-
ward voltage and be able to handle the load current
per phase during the dead times.
Boost Capacitors
The boost capacitors (CBST) must be selected large
enough to handle the gate-charging requirements of
the high-side MOSFETs. Select the boost capacitors to
avoid discharging the capacitor more than 200mV while
charging the high-side MOSFETs’ gates:
where N is the number of high-side MOSFETs used for
one regulator, and QGATE is the gate charge specified
in the MOSFET’s data sheet. For example, assume (1)
FDS6298 n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle FDS6298 has a maximum gate charge of 19nC
(VGS = 5V). Using the above equation, the required
boost capacitance would be:
Selecting the closest standard value; this example
requires a 0.1μF ceramic capacitor.
Current Limit and Slew-Rate Control
(TIME and ILIM)
TIME and ILIM are used to control the slew rate and
current limit. TIME regulates to a fixed 2.0V. The
MAX17030/MAX17036 use the TIME source current to
set the slew rate (dVTARGET/dt). The higher the source
current, the faster the output-voltage slew rate:
where RTIME is the sum of resistance values between
TIME and ground.
The ILIM voltage determines the valley current-sense
threshold. When ILIM = VCC, the controller uses the
22.5mV preset current-limit threshold. In an adjustable
design, ILIM is connected to a resistive voltage-
divider connected between TIME and ground. The dif-
ferential voltage between TIME and ILIM sets the cur-
rent-limit threshold (VLIMIT), so the valley current-sense
threshold:
This allows design flexibility since the DCR sense circuit
or sense resistor does not have to be adjusted to meet
the current limit as long as the current-sense voltage
never exceeds 50mV. Keeping VLIMIT between 20mV to
40mV leaves room for future current-limit adjustment.
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at ILOAD(MAX) minus
half the ripple current; therefore:
II LIR
VALLEY LOAD MAX
>−
⎛
⎝
⎜⎞
⎠
⎟
()
12
VVV
LIMIT TIME ILIM
=−
10
dV dt mV μs k
R
TARGET TIME
=×
⎛
⎝
⎜⎞
⎠
⎟
12 5 71 5
..Ω
CnC
mV μF
BST =×=
110
200 005.
CNQ
mV
BST GATE
=×
200
II
I
LOAD TOTAL VALLEY MAX INDUCTOR
=+
⎛
⎝
⎜⎞
⎠
⎟
η()
Δ
2
() ()
=+ηTOTAL VALLEY MAX LOAD MAX
IILIR
22
⎛
⎝
⎜⎞
⎠
⎟
PD (NL Resistive) = 1−⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
V
V
OUT
IN MAX()
⎤⎤
⎦
⎥
⎥
⎛
⎝
⎜⎞
⎠
⎟
IR
LOAD
TOTAL DS ON
η
2
()
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
______________________________________________________________________________________ 37
where:
where RSENSE is the sensing resistor or effective induc-
tor DCR.
Voltage Positioning and
Loop Compensation
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the out-
put capacitance and processor’s power-dissipation
requirements. The MAX17030/MAX17036 use a
transconductance amplifier to set the transient and DC
output voltage droop (Figure 3) as a function of the
load. This adjustability allows flexibility in the selected
current-sense resistor value or inductor DCR, and
allows smaller current-sense resistance to be used,
reducing the overall power dissipated.
Steady-State Voltage Positioning
Connect a resistor (RFB) between FB and VOUT to set
the DC steady-state droop (load line) based on the
required voltage-positioning slope (RDROOP):
where the effective current-sense resistance (RSENSE)
depends on the current-sense method (see the
Current
Sense
section), and the voltage positioning amplifier’s
transconductance (Gm(FB)) is typically 400μS as
defined in the
Electrical Characteristics
table. The con-
troller sums together the input signals of the current-
sense inputs (CSP_, CSN_).
When the inductors’ DCR is used as the current-sense
element (RSENSE = RDCR), each current-sense input
should include an NTC thermistor to minimize the tem-
perature dependence of the voltage-positioning slope.
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Refer to the MAX17030 Evaluation Kit specifi-
cation for a layout example and follow these guidelines
for good PCB layout:
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
2) Connect all analog grounds to a separate solid cop-
per plane, which connects to the ground pin of the
Quick-PWM controller. This includes the VCC bypass
capacitor, FB, and GNDS bypass capacitors.
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCB (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mΩ
of excess trace resistance causes a measurable
efficiency penalty.
4) Keep the high current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
5) CSP_ and CSN_ connections for current limiting
and voltage positioning must be made using Kelvin
sense connections to guarantee the current-sense
accuracy.
6) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
7) Route high-speed switching nodes away from sen-
sitive analog areas (FB, CSP_, CSN_, etc.).
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (low-side MOSFET source, CIN,
COUT, and D1 anode). If possible, make all these
connections on the top layer with wide, copper-
filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50mils to 100mils wide if the MOSFET is 1in
from the controller IC).
3) Group the gate-drive components (BST diodes and
capacitors, VDD bypass capacitor) together near
the controller IC.
RR
RG
FB DROOP
SENSE m FB
=
()
IV
R
VALLEY LIMIT
SENSE
=
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
38 ______________________________________________________________________________________
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
40 TQFN-EP T4055-2 21-0140
Chip Information
PROCESS: BiCMOS
4) Make the DC-DC controller ground connections as
shown in the standard application circuits. This dia-
gram can be viewed as having four separate ground
planes: input/output ground, where all the high-
power components go; the power ground plane,
where the GND pin and VDD bypass capacitor go;
the master’s analog ground plane, where sensitive
analog components, the master’s GND pin and VCC
bypass capacitor go; and the slave’s analog ground
plane, where the slave’s GND pin and VCC bypass
capacitor go. The master’s GND plane must meet
the GND plane only at a single point directly
beneath the IC. Similarly, the slave’s GND plane
must meet the GND plane only at a single point
directly beneath the IC. The respective master and
slave ground planes should connect to the high-
power output ground with a short metal trace from
GND to the source of the low-side MOSFET (the
middle of the star ground). This point must also be
very close to the output capacitor ground terminal.
5) Connect the output power planes (VCORE and sys-
tem ground planes) directly to the output filter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC-DC converter circuit as
close to the CPU as is practical.
MAX17030/MAX17036
1/2/3 Phase-Quick-PWM
IMVP-6.5 VID Controllers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
39
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 4/09 Initial release —
1 8/09
Updated the Pin Description, Figure 3, Table 3, and the Power-Up Sequence
(POR, UVLO), Shutdown Output Undervoltage Protection, and Thermal-Fault
Protection sections.
13, 14, 19,
25, 31, 32
