©2002 Fairchild Semiconductor Corporation
January 2002
Rev. B
IRF640N/IRF640NS/IRF640NL
IRF640N/IRF640NS/IRF640NL
N-Channel Power MOSFETs
200V, 18A, 0.15
Ω
Features
• Ultra Low On-Resistance
-r
DS(ON)
= 0.102
Ω
(Typ)
,
V
GS
=
10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER
©
Electrical Models
- Spice and SABER
©
Thermal Impedance Models
• Peak Current vs Pulse Width Curve
• UIS Rateing Curve
MOSFET Maximum Ratings
T
A
= 25°C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
V
DSS
Drain to Source Voltage 200 V
V
GS
Gate to Source Voltage
±
20 V
I
D
Drain Current
18 A
Continuous (T
C
= 25
o
C, V
GS
= 10V)
Continuous (T
C
= 100
o
C, V
GS
= 10V) 13 A
Pulsed Figure 4 A
E
AS
Single Pulse Avalanche Energy (Note 1) 247 mJ
P
D
Power dissipation
Derate above 25
o
C
150
1.0
W
W/
o
C
T
J
, T
STG
Operating and Storage Temperature -55 to 175
o
C
R
θ
JC
Thermal Resistance Junction to Case TO-220, TO-262, TO-263 1.0
o
C/W
R
θ
JA
Thermal Resistance Junction to Ambient TO-220, TO-262, TO-263 62
o
C/W
R
θ
JA
Thermal Resistance Junction to Ambient TO-263, 1in
2
copper pad area 40
o
C/W
Device Marking Device Package Reel Size Tape Width Quantity
640N IRF640NS TO-263AB 330mm 24mm 800 units
640N IRF640NL TO-262AA Tube N/A 50
640N IRF640N TO-220AB Tube N/A 50
D
G
S
TO-263 TO-220
GATE
SOURCE
DRAIN
(FLANGE)
DRAIN
(FLANGE)
DRAIN
SOURCE
GATE
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
TO-262
©2002 Fairchild Semiconductor Corporation Rev. B
IRF640N/IRF640NS/IRF640NL
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
(V
GS
= 10V)
Drain-Source Diode Characteristics
Notes:
1:
Starting T
J
= 25°C, L = 4.2mH, I
AS
= 11A.
2:
Pulse width
≤
400
µ
s; duty cycle
≤
2%.
Symbol Parameter Test Conditions Min Typ Max Units
B
VDSS
Drain to Source Breakdown Voltage I
D
= 250
µ
A, V
GS
= 0V 200 - - V
I
DSS
Zero Gate Voltage Drain Current V
DS
= 200V, V
GS
= 0V - - 25
µ
A
V
DS
= 160V T
C
= 150
o
- - 250
I
GSS
Gate to Source Leakage Current V
GS
=
±
20V - -
±
100 nA
V
GS(TH)
Gate to Source Threshold Voltage V
GS
= V
DS
, I
D
= 250
µ
A2-4V
r
DS(ON)
Drain to Source On Resistance I
D
= 11A, V
GS
= 10V - 0.102 0.15
Ω
g
fs
Forward Transconductance V
DS
= 50V, I
D
= 11A (Note 2) 6.8 - -
S
C
ISS
Input Capacitance
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
- 2200 - pF
C
OSS
Output Capacitance - 400 - pF
C
RSS
Reverse Transfer Capacitance - 120 - pF
Q
g(TOT)
Total Gate Charge at 20V V
GS
= 0V to 20V
V
DD
=100V
I
D
= 22A
I
g
= 1.0mA
117 152 nC
Q
g(10)
Total Gate Charge at 10V V
GS
= 0V to 10V - 64 83 nC
Q
g(TH)
Threshold Gate Charge V
GS
= 0V to 2V - 5 7 nC
Q
gs
Gate to Source Gate Charge - 9 - nC
Q
gd
Gate to Drain “Miller” Charge - 24 - nC
t
ON
Turn-On Time
V
DD
= 100V, I
D
= 11A
V
GS
= 10V, R
GS
= 2.5
Ω
- - 44 ns
t
d(ON)
Turn-On Delay Time - 10 - ns
t
r
Rise Time - 19 - ns
t
d(OFF)
Turn-Off Delay Time - 23 - ns
t
f
Fall Time - 5.5 - ns
t
OFF
Turn-Off Time - - 46 ns
V
SD
Source to Drain Diode Voltage I
SD
= 11A - - 1.3 V
t
rr
Reverse Recovery Time I
SD
= 11A, dI
SD
/dt = 100A/
µ
s - - 251 ns
Q
RR
Reverse Recovered Charge I
SD
= 11A, dI
SD
/dt = 100A/
µ
s - - 1394 nC
©2002 Fairchild Semiconductor Corporation Rev. B
IRF640N/IRF640NS/IRF640NL
Typical Characteristic
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
Figure 3. Normalized Maximum Transient Thermal Impedance
Figure 4. Peak Current Capability
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
0
5
10
15
20
25 50 75 100 125 150 175
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
0.1
1
2
10-4 10-3 10-2 10-1 100101
0.01
10-5
t, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
THERMAL IMPEDANCE
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
100
10
10-4 10-3 10-2 10-1 100101
10-5
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
300
©2002 Fairchild Semiconductor Corporation Rev. B
IRF640N/IRF640NS/IRF640NL
Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching
Capability
Figure 7. Transfer Charicteristics Figure 8. Saturation Charactoristics
Figure 9. Normalized Drain To Source On
Resistance vs Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
Typical Characteristic (Continued)
0.1
1
10
100
1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
SINGLE PULSE
100µs
10ms
1ms
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
300
200
1
10
100
0.001 0.01 0.1 1 10
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
0
10
20
30
40
2346
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = 175oC
TJ = 25oC
TJ = -55oC
5
0
10
20
30
40
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS =4.5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
VGS = 10V
VGS = 5V
0 234561
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 22A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 200
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
THRESHOLD VOLTAGE
160
0.6
0.8
1.0
1.2
©2002 Fairchild Semiconductor Corporation Rev. B
IRF640N/IRF640NS/IRF640NL
Figure 11. Normalized Drain To Source
Breakdown Voltage vs Junction Temperature
Figure 12. Capacitance vs Drain to Source
Voltage
Figure 13. Gate Charge Waveforms for Constant Gate Currents
Typical Characteristic (Continued)
0.8
0.9
1.0
1.1
1.2
1.3
-80 -40 0 40 80 120 200
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
160160 10
100
1000
10000
0.1 1 10 100
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≅ CDS + CGD
200
0
2
4
6
8
10
0 10 203040506070
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 100V
Qg, GATE CHARGE (nC)
ID = 22A
ID = 5A
WAVEFORMS IN
DESCENDING ORDER:
Test Circuits and Waveforms
Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
©2002 Fairchild Semiconductor Corporation Rev. B
IRF640N/IRF640NS/IRF640NL
Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms
Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
©2002 Fairchild Semiconductor Corporation Rev. B
IRF640N/IRF640NS/IRF640NL
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in
an application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 20
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 20 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
(EQ. 1)
PDM
TJM TA
–()
ZθJA
-------------------------------=
(EQ. 2)
RθJA 26.51 19.84
0.262 Area+()
-------------------------------------+=
Figure 20. Thermal Resistance vs Mounting
Pad Area
20
40
60
80
110
0.1
RθJA = 26.51+ 19.84/(0.262+Area)
RθJA (oC/W)
AREA, TOP COPPER AREA (in2)
©2002 Fairchild Semiconductor Corporation Rev. B
IRF640N/IRF640NS/IRF640NL
PSPICE Electrical Model
.SUBCKT IRF640N 2 1 3 ; rev 10 October 2000
CA 12 8 3.6e-9
CB 15 14 3.5e-9
CIN 6 8 2e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 225
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 5.78e-9
LSOURCE 3 7 3.92e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 83.5e-3
RGATE 9 20 7.6e-1
RLDRAIN 2 5 10
RLGATE 1 9 57.8
RLSOURCE 3 7 39.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 10e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*38),2.5))}
.MODEL DBODYMOD D (IS = 1.2e-12 RS = 5.5e-3
XTI = 5.5 TRS1 = 1e-5 TRS2 = 8e-6 + CJO = 12.5e-10 TT = 1e-7 M = 0.42)
.MODEL DBREAKMOD D (RS = 2.5 TRS1 = 1e-3 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 2.5e-9 IS = 1e-30 N = 10 M = 0.9)
.MODEL MMEDMOD NMOS (VTO = 3.14 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 7.6e-1)
.MODEL MSTROMOD NMOS (VTO = 3.68 KP = 100 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.76 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 7.6 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 =1.52e-3 TC2 = -2e-7)
.MODEL RDRAINMOD RES (TC1 = 9.8e-3 TC2 = 2.6e-5)
.MODEL RSLCMOD RES (TC1 = 3e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.3e-3 TC2 = -1.3e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.8e-3 TC2 = 1.7e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.5 VOFF= -1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF= -8.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.1 VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.1)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
©2002 Fairchild Semiconductor Corporation Rev. B
IRF640N/IRF640NS/IRF640NL
SABER Electrical Model
REV 10 October 2000
template IRF640N n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1.2e-12, rs=5.5e-3, trs1=1e-5, trs2=8e-6, cjo = 12.5e-10, m=0.42, tt = 1e-7, xti = 5.5)
dp..model dbreakmod = (rs=2.5, trs1=1e-3, trs2=-8.9e-6)
dp..model dplcapmod = (cjo = 2.5e-9, isl =10e-30, nl=10, m = 0.9)
m..model mmedmod = (type=_n, vto = 3.14, kp = 5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.68, kp = 100, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.76, kp = 0.05, is = 1e-30, tox = 1, rs = 0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8.5, voff = -1)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1, voff = -8.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.1)
c.ca n12 n8 = 3.6e-9
c.cb n15 n14 = 3.5e-9
c.cin n6 n8 = 2e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.78e-9
l.lsource n3 n7 = 3.92e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.52e-3, tc2 = -2e-7
res.rdrain n50 n16 = 83.5e-3, tc1 = 9.8e-3, tc2 = 2.6e-5
res.rgate n9 n20 = 7.6e-1
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 57.8
res.rlsource n3 n7 = 39.2
res.rslc1 n5 n51 = 1e-6, tc1 = 3e-3, tc2 = 1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 10e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.8e-3, tc2 = 1.7e-6
res.rvthres n22 n8 = 1, tc1 = -2.3e-3, tc2 = -1.3e-5
spe.ebreak n11 n7 n17 n18 = 225
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/38))** 2.5))
}
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
©2002 Fairchild Semiconductor Corporation Rev. B
IRF640N/IRF640NS/IRF640NL
SPICE Thermal Model
REV 10 October 2000
IRF640N
CTHERM1 th 6 2.8e-3
CTHERM2 6 5 4.6e-3
CTHERM3 5 4 5.5e-3
CTHERM4 4 3 9.2e-3
CTHERM5 3 2 1.7e-2
CTHERM6 2 tl 4.3e-2
RTHERM1 th 6 5e-4
RTHERM2 6 5 1.5e-3
RTHERM3 5 4 2e-2
RTHERM4 4 3 9e-2
RTHERM5 3 2 1.9e-1
RTHERM6 2 tl 2.9e-1
SABER Thermal Model
IRF640N
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.8e-3
ctherm.ctherm2 6 5 = 4.6e-3
ctherm.ctherm3 5 4 = 5.5e-3
ctherm.ctherm4 4 3 = 9.2e-3
ctherm.ctherm5 3 2 = 1.7e-2
ctherm.ctherm6 2 tl = 4.3e-2
rtherm.rtherm1 th 6 = 5e-4
rtherm.rtherm2 6 5 = 1.5e-3
rtherm.rtherm3 5 4 = 2e-2
rtherm.rtherm4 4 3 = 9e-2
rtherm.rtherm5 3 2 = 1.9e-1
rtherm.rtherm6 2 tl = 2.9e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
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