Page 10 Preliminary Information Document DL-0056 Version 1.1
Direct Rambus Clock Generator Data Sheet
Table 7 shows the logic for selecting the Powerdown
mode, using the PWRDNB input signal. PWRDNB is
active low (enabled when = 0). When PWRDNB is
disabled, the DRCG is in its Normal mode. When
PWRDNB is enabled (PWRDNB = 0), the DRCG is put
into a powered-off state, and the CLK and CLKB
outputs are both low (ground). The internal resistor
dividers ar e disconnected during Power down mode in
order to save power. This is true both for the resistor
dividers used to set VX,STOP during Clk Stop mode,
and for the resistor dividers used to set the trip points
for the input clocks.
PLL Multiplier
Table 8 shows the logic for selecting the PL L prescaler
and feedback dividers to determine the multiply ratio
for the PLL from the REFCLK input. Divider A sets the
feedback and Divider B sets the prescaler, so the PLL
output clock (PLLClk in Figure 3) is set by: PLLClk =
REF CLK * A/ B.
Distributed Loop Lock Time
After the DRCG PLL has settled, the distribu ted loop
containing the Phase Aligner must also settle. This
settling time depends o n com p onents in the distrib-
uted loop which are outside of the clock source. There-
fore, this system settling tim e is not a compo nen t
specification.
The maximum lock time for the distributed loop is
specified in Table 9. Note that the total time for the
output clock to settle from the Powerdown state to the
Normal state is the sum of tPOWERUP plus tDIS-
TLOCK. Simila rly, if MU LT0 and MULT1 control
signals are changed whil e the DRCG is in the Normal
state, the total time for the o utput clock to re-settle is
the sum of tMULT plu s tDISTLOCK.
The above specification is the maximum possible lock
time for the distributed loop. The actual lock time
depends on the cycle time of the phase detector input
clocks (tCYCLE,PD), the amount of initial phase error at
the phase detector inputs (tERR,INIT), and the phase
detector step size per update (tSTEP) shown in Table 17.
The lock time is given by:
tDISTLOCK = tCYCLE,PD * tERR,INIT / tSTEP.
Using the values given in Table 1 6 and Table 17, this
reduces to:
tDISTLOCK = 0.5 * (tCYCLE,PD)2 / 2ps.
The resulting lock time, theref ore, str ongly depends on
the phase detector input cycle time. For the maxim um
cycl e time of 10 0ns (10MH z), this gives 2.5m s as shown
in Table 9. For a cycle time of 80ns (12.5MHz), the lock
time drops to 1.6ms. And for a faster cycle time of 40ns
(25MHz), the lock time drops to 0.4ms.
Test Modes
Table 10 shows the logic for selecti ng the Bypass and
Test modes. The select bits, S0 and S1, control the selec-
tion of these modes. The Bypass mode selects and
outputs the full speed PLL output clock (PLLClk) to
the CLK/CLKB outputs bypassin g the Phase Aligner.
The Test mode selects the REFCLK input and outputs
it to the CLK/CLKB outpu ts bypassing both the PLL
and the Phase Aligner.
In the Output Test mode (OE), both the CLK and CLKB
outputs are put into a high-im p edance state (Hi-Z).
This mode can be used for component testing and for
board-level testing. The internal resistor dividers used
Table 7. Powerdown Mode Selec tion
Mode PWRDNB STOPB CLK CLKB
Normal 1 1 PAClk PAClkB
Power-
down 0XGndGnd
Table 8. PLL Divider Selection
MULT0 MULT1 A B
0041
0161
1181
1083
Table 9. Distributed Loo p Lock Time Specific ation
Symbol Min Max Unit Description
tDISTLOCK 2.5 ms Time from when
CLK/CLK B out-
put is settled to
when the phase
error between
SYNCLK N an d
PCLKM falls
withi n the tERR-PD
spec in Table 17.