DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D109 BSS192 P-channel enhancement mode vertical D-MOS transistor Product specification Supersedes data of 1997 Jun 20 2002 May 22 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS192 FEATURES PINNING - SOT89 * Direct interface to C-MOS, TTL, etc. PIN SYMBOL DESCRIPTION * High-speed switching 1 s source * No secondary breakdown. 2 d drain 3 g gate APPLICATIONS * Line current interrupter in telephone sets * Relay, high-speed and line transformer drivers. d handbook, halfpage DESCRIPTION g P-channel enhancement mode vertical D-MOS transistor in a SOT89 package. 1 2 Bottom view 3 s MAM354 Marking code: KB. Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER VDS drain-source voltage (DC) VGSth gate-source threshold voltage ID drain current (DC) RDSon drain-source on-state resistance 2002 May 22 CONDITIONS MAX. -240 ID = -1 mA; VGS = VDS ID = -200 mA; VGS = -10 V 2 UNIT V -2.8 V -200 mA 12 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS192 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT - -240 V - 20 V drain current (DC) - -200 mA peak drain current - -600 mA - 1 W storage temperature -65 +150 C junction temperature - 150 C VDS drain-source voltage (DC) VGSO gate-source voltage (DC) ID IDM Ptot total power dissipation Tstg Tj open drain Tamb 25 C; note 1 Note 1. Device mounted on a ceramic substrate; area 2.5 cm2; thickness 0.7 mm. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 125 K/W note 1 Note 1. Device mounted on a ceramic substrate; area 2.5 cm2; thickness 0.7 mm. CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS drain-source breakdown voltage VGS = 0; ID = -10 A -240 - - V VGSth gate-source threshold voltage VGS = VDS; ID = -1 mA -0.8 - -2.8 V IDSS drain-source leakage current VGS = 0; VDS = -60 V - - -200 nA VGS = -0.2 V; VDS = -200 V - -0.1 -60 A IGSS gate leakage current VDS = 0; VGS = 20 V - - 100 nA RDSon drain-source on-state resistance VGS = -10 V; ID = -200 mA - 10 12 yfs forward transfer admittance VDS = -25 V; ID = -200 mA 60 200 - mS Ciss input capacitance VGS = 0; VDS = -25 V; f = 1 MHz - 55 90 pF Coss output capacitance VGS = 0; VDS = -25 V; f = 1 MHz - 20 30 pF Crss reverse transfer capacitance VGS = 0; VDS = -25 V; f = 1 MHz - 5 15 pF Switching times (see Figs 2 and 3) ton turn-on time VGS = 0 to -10 V; VDD = -50 V; ID = -250 mA - 5 10 ns toff turn-off time VGS = -10 to 0 V; VDD = -50 V; ID = -250 mA - 20 30 ns 2002 May 22 3 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS192 handbook, halfpage VDD = -50 V handbook, halfpage 10 % INPUT 90 % 10 % 0V OUTPUT ID -10 V 50 90 % ton MBB689 toff MBB690 Fig.2 Switching times test circuit. Fig.3 Input and output waveforms. MLC697 1.2 MDA180 160 handbook, halfpage handbook, halfpage C (pF) Ptot (W) 120 0.8 80 (1) 0.4 40 (2) (3) 0 0 0 50 100 150 200 Tamb (C) 0 -5 -10 -15 -20 -25 VDS (V) VGS = 0; Tj = 25 C; f = 1 MHz. (1) Ciss. (2) Coss. (3) Crss. Fig.5 Fig.4 Power derating curve. 2002 May 22 4 Capacitance as a function of drain-source voltage; typical values. Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS192 MDA177 -1 handbook, halfpage ID (A) -0.8 MDA178 -1 handbook, halfpage (1) ID (A) -0.8 (2) -0.6 -0.6 (3) -0.4 -0.4 (4) -0.2 -0.2 (5) 0 -5 0 -10 Tj = 25 C. (1) VGS = -10 V. (2) VGS = -6 V. -15 0 -20 -25 VDS (V) (3) VGS = -5 V. (4) VGS = -4 V. (5) VGS = -3 V. -4 -6 -8 -10 VGS (V) VDS = -10 V; Tj = 25 C. Fig.6 Output characteristics; typical values. -103 handbook, halfpage -2 0 Fig.7 Transfer characteristic; typical values. MDA179 MDA182 1.2 (1) handbook, halfpage k (2) 1.1 ID (mA) (3) 1 -102 0.9 0.8 -10 8 12 16 20 0.7 -50 24 28 RDSon () Tj = 25 C. 50 100 Tj (oC) 150 V GSth at T j k = ------------------------------------V GSth at 25C (1) VGS = -10 V. (2) VGS = -5 V. (3) VGS = -4 V. VGSth at ID = -1 mA. Fig.8 Fig.9 Drain current as a function of drain-source on-state resistance; typical values. 2002 May 22 0 5 Temperature coefficient of gate-source threshold voltage; typical values. Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS192 MDA181 2.5 handbook, halfpage k 2 1.5 1 0.5 0 -50 0 50 100 Tj (oC) 150 R DSon at T j k = ---------------------------------------R DSon at 25 C ID = -200 mA; VGS = -10 V. Fig.10 Temperature coefficient of drain-source on-state resistance; typical values. 2002 May 22 6 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS192 PACKAGE OUTLINE Plastic surface mounted package; collector pad for good heat transfer; 3 leads SOT89 B D A b3 E HE L 1 2 3 c b2 w M b1 e1 e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A b1 b2 b3 c D E e e1 HE L min. w mm 1.6 1.4 0.48 0.35 0.53 0.40 1.8 1.4 0.44 0.37 4.6 4.4 2.6 2.4 3.0 1.5 4.25 3.75 0.8 0.13 OUTLINE VERSION SOT89 2002 May 22 REFERENCES IEC JEDEC EIAJ TO-243 SC-62 7 EUROPEAN PROJECTION ISSUE DATE 97-02-28 99-09-13 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS192 DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 May 22 8 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS192 NOTES 2002 May 22 9 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS192 NOTES 2002 May 22 10 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSS192 NOTES 2002 May 22 11 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA74 (c) Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613510/03/pp12 Date of release: 2002 May 22 Document order number: 9397 750 09633