DATA SH EET
Product specification
Supersedes data of 1997 Jun 20 2002 May 22
DISCRETE SEMICONDUCTORS
BSS192
P-channel enhancement mode
vertical D-MOS transistor
b
ook, halfpage
M3D109
2002 May 22 2
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSS192
FEATURES
•Direct interface to C-MOS, TTL, etc.
•High-speed switching
•No secondary breakdown.
APPLICATIONS
•Line current interrupter in telephone sets
•Relay, high-speed and line transformer drivers.
DESCRIPTION
P-channel enhancement mode vertical D-MOS transistor
in a SOT89 package.
PINNING - SOT89
PIN SYMBOL DESCRIPTION
1 s source
2 d drain
3 g gate
Fig.1 Simplified outline and symbol.
Marking code: KB.
handbook, halfpage
123
MAM354
Bottom view s
d
g
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MAX. UNIT
VDS drain-source voltage (DC) −240 V
VGSth gate-source threshold voltage ID=−1 mA; VGS =V
DS −2.8 V
IDdrain current (DC) −200 mA
RDSon drain-source on-state resistance ID=−200 mA; VGS =−10 V 12 Ω
2002 May 22 3
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSS192
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Note
1. Device mounted on a ceramic substrate; area 2.5 cm2; thickness 0.7 mm.
THERMAL CHARACTERISTICS
Note
1. Device mounted on a ceramic substrate; area 2.5 cm2; thickness 0.7 mm.
CHARACTERISTICS
Tj=25°C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS drain-source voltage (DC) −−240 V
VGSO gate-source voltage (DC) open drain −±20 V
IDdrain current (DC) −−200 mA
IDM peak drain current −−600 mA
Ptot total power dissipation Tamb ≤25 °C; note 1 −1W
T
stg storage temperature −65 +150 °C
Tjjunction temperature −150 °C
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-a thermal resistance from junction to ambient note 1 125 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS drain-source breakdown voltage VGS = 0; ID=−10 µA−240 −−V
V
GSth gate-source threshold voltage VGS =V
DS; ID=−1mA −0.8 −−2.8 V
IDSS drain-source leakage current VGS = 0; VDS =−60 V −−−200 nA
VGS =−0.2 V; VDS =−200 V −−0.1 −60 µA
IGSS gate leakage current VDS = 0; VGS =±20 V −−±100 nA
RDSon drain-source on-state resistance VGS =−10 V; ID=−200 mA −10 12 Ω
yfsforward transfer admittance VDS =−25 V; ID=−200 mA 60 200 −mS
Ciss input capacitance VGS = 0; VDS =−25 V; f = 1 MHz −55 90 pF
Coss output capacitance VGS = 0; VDS =−25 V; f = 1 MHz −20 30 pF
Crss reverse transfer capacitance VGS = 0; VDS =−25 V; f = 1 MHz −515pF
Switching times (see Figs 2 and 3)
ton turn-on time VGS =0to−10 V; VDD =−50 V;
ID=−250 mA −510ns
t
off turn-off time VGS =−10 to 0 V; VDD =−50 V;
ID=−250 mA −20 30 ns
2002 May 22 4
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSS192
Fig.2 Switching times test circuit.
handbook, halfpage
MBB689
50 Ω
VDD = −50 V
ID
0 V
−10 V
Fig.3 Input and output waveforms.
handbook, halfpage
MBB690
10 %
90 %
90 %
10 %
ton toff
OUTPUT
INPUT
Fig.4 Power derating curve.
handbook, halfpage
0 200
0
0.4
0.8
1.2
MLC697
Tamb (°C)
50 100 150
Ptot
(W)
Fig.5 Capacitance as a function of drain-source
voltage; typical values.
VGS = 0; Tj=25°C; f = 1 MHz.
(1) Ciss.
(2) Coss.
(3) Crss.
handbook, halfpage
0
(1)
(2)
(3)
−5−25
160
120
40
0
C
(pF)
VDS (V)
80
−10 −15 −20
MDA180
2002 May 22 5
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSS192
Fig.6 Output characteristics; typical values.
handbook, halfpage
0
(1)
(2)
(3)
(5)
−25
−1
0
VDS (V)
ID
(A)
−0.2
−0.4
−0.6
−0.8
−5−10 −15 −20
MDA177
(4)
Tj=25°C.
(1) VGS =−10 V.
(2) VGS =−6V.
(3) VGS =−5V.
(4) VGS =−4V.
(5) VGS =−3V.
Fig.7 Transfer characteristic; typical values.
VDS =−10 V; Tj=25°C.
handbook, halfpage
0−10
−1
0
VGS (V)
ID
(A)
−0.2
−0.4
−0.6
−0.8
−2−4−6−8
MDA178
Fig.8 Drain current as a function of drain-source
on-state resistance; typical values.
Tj=25°C.
(1) VGS =−10 V.
(2) VGS =−5V.
(3) VGS =−4V.
handbook, halfpage
288
ID
(mA)
RDSon (Ω)
12 16 20 24
−103
−102
−10
MDA179
(2)
(3)
(1)
Fig.9 Temperature coefficient of gate-source
threshold voltage; typical values.
VGSth at ID=−1 mA.
kVGSth at Tj
VGSth at 25°C
--------------------------------------
=
handbook, halfpage
−50 0 50 150
1.2
0.7
k
1.1
100
1
0.9
0.8
MDA182
Tj (oC)
2002 May 22 6
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSS192
Fig.10 Temperature coefficient of drain-source
on-state resistance; typical values.
ID=−200 mA; VGS =−10 V.
kRDSon at Tj
RDSon at 25 °C
-----------------------------------------
=
handbook, halfpage
−50 0 50 150
2.5
0
k
2
100
1.5
1
0.5
MDA181
Tj (oC)
2002 May 22 7
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSS192
PACKAGE OUTLINE
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
DIMENSIONS (mm are the original dimensions)
SOT89 TO-243 SC-62 97-02-28
99-09-13
wM
e1
e
EHE
B
0 2 4 mm
scale
b3
b2
b1
c
D
L
A
Plastic surface mounted package; collector pad for good heat transfer; 3 leads SOT89
123
UNIT A
mm 1.6
1.4 0.48
0.35
c
0.44
0.37
D
4.6
4.4
E
2.6
2.4
HE
4.25
3.75
e
3.0
w
0.13
e1
1.5
L
min.
0.8
b2
b1
0.53
0.40
b3
1.8
1.4
2002 May 22 8
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSS192
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
DATA SHEET STATUS(1) PRODUCT
STATUS(2) DEFINITIONS
Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratany otherconditionsabove thosegivenin the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationor warrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusing orsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseofanyofthese products,conveys nolicence ortitle
under any patent, copyright, or mask work right to these
products,and makes norepresentationsor warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
2002 May 22 9
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSS192
NOTES
2002 May 22 10
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSS192
NOTES
2002 May 22 11
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSS192
NOTES
© Koninklijke Philips Electronics N.V. 2002 SCA74
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Printed in The Netherlands 613510/03/pp12 Date of release: 2002 May 22 Document order number: 9397 750 09633
