Gigabit-Ethernet/Fast-Ethernet - Agere Systems, Inc.

Product Brief

June 2001

Gigabit Ethernet/Fast Ethernet POS-PHY Bridge

Overview

The gigabit Ethernet (GbE)/fast Ethernet POS-PHY

bridge enables system solutions to be created f or two

diff erent applications. The first application involves

transporting GbE frames or 10 Mbits/s/100 Mbits/s

Ethernet frames over existing SONET/SDH rings or

point-to-point connections. The second application

inv olv es transporting GbE or 10/100 Ethernet frames

to and from the switch f abric. The SONET/SDH

transport is provided using a combination of SONET/

SDH and GbE/fast Ethernet standard products,

together with an FPGA and stand-alone SDRAM

devices. The transport ov er the switch fabric is pro-

vided using Agere Systems Inc.’s PayLoadPlus™

network processor chip set, GbE/fast Ethernet stan-

dard products together with an FPGA.

One of the benefits of this solution is the unification of

all WAN and PSTN service deliveries over the same

infrastructure, platforms, and fiber-access interfaces.

Virtual private networks (VPNs) can also be imple-

mented over optical networks having the reliability

built into SONET/SDH systems. The solution allows

transport of GbE/fast Ethernet traffic to and from the

switch fabric.

The solution provided by Agere is an end-to-end

hardware solution. This includes interconnection to

both the switch fabric and the Ethernet networks,

encapsulation o f Ethernet frames into POS (packet-

over-SONET) frames, ingress and egress packet

buffering, error checking, and optional flow control

across the fiber link and into the Ethernet network.

An intellectual property (IP) VHDL* core is provided

from Agere that targets ORCA® Series FPGAs and

performs the GbE (or Ethernet/fast Ethernet) encap-

sulation into POS frames to interface to the Agere

PayLoadPlus network processor chip set or to a

SONET/SDH framer (for SONET/SDH systems).

This IP core is provided along with all of the needed

implementation scripts, test benches, and documen-

tation to allow easy modification of the core to meet

differing customer needs.

*VHDL is a registered trademark of Gateway Design Automation

Corporation.

The supplied solution has been implemented for OC-

48c networks b ut the architecture has been designed

to allow for speed increases of the switch fabric (or

SONET/SDH) and GbE networks by using f aster

standard products with modifications to the IP core

solution.

GbE/Fast Ethernet PayLoadPlus POS-

PHY Bridge Features

The first application of the POS-PHY bridge is to

encapsulate GbE/fast Ethernet frames into packet

over SONET-physical laye r level 3 (POS-PHY L3) for-

mat for connecting to Agere’s PayLoadPlus network

processor chip set. This allows transport of GbE/fast

Ethernet traffic to and from the s witch f abric. Figure 1

is a block diagram of this application.

■The network processor chip set consists of three

devices; the fast pattern processor (FPP), the route

switch processor (RSP), and the Agere system

interface (ASI):

— The FPP provides the ingress data path and

performs traffic data classification at wire speed

rates. Data is identified, queued, and stored in

external DRAM in complete protocol data units

(PDUs) during first-pass processing. Second-

pass processing is performed on complete

PDUs and passed to the RSP with classification

decisions.

— The RSP performs PDU modifications and

applies traffic management algorithms on

egress data.

— The ASI provides the host system interface for

passing e xternal function calls, local control reg-

ister access, and policing management port

functions.

■Provides asynchronous FIFO decoupled interf aces

between the MA C transmit/receiv e FIFO ports and

the FPP/RSP ingress/egress FIFO ports.

■Provides a communication interface between the

ASI configuration bus and the control register CPU

interface provided by the MAC devices.

22 Agere Systems Inc.

Product Brief

June 2001

POS-PHY Bridge

Gigabit Ethernet/Fast Ethernet

GbE/Fast Ethernet PayLoadPlus POS-

PHY Bridge Features (continued)

■The GbE/ fast Ethernet PayLoadPlus POS-PHY

bridge solution consists of the following products:

— Agere’s PayLoadPlus network processor chip set.

— A dual-channel GbE MAC device or octal 10/100

MACs.

— Agere’s physical layer (SERDES) devices.

— An ORCA Series 4 FPGA (typically an OR4E6)

with a VHDL IP core to implement the required

interface functions. The programmability of these

devices allows for easy modifications to the base

architecture or the incorporation of other system

functions in the same device.

■Base architecture allows modifications for switch fab-

ric speed improvements to OC-192, Ethernet speed

improvements to 10 GbE, and for increased GbE

channels per OC-48 link.

GbE/Fast Ethernet SONET/SDH POS-

PHY Bridge Features

Optionally, the POS-PHY bridge can be used to encap-

sulate GbE/fast Ethernet frames into the SONET/SDH

protocol using packet-over SONET physical layer level

3 (POS-PHY L3) format. In the future, interfaces for

UTOPIA 3+ (PLATO) will also be available for interfac-

ing to the TADM042G5 or TDAT042G5 devices. Figure

2 is a block diagram of this application.

■Performs all SONET/SDH section, line, and path ter-

mination func ti ons.

■Encapsulates the GbE frame using either point-to-

point protocol (PPP using byte-sync HDLC), sim-

plified data link (SDL), or generic framing procedure

(GFP).

■Provides two OC-24c POS interfaces to the

SONET/SDH optical network, with each OC-24c car-

rying one of the two GbE data channels.

■Optionally, each GbE interface can be transported

using two OC-12c POS links. Minor modifications to

the current IP block are required for this solution and

will be availabl e as a follow-on IP core.

■Each SONET/SDH GbE/fast Ethernet POS-PHY

bridge solution consists of the following products:

— Agere’s TADM042G5 OC-48/Quad OC-12

SONET add/drop MUX interface device (for point-

to-point connections, the TDAT042G5 device is

used) or any industry-standard

SONET/SDH framer with POS-PHY L3 interface.

— A dual-channel GbE MAC device or octal

10/100 MACs.

— Agere’s physical layer (SERDES) devices.

— OC-48 MUX/deMUX (TTRN012G5 and

TRCV012 G5) and laser interfa ce devi ces.

— Agere’s LG1627BXC OC-48 SONET/SDH

compliant lasers.

— An industry standard SDRAM.

— An ORCA Series 4 FPGA (typically an OR4E4)

with a VHDL IP core to implement the required

interface functions. The programmability of these

devices allow for easy modifications to the base

architecture or the incorporation of other system

functions in the same device.

■Base architecture allows modifications for

SONET/SDH speed improvements to OC-192,

Ethernet speed improvements to 10 GbE, and for

increased GbE channels per OC-48 SONET/SDH

link.

1460.a(F)

Figure 1. GbE/Fast Ethernet POS-PHY Bridge Interfacing to PayLoadPlus

RSP FPP

ASI HOST

CPU

SWITCH FABRIC

MTP LEVEL ONE

DATA

CPU BUS IXF1002

OR IXF440

32b

DATA

32b

(8) 10/100

BASE

(2) G bE

PL3 16b/32b

UTOPIA/PL3/PLAT O /UTO PIA+ 1 6 b

PL3

32b

PL3 16b/32b

PCI

CPU (CONFIGURATION) BUS

UTOPIA/PL3/

PLATO/

UTOPIA+

16b

Product Brief

J une 2001

Agere Systems Inc. 3

POS-PHY Bridge

Gigabit Ethe rnet/Fast Ethernet

GbE/Fast Ethernet PayLoadPlus POS-PHY Bridge Features (continued)

0228.c(F)

Figure 2. GbE ov er SONET Block Diagram

TADM042G5

TO/FROM

SONET

RING

PHYSICAL

LAYER

SONET/GbE

INTERFACE

FUNCTIONS EGRESS

FIFO B

128K x 36

INGRESS

FIFO B

512 x 36

INGRESS

FIFO A

512 x 36

EGRESS

FIFO A

128K x 36

DUAL

GIGABIT

MAC

GbE PHY

GbE

NETWORK A

GbE

NETWORK B

3232

32 32

3232

SONET/GbE

INTERFACE

FUNCTIONS

PL3 INTERFACE

ORCA FPGA

Description

The detailed implementation of the PayLoadPlus sys-

tem is shown in Figure 1. The FPGA portion of the

design performs the interface function between the

GbE/fast Ethernet controller devices and the PayLoad-

Plus network processor chip set.

The PayLoadPlus network processor chip set consists

of three devices, the fast pattern processor (FPP), the

route switch processor (RSP), and the Agere system

interface (ASI). The FPP provides the ingress data path

and performs traffic data classification at wire speed

rates. Data is identified, queued, and stored in e xternal

DRAM in complete protocol data units (PDUs) during

first-pass processing. Second-pass processing is per-

f ormed on complete PDUs and passed to the RSP with

classification decisions. The RSP performs PDU modi-

fications and applies traffic management algorithms on

egress data. The ASI provides the host system inter-

face for passing external function calls, local control

tions.

The dual-GbE/quad-10/100 Mbits/s Ethernet MAC per-

forms interface functions to the Ethernet networks,

including the handling of congestion by using industry-

standard techniques such as PAUSE commands and

XON/XOFF flow control. The physical layer devices

interface to the Ethernet network physical transport

medium.

The IP core in the FPGA devices performs all of the

handshaking between the GbE/fast Ethernet media

access controller (MAC) and the PayLoadPlus chip set

(FPP and RSP) or the SONET/SDH device. Also

included in the FPGA core is the handling of rate mis-

matches between the interconnected networks, control

of the data buffering and flow control between the net-

works, and the discarding of errored packets received

from the MA C before transmission across the

SONET/SDH fiber or switch fabric interface. Other

user-defined functions can also be easily integrated

into any remaining gates of the FPGA devices.

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. ORCA is

a registered trademark and PayloadPlus is a trademark of Agere Systems Inc.

Printed in U.S.A.

June 2001

PB01-098NCIP (Replaces PB01-029 NCIP)

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@micro.lucent.com

N. AM E R ICA: Agere Systems Inc., 555 Union Bou levard, Room 30 L-15P - B A, Allentown, PA 1810 9-3286

1-800-372-2447, FA X 610-712-4106 (I n CANA DA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC

Tel. (86) 21 50471212 , FAX (86) 21 50472266

JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan

Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE: Data Requ est s: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148

Tech ni cal Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM : (44) 1344 865 900 (Ascot),

FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm) , FINLAN D: (358) 9 3507670 (Helsinki),

ITALY: (39) 02 6608131 (Milan), SPAIN : (34) 1 807 1441 (Madrid)

Product Brief

June 2001

POS-PHY Bridge

Gigabit Ethernet/Fast Ethernet

Description (continued)

For the SONET/SDH system, the FPGA connects via

the POS-PHY L3 interface to a SONET/SDH de vice

performing the needed SONET/SDH interface func-

tions. These include section, line, and path overhead

functions, pointer processing, automatic protection

switch interfaces, and cross-connect support for trans-

mit and receive of data engine payload functions, such

as PPP, using HDLC or SDL, and POS-PHY L2 and L3

(or UTOPIA L2 and L3) physical interfaces, including

packet support through POS extensions.

All devices are provisioned, monitored, and controlled

through microprocessor interfaces to allow for easy in-

system modifications. Low-level software drivers are

also available for many of the standard products to

ease system integration of these devices.

Other Information

Product briefs, data sheets, application notes, and

other information on many of the products used in the

above system solutions are available from Agere. This

solution is also highlighted on the networks and com-

munications website at:

http://www.agere.com/netcom

Ordering Information

Contact your local Agere sales representativ e f or order-

ing information. The IP core is a member of the Smart

Silicon f amily of Agere IP cores, and an IP core license

agreement is required for the VHDL IP kit. The license

agreement is for unlimited reuse of the solution in your

company, but will limit the implementation of the IP core

described above to Agere devices, either as standard

products, standard-cell ASICs, FPGAs, or FPSCs

(combined FPGA/standard-cell ASIC devices).