a FEATURES Transformer-Like Balanced Output Drives 10 V RMS Into a 600 V Load Stable When Driving Large Capacitive Loads and Long Cables Low Distortion 0.006% typ 20 Hz-20 kHz, 10 V RMS into 600 V High Slew Rate 15 V/ms typ Low Gain Error (Differential or Single-Ended); 0.7% typ Outputs Short-Circuit Protected Available In Space-Saving 8-Pin Mini-DIP Package Low Cost APPLICATIONS Audio Mix Consoles Distribution Amplifiers Graphic and Parametric Equalizers Dynamic Range Processors Digital Effects Processors Telecommunications Systems Industrial Instrumentation Hi-Fi Equipment GENERAL DESCRIPTION The SSM2142 is an integrated differential-output buffer amplifier that converts a single-ended input signal to a balanced output signal pair with high output drive. By utilizing low noise thermally matched thin film resistors and high slew rate amplifiers, the SSM2142 helps maintain the sonic quality of audio systems by eliminating power line hum, RF interference, voltage drops, and other externally generated noise commonly encountered with long audio cable runs. Excellent rejection of common-mode noise and offset errors is achieved by laser trimming of the onboard resistors, assuring high gain accuracy. The carefully designed output stage of the SSM2142 is capable of driving difficult loads, yielding low distortion performance despite extremely long cables or loads as low as 600 , and is stable over a wide range of operating conditions. Balanced Line Driver SSM2142 FUNCTIONAL BLOCK DIAGRAM VIN 50 +OUT FORCE +OUT SENSE 10k - OUT SENSE 50 - OUT FORCE ALL RESISTORS 30k UNLESS OTHERWISE INDICATED 10k GND Based on a cross-coupled, electronically balanced topology, the SSM2142 mimics the performance of fully balanced transformer-based solutions for line driving. However, the SSM2142 maintains lower distortion and occupies much less board space than transformers while achieving comparable common-mode rejection performance with reduced parts count. The SSM2142 in tandem with the SSM2141 differential receiver establishes a complete, reliable solution for driving and receiving audio signals over long cables. The SSM2141 features an Input Common-Mode Rejection Ratio of 100 dB at 60 Hz. Specifications demonstrating the performance of this typical system are included in the data sheet. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 (c)1991-2011 Analog Devices, Inc. All rights reserved. (VS = 618 V, -408C TA +858C, operating in differential mode unless otherwise SSM2142-SPECIFICATIONS noted. Typical characteristics apply to operation at T = +258C.) A Parameter Symbol INPUT IMPEDANCE ZIN INPUT CURRENT IIN Conditions Min Typ Max Units 10 VIN = 7.071 V 750 GAIN, DIFFERENTIAL GAIN, SINGLE-ENDED Single-Ended Mode GAIN ERROR, DIFFERENTIAL RL = 600 k 900 A 5.8 5.98 dB 5.7 5.94 dB 0.7 2 % POWER SUPPLY REJECTION RATIO STATIC PSRR VS = 13 V to 18 V OUTPUT COMMON-MODE REJECTION OCMR See Test Circuit; f = 1 kHz -45 -38 dB OUTPUT SIGNAL BALANCE RATIO SBR See Test Circuit; f = 1 kHz -40 -35 dB TOTAL HARMONIC DISTORTION Plus Noise THD+N 20 Hz to 20 kHz, VO = 10 V rms, RL = 600 0.006 % SIGNAL-TO-NOISE RATIO SNR VIN = 0 V -93.4 dBu HEADROOM HR CLIP Level = 10.5 V rms +93.4 dBu SLEW RATE SR 15 V/s OUTPUT COMMON-MODE VOLTAGE OFFSET1 VOOS RL = 600 -250 25 250 mV DIFFERENTIAL OUTPUT VOLTAGE OFFSET VOOD RL = 600 -50 15 50 mV VIN = 7.071 V 13.8 14.14 45 50 55 5.5 70 7.0 60 mA mA DIFFERENTIAL OUTPUT VOLTAGE SWING OUTPUT IMPEDANCE ZO SUPPLY CURRENT OUTPUT CURRENT, SHORT CIRCUIT ISY ISC 60 Unloaded, VIN = 0 V 80 dB V NOTES 1 Output common-mode offset voltage can be removed by inserting dc blocking capacitors in the sense lines. See Applications Information. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* PIN CONNECTIONS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Storage Temperature . . . . . . . . . . . . . . . . . . -60C to +150C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150C Operating Temperature Range . . . . . . . . . . . . -40C to +85C Output Short Circuit Duration (Both Outputs) . . . . Indefinite 8-Pin Plastic DIP (P Suffix) *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -2- 16-Pin Wide Body SOL (S Suffix) NC 1 16 NC NC 2 15 NC - FORCE 3 14 + FORCE - SENSE 4 13 + SENSE GROUND 5 12 +V VIN 6 11 -V NC 7 10 NC NC 8 9 NC REV. C SSM2142 300 V OUT 300 V VS = 0V 1 8 2 7 300 3 6 +18V 4 5 -18V 600 VIN = 10V p-p 1 8 2 7 3 6 4 5 300 600 +18V V VOUT -18V V CMR = 10V p-p SBR = 20 LOG VOUT OCMR = 20 LOG VCMR Figure 1. Output CMR Test Circuit VOUT VIN Figure 2. Signal Balance Ratio (BBC Method) Test Circuit Typical Performance Characteristics 12 140 POWER SUPPLY REJECTION - dB OUTPUT VOLTAGE SWING - V rms TA = +25C VS = 18V 120 VS = 1V 100 -PSR 80 +PSR 60 40 20 TA = +25C VS = 18V RL = 600 DIFF. MODE 10 8 0.1% DISTORTION 0.01% DISTORTION 6 4 2 0 0 10 100 1k 10k 20 10 100k FREQUENCY - Hz Figure 3. Power Supply Rejection vs. Frequency 100 6.5 TA = +25C RL = 600 10 TA = +25C VIN = 0V 6.0 DIFF. MODE FREQ. = 20kHz SUPPLY CURRENT - mA OUTPUT VOLTAGE SWING - V rms 50 Figure 4. Maximum Output Voltage Swing vs. Frequency 12 8 0.1% DISTORTION 6 4 NO LOAD 5.5 5.0 4.5 4.0 2 3.5 0 2 6 10 14 18 2 6 10 14 18 SUPPLY VOLTAGE - Volts SUPPLY VOLTAGE - Volts Figure 6. Supply Current vs. Supply Voltage Figure 5. Output Voltage Swing vs. Supply Voltage REV. C 30 FREQUENCY - kHz -3- SSM2142 THD PERFORMANCE The following data, taken from the THD test circuit on an Audio Precision System One using the internal 80 kHz noise filter, demonstrates the typical performance of a balanced pair system based on the SSM2142/SSM2141 chip set. Both differential and single-ended modes of operation are shown, under a number of output load conditions which simulate various application situations. Note also that there is no adverse effect on system performance when using the optional series feedback capacitors, which reject dc cable offsets in order to maintain optimal ac noise rejection. The large signal transient response of the system to a 100 kHz square wave input is also shown, demonstrating the stability of the SSM2142 under load. +18V A 10F* C V IN 4 6 7 SSM 3 2142 2 8 RL 1 B SSM 2141 Figure 9. THD+N vs. Frequency at Point B (Differential Mode) VOUT 5 10F* R1 R2 -18V *USED ONLY IN THD PLOTS AS NOTED. ALL CABLE MEASUREMENTS USE BELDEN 8451 CABLE. Figure 7. THD Test Circuit Figure 10. THD+N vs. Frequency at Point A (Single Ended) Figure 8. THD+N vs. Frequency at Point B (Differential Mode) Figure 11. THD+N vs. Frequency at Point C (SSM2141 Output) -4- REV. C SSM2142 on-chip 50 series damping resistors. The impedances in the output buffer pair are precisely balanced by laser trimming during production. This results in the high gain accuracy needed to obtain good common-mode noise rejection, and excellent separation between the offset error voltages common to the cable pair and the desired differential input signal. As shown in the test circuit, it is suggested that a suitable balanced, high input-impedance differential amplifier such as the SSM2141 be used at the receiving end for best system performance. The SSM2141 receiver output is configured for a gain of one half following the 6 dB gain of the SSM2142, in order to maintain an overall system gain of unity. 100 90 10 0% In applications encountering a large dc offset on the cable or those wishing to ensure optimal rejection performance by avoiding differential offset error sources, dc blocking capacitors may be employed at the sense outputs of the SSM2142. As shown in the test circuit, these components should present as little impedance as possible to minimize low-frequency errors, such as 10 F NP (or tantalum if the polarity of the offset is known). Figure 12. 100 kHz Square Wave Observed at Point B (Differential Mode). VO = 10 V rms, R1 = R2 = , RL = 600 SYSTEM GROUNDING CONSIDERATIONS Due to ground currents, supply variations, and other factors, the ground potentials of the circuits at each end of a signal cable may not be exactly equal. The primary purpose of a balanced pair line is to reject this voltage difference, commonly called "longitudinal error." A measure of the ability of the system to reject longitudinal error voltage is output common-mode rejection. In order to obtain the optimal OCMR and noise rejection performance available with the SSM2142, the user should observe the following precautions: 100 90 10 0% 1. The quality of the differential output is directly dependent upon the accuracy of the input voltage presented to the device. Input voltage errors developed across the impedance of the source must be avoided in order to maintain system performance. The input of the SSM2142 should be driven directly by an operational amplifier or buffer offering low source impedance and low noise. Figure 13. 100 kHz Square Wave at Point B (Differential Mode). VO = 10 V rms, R1 = R2 = , RL = 600 , with Series Feedback Capacitors +15V 2. The ground input should be in close proximity to the singleended input's source common. Ground offset errors encountered in the source circuitry also impair system performance. +15V 4 V IN 3 7 6 3 7 8 SSM 2142 2 5 2 1 SHIELDED TWISTED-PAIR CABLE SSM 2141/ 2143 5 6 3. Make sure that the SSM2142 is adequately decoupled with 0.1 F bypass capacitors located close to each supply pin. V OUT 1 4. Avoid the use of passive circuitry in series with the SSM2142 outputs. Any reactive difference in the line pair will cause significant imbalances and affect the gain error of the device. Snubber networks or series load resistors are not required to maintain stability in SSM2142 based systems, even when driving signals over extremely long cables. 4 -15V -15V Figure 14. Typical Application of the SSM2142 and SSM2141 5. Efforts should be made to maintain a physical balance in the arrangement of the signal pair wiring. Capacitive differences due to variations in routing or wire length may cause unequal noise pickup between the pair, which will degrade the system OCMR. Shielded twisted-pair cable is the preferred choice in all applications. The shield should not be utilized as a signal conductor. Grounding the shield at one end, near the output common, avoids ground loop currents flowing in the shield which increase noise coupling and longitudinal errors. APPLICATIONS INFORMATION The SSM2142 is designed to provide excellent common-mode rejection, high output drive, and low signal distortion and noise in a balanced line-driving system. The differential output stage consists of twin cross-coupled unity gain buffer amplifiers with REV. C -5- SSM2142 THE CABLE PAIR The SSM2142 is capable of driving a 10 V rms signal into 600 and will remain stable despite cable capacitances of up to 0.16 F in either balanced or single-ended configurations. Low impedance shielded audio cable such as the standard Belden 8451 or similar is recommended, especially in applications traversing considerable distances. The user is cautioned that the so-called "audiophile" cables may incur four times the capacitance per unit length of the standard industrial-grade product. In situations of extreme load and/or distance, adding a second parallel cable allows the user to trade off half of the total line resistance against a doubling in capacitive load. SINGLE-ENDED OPERATION The SSM2142 is designed to be compatible with existing balanced-pair interface systems. Just as in transformer-based circuits, identical but opposite currents are generated by the output pair which can be ground-referenced if desired and transmitted on a single wire. Single-ended operation requires that the unused side of the output pair be grounded to a solid return path in order to avoid voltage offset errors at the nearby input common. The signal quality obtained in these systems is directly dependent on the quality of the ground at each end of the wire. Also note that in single-ended operation the gain through the device is still 6 dB, and that the SSM2142 incurs no significant degradation in signal distortion or output drive capability, although the noise rejection inherent in balancedpair systems is lost. POWER SUPPLY SEQUENCING A problem occasionally encountered in the interface system environment involves irregular application of the supplies. The user is cautioned that applying power erratically can inadvertently bias parts of the circuit into a latch-up condition. The small geometries of an integrated circuit are easily breached and damaged by short-risetime spikes on a supply line, which usually demonstrate considerable overshoot. The questionable practice of exchanging components or boards while under power can create such an undesirable sequence as well. Possible options which offer improved board-level device protection include: additional bypass capacitors, high-current reversebiased steering diodes between both supplies and ground, various transient surge suppression devices, and safety grounding connectors. PRINTED IN U.S.A. Likewise, power should be applied to the device before the output is connected to "live" systems which may carry voltages of sufficient magnitude to turn on the output devices of the SSM2142 and damage the device. In any case, of course, the user must always observe the absolute maximum ratings shown in the specifications. -6- REV. C SSM2142 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070606-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 1. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 8 0 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 1.27 (0.0500) 0.40 (0.0157) 03-27-2007-B 1 Figure 2. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model1 SSM2142PZ SSM2142SZ SSM2142SZ-REEL 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Descriptions 8-Lead PDIP 16-Lead SOIC_W 16-Lead SOIC_W Z = RoHS Compliant Part. Rev. C | Page 7 of 8 Package Option N-8 RW-16 RW-16 SSM2142 REVISION HISTORY 5/11--Rev. B to Rev. C Changes to Output Common-Mode Rejection Parameter and Output Signal Balance Ratio Parameter in SSM2142--Specifications Table ...................................................... 2 Updated Outline Dimensions ......................................................... 7 Changes to Ordering Guide ............................................................ 7 (c)1991-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01496-0-5/11(C) Rev. C | Page 8 of 8