Product Folder Sample & Buy Support & Community Tools & Software Technical Documents REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 REF50xx-EP Low-Noise, Very Low Drift, Precision Voltage Reference 1 Features 3 Description * The REF50xx is a family of low-noise, very low-drift, very high precision voltage references. These references are capable of both sinking and sourcing, and are very robust with regard to line and load changes. 1 * * * * * * * Low Temperature Drift: 5 ppm/C (Maximum) High Accuracy: 0.08% (Maximum) Low Noise: 3 VPP/V High Output Current: 10 mA Available in Military (-55C to 125C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Excellent temperature drift and high accuracy are achieved using proprietary design techniques. These features, combined with very low noise, make the REF50xx family ideal for use in high-precision data acquisition systems. They are offered in SOIC-8 packages, and are specified from -55C to 125C. Device Information(1) 2 Applications * * * * * * * * * (1) PART NUMBER 16-Bit Data Acquisition Systems ATE Equipment Industrial Process Control Medical Instrumentation Optical Control Systems Precision Instrumentation Controlled Baseline One Assembly/Test Site One Fabrication Site REF50xx-EP PACKAGE SOIC (8) BODY SIZE (NOM) 4.90 mm x 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Custom temperature ranges available Simplified Schematic +5 V Input Signal 0 V to 4 V +5 V R1 50 VDD +IN OPA365 ADS8326 C1 1.2 nF - IN REF GND REF5040 +5 V CBYPASS 1 F VIN GND VOUT C2 22 f 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 3 3 4 4 4 5 6 Detailed Description ............................................ 10 7.1 7.2 7.3 7.4 8 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics: Per Device ....................... Electrical Characteristics: All Devices....................... Typical Characteristics .............................................. Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 12 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Applications ............................................... 13 8.3 System Example ..................................................... 17 9 Power Supply Recommendations...................... 19 9.1 Basic Connections .................................................. 19 9.2 Low Dropout Voltage .............................................. 19 10 Layout................................................................... 19 10.1 Layout Guidelines ................................................. 19 10.2 Layout Example .................................................... 20 10.3 Power Dissipation ................................................. 20 11 Device and Documentation Support ................. 21 11.1 11.2 11.3 11.4 11.5 11.6 Documentation Support ....................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 21 21 21 21 21 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History Changes from Revision A (October 2012) to Revision B Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 3 * Changed title of Supply Voltage to Low Dropout Voltage ................................................................................................... 19 2 Submit Documentation Feedback Copyright (c) 2010-2015, Texas Instruments Incorporated Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP www.ti.com SBOS471B - APRIL 2010 - REVISED JUNE 2015 5 Pin Configuration and Functions D Package 8- Pin SOIC Top View 8 DNC(1) 7 NC(2) 3 6 VOUT 4 5 TRIM/NR DNC(1) 1 VIN 2 TEMP GND REF50xx NOTES: (1) DNC = Do not connect. (2) NC = No internal connection. Pin Functions PIN NAME I/O NO. DESCRIPTION DNC 1 -- Do not connect VIN 2 Power TEMP 3 O GND 4 Power TRIM/NR 5 I Output adjustment and noise reduction input. Connecting 1 F to this pin will create low pas filter at the bandgap and reduce output noise VOUT 6 O Very accurate, factory-trimmed voltage output. Recommended bypass capacitor from 1 F up to 50 F with ESR between 1 and 1.5 NC 7 -- No internal connection DNC 8 -- Do not connect Power supply voltage. Range from VOUT + 0.2 V up to 18 V. Recommended bypass capacitor from 1 F up to 10 F Temperature monitoring pin provides a temperature-dependent voltage output System ground 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN Input voltage MAX UNIT VIN 18 V Output short-circuit 30 mA 125 C 150 C 150 C Operating temperature -55 Junction temperature, TJ Storage temperature, Tstg (1) -65 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 3000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright (c) 2010-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP 3 REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIN MIN MAX VOUT + 0.2 V 18 V -10 10 mA IOUT UNIT 6.4 Thermal Information REF502x-EP THERMAL METRIC (1) D (SOIC) UNIT 8 PINS RJA Junction-to-ambient thermal resistance 97.1 C/W RJC(top) Junction-to-case (top) thermal resistance 42.2 C/W RJB Junction-to-board thermal resistance 34.6 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics: Per Device At TA = 25C, ILOAD = 0, CL = 1 F, and VIN = (VOUT + 0.2 V) to 18 V, unless otherwise noted. PARAMETER TA = 25C TEST CONDITIONS MIN TYP TA = -55C to 125C MAX MIN TYP UNIT MAX REF5020 (VOUT = 2.048V) (1) OUTPUT VOLTAGE Output Voltage VOUT 2.7 V < VIN < 18 V Initial Accuracy 2.048 -0.05% V 0.05% Over Temperature -0.08% 0.08% NOISE Output Voltage Noise f = 0.1 Hz to 10 Hz VPP 6 REF5025 (VOUT = 2.5 V) OUTPUT VOLTAGE Output Voltage VOUT 2.5 Initial Accuracy -0.05% V 0.05% NOISE Output Voltage Noise f = 0.1 Hz to 10 Hz VPP 7.5 REF5040 (VOUT = 4.096V) OUTPUT VOLTAGE Output Voltage VOUT 4.096 Initial Accuracy -0.05% V 0.05% Over Temperature -0.08% 0.08% NOISE Output Voltage Noise f = 0.1 Hz to 10 Hz VPP 12 REF5050 (VOUT = 5 V) OUTPUT VOLTAGE Output Voltage VOUT 5 Initial Accuracy -0.05% V 0.05% Over Temperature -0.08% 0.08% NOISE Output Voltage Noise (1) 4 f = 0.1 Hz to 10 Hz VPP 15 For VOUT 2.5 V, the minimum supply voltage is 2.7 V. Submit Documentation Feedback Copyright (c) 2010-2015, Texas Instruments Incorporated Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP www.ti.com SBOS471B - APRIL 2010 - REVISED JUNE 2015 6.6 Electrical Characteristics: All Devices At TA = 25C, ILOAD = 0, CL = 1 F, and VIN = (VOUT + 0.2 V) to 18 V, unless otherwise noted. PARAMETER TA = 25C TEST CONDITIONS MIN TYP TA = -55C to 125C MAX MIN UNIT TYP MAX REF5025 4 6.5 ppm/C REF5050 4 6.5 ppm/C All other devices 3 5 ppm/C OUTPUT VOLTAGE TEMPERATURE DRIFT Output Voltage Temperature Drift dVOUT/dT LINE REGULATION Line Regulation dVOUT/dVIN REF5020 (1) VIN = 2.7 V to 18V 0.1 1 All other devices VIN = VOUT + 0.2 V 0.1 1 ppm/V ppm/V Over Temperature 1 3 ppm/V LOAD REGULATION Load Regulation dVOUT/dILOAD REF5020 -10 mA < ILOAD < +10 mA, VIN = 3V 20 30 ppm/mA All other devices -10 mA < ILOAD < +10 mA, VIN = VOUT + 0.75 V 20 30 ppm/mA Over Temperature 60 ppm/mA SHORT-CIRCUIT CURRENT Short-Circuit Current ISC VOUT = 0 25 mA TEMP PIN Voltage Output At TA = 25C 575 mV Temperature Sensitivity 2.64 mV/C TURNON SETTLING TIME To 0.1% with CL = 1 F Turnon Settling Time s 200 POWER SUPPLY Supply Voltage VIN See Note (1) VOUT + 0.2 (1) Quiescent Current 18 0.8 V 1 mA Over Temperature 1.25 mA TEMPERATURE RANGE Specified Range -55 125 Operating Range -55 125 Thermal Resistance (1) JA C C 150 C/W For VOUT 2.5 V, the minimal supply voltage is 2.7 V. Copyright (c) 2010-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP 5 REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 www.ti.com 6.7 Typical Characteristics 7.50 8.00 6.50 7.00 5.50 6.00 4.50 5.00 3.50 4.00 2.50 Drift (ppm/C) 3.00 1.50 2.00 0.50 1.00 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 0 Population (%) Population (%) At TA = 25C, ILOAD = 0, and VIN = VOUT + 0.2 V, unless otherwise noted. For VOUT 2.5 V, the minimum supply voltage is 2.7 V. Drift (ppm/C) 0C to 85C -40C to 125C Figure 1. Temperature Drift Figure 2. Temperature Drift 0.05 Population (%) Output Voltage Accuracy (%) 0.04 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.05 0.05 0.04 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0.04 -50 -25 Output Initial Accuracy (%) 0.8 140 0.7 120 0.6 100 80 60 40 20 75 100 125 +125C +25C 0.5 -40C 0.4 0.3 0.2 0.1 0 0 10 100 1k Frequency (Hz) 10k 100k Figure 5. Power-Supply Rejection Ratio vs Frequency 6 25 50 Temperature (C) Figure 4. Output Voltage Accuracy vs Temperature 160 Dropout Voltage (V) PSRR (dB) Figure 3. Output Voltage Initial Accuracy 0 Submit Documentation Feedback -15 -10 -5 0 5 Load Current (mA) 10 15 Figure 6. Dropout Voltage vs Load Current Copyright (c) 2010-2015, Texas Instruments Incorporated Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP www.ti.com SBOS471B - APRIL 2010 - REVISED JUNE 2015 Typical Characteristics (continued) At TA = 25C, ILOAD = 0, and VIN = VOUT + 0.2 V, unless otherwise noted. For VOUT 2.5 V, the minimum supply voltage is 2.7 V. 0.9 2.50125 TEMP Pin Output Voltage (V) 2.50100 Output Voltage (V) 2.50075 2.50050 2.50025 +25C 2.50000 2.49975 2.49950 -40C 2.49925 +125C 2.49900 0.8 0.7 0.6 0.5 0.4 0.3 2.49875 -10 -5 0 Load Current (mA) 5 10 -50 Figure 7. REF5025 Output Voltage vs Load Current -25 0 25 50 Temperature (C) 75 100 125 Figure 8. Temp Pin Output vs Voltage Temperature 1050 Quiescent Current (mA) 1000 950 900 850 800 750 700 650 600 -50 -25 0 25 50 Temperature (C) 75 100 125 Figure 10. Quiescent Current vs Input Voltage Figure 9. Quiescent Current vs Temperature 0.5 35 Sourcing 30 Short-Circuit Current (mA) Line Regulation (ppm/V) 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 25 20 Sinking 15 10 5 -0.4 0 -0.5 -50 -25 0 25 50 Temperature (C) 75 100 Figure 11. Line Regulation vs Temperature Copyright (c) 2010-2015, Texas Instruments Incorporated 125 -50 -25 0 25 50 Temperature (C) 75 100 125 Figure 12. Short-Circuit Current vs Temperature Submit Documentation Feedback Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP 7 REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 www.ti.com Typical Characteristics (continued) At TA = 25C, ILOAD = 0, and VIN = VOUT + 0.2 V, unless otherwise noted. For VOUT 2.5 V, the minimum supply voltage is 2.7 V. 1mV/div VIN 2V/div VOUT 1V/div 40 s/div 1s/div REF5025, CL = 1 F Figure 14. Start-up Figure 13. NOISE +1mA VIN ILOAD 5V/div -1mA -1mA 1mA/div VOUT 5mV/div VOUT 1V/div 400 s/div 20ms/div REF5025, CL = 10 F CL = 1 F, IOUT = 1 mA Figure 15. Start-up Figure 16. Load Transient ILOAD 10mA/div +1mA +10mA +10mA ILOAD -1mA -1mA 1mA/div -10mA VOUT VOUT 5mV/div 2mV/div 100ms/div 20ms/div CL = 1 F, IOUT = 10 mA CL = 10 F, IOUT = 1 mA Figure 17. Load Transient 8 Submit Documentation Feedback Figure 18. Load Transient Copyright (c) 2010-2015, Texas Instruments Incorporated Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP www.ti.com SBOS471B - APRIL 2010 - REVISED JUNE 2015 Typical Characteristics (continued) At TA = 25C, ILOAD = 0, and VIN = VOUT + 0.2 V, unless otherwise noted. For VOUT 2.5 V, the minimum supply voltage is 2.7 V. ILOAD 10mA/div +10mA -10mA -10mA VIN 500mV/div VOUT 2mV/div VOUT 5mV/div 100ms/div 20ms/div CL = 10 F, IOUT = 10 mA CL = 1 F Figure 19. Load Transient 500mV/div 5mV/div Figure 20. Line Transient VIN VOUT 100ms/div CL = 10 F Figure 21. Line Transient Copyright (c) 2010-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP 9 REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 www.ti.com 7 Detailed Description 7.1 Overview The REF50xx devices are low-noise, low-drift, very high precision voltage references. These references can both sink and source, and are very robust with regard to line and load changes. 7.2 Functional Block Diagram VIN REF50xx R2 R1 aT (10mA at +25C) VOUT R4 TEMP aT 10kW R3 TRIM/NR 1.2V R5 60kW 1kW GND 7.3 Feature Description 7.3.1 Output Adjustment Using The TRIM/NR Pin The REF50xx provides a very accurate, factory-trimmed voltage output. However, VOUT can be adjusted using the trim and noise reduction pin (TRIM/NR, pin 5). Figure 22 shows a typical circuit that allows an output adjustment of 15 mV +VSUPPLY REF50xx DNC VIN TEMP DNC NC VOUT GND TRIM/NR 10kW 470kW 1kW Figure 22. VOUT Adjustment Using the TRIM/NR Pin The REF50xx allows access to the bandgap through the TRIM/NR pin. Placing a capacitor from the TRIM/NR pin to GND (see Figure 24) in combination with the internal R3 and R4 resistors creates a low-pass filter. A capacitance of 1 F creates a low-pass filter with the corner frequency between 10 Hz and 20 Hz. Such a filter decreases the overall noise measured on the VOUT pin by half. Higher capacitance results in a lower filter cutoff frequency, further reducing output noise. Use of this capacitor increases start-up time. 10 Submit Documentation Feedback Copyright (c) 2010-2015, Texas Instruments Incorporated Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP www.ti.com SBOS471B - APRIL 2010 - REVISED JUNE 2015 Feature Description (continued) 7.3.2 Low Temperature Drift The REF50xx is designed for minimal drift error, which is defined as the change in output voltage over temperature. The drift is calculated using the box method, as described by Equation 1: ae V - VOUTMIN o 6 Drift = c OUTMAX / 10 (ppm) e VOUT Temp Range o (1) The REF50xx features a maximum drift coefficient of 3 ppm/C for the high-grade version, and 8 ppm/C for the standard-grade. 7.3.3 Temperature Monitoring The temperature output terminal (TEMP, pin 3) provides a temperature-dependent voltage output with approximately 60-k source impedance. As seen in Figure 8, the output voltage follows the nominal relationship: VTEMP PIN = 509 mV + 2.64 x T(C) (2) This pin indicates general chip temperature, accurate to approximately 15C. Although it is not generally suitable for accurate temperature measurements, it can be used to indicate temperature changes or for temperature compensation of analog circuitry. A temperature change of 30C corresponds to an approximate 79 mV change in voltage at the TEMP pin. The TEMP pin has high output impedance (see Functional Block Diagram). Loading this pin with a lowimpedance circuit induces a measurement error; however, it does not have any effect on VOUT accuracy. To avoid errors caused by low-impedance loading, buffer the TEMP pin output with a suitable low-temperature drift operational amplifiers, such as the OPA333, OPA335, or OPA376, as shown in Figure 23. +V REF50xx DNC VTEMP 2.6mV/C OPA (1) VIN TEMP DNC NC VOUT GND TRIM/NR NOTE: (1) Low drift op amp, such as the OPA333, OPA335, or OPA376. Figure 23. Buffering the TEMP Pin Output 7.3.4 Noise Performance Typical 0.1-Hz to 10-Hz voltage noise for each member of the REF50xx family is specified in the Electrical Characteristics: Per Device table. The noise voltage increases with output voltage and operating temperature. Additional filtering can be used to improve output noise levels, although take care to ensure the output impedance does not degrade performance. For additional information about how to minimize noise and maximize performance in mixed-signal applications such as data converters, refer to the series of Analog Applications Journal articles entitled, How a Voltage Reference Affects ADC Performance. This three-part series is available for download from the TI website under three literature numbers: SLYT331, SLYT339, and SLYT355, respectively. Copyright (c) 2010-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP 11 REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 www.ti.com Feature Description (continued) +VSUPPLY REF50xx DNC VIN TEMP DNC NC VOUT GND TRIM/NR C1 1mF Figure 24. Noise Reduction Using the TRIM/NR Pin 7.4 Device Functional Modes The REF50xx is powered on when the voltage on the VIN pin is greater than VOUT + 0.2 V, except for the REF5020 and REF5025, where the minimum supply voltage is 2.7 V. The maximum input voltage for the REF50xx is 18 V. Use a supply bypass capacitor ranging from 1 F to 10 F. The total capacitive load at the output must be between 1 F to 50 F to ensure best output stability. 12 Submit Documentation Feedback Copyright (c) 2010-2015, Texas Instruments Incorporated Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP www.ti.com SBOS471B - APRIL 2010 - REVISED JUNE 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The REF50xx devices are low-noise, precision bandgap voltage references that are specifically designed for excellent initial voltage accuracy and drift. View the Functional Block Diagram of the REF50xx. When designing circuits with a voltage reference, output noise is one of the main concerns. The main source of voltage noise in the reference voltages originates from the bandgap and output amplifier, which contribute significantly to the overall noise. During the design process, it is important to minimize these sources of voltage noise. 8.2 Typical Applications 8.2.1 Negative Reference Voltage For applications requiring a negative and positive reference voltage, the REF50xx and OPA735 can be used to provide a dual-supply reference from a 5-V supply. Figure 25 shows the REF5020 used to provide a 2.5-V supply reference voltage. The low-drift performance of the REF50xx complements the low offset voltage and zero drift of the OPA735 to provide an accurate solution for split-supply applications. Care must be taken to match the temperature coefficients of R1 and R2. +5V REF5020 DNC VIN DNC NC TEMP VOUT GND TRIM/NR +2V 1mF R1 10kW R2 10kW +5V OPA735 -2V -5V NOTE: Bypass capacitors not shown. Figure 25. The REF5020 and OPA735 Create Positive and Negative Reference Voltages 8.2.1.1 Design Requirements When using REF50xx in the design, it is important to select proper capacitive load that will not create gain peaking adding noise to the output voltage. At the same time, the capacitor must be selected to provide required filtering performance for the system. In addition, input bypass capacitor and noise reduction capacitors must be added for optimum performances. 8.2.1.2 Detailed Design Procedure Proper design procedure will require first to select output capacitor. If the ESR of the capacitor is not in 1- range additional resistor must be added in series with the load capacitor. Next, add a 1-F capacitor to the NR pin to reduce internal noise of the REF50xx. Measuring output noise will confirm if the design has met the initial target. Copyright (c) 2010-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP 13 REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 www.ti.com Typical Applications (continued) 8.2.1.3 Application Curves Figure 26. Noise Measurements of Properly Design REF50xx Data Acquisition System from Figure 33 Figure 27. FFT of Data Acquisition System Design With REF50xx from Figure 33 8.2.2 Positive Reference Voltage Variable NC 1 VIN 2 8 NC +5V 7 NC +4.096V REF5040 CIN 10F TEMP 3 6 VOUT GND 4 5 TRIM COUT 1F - 50F Figure 28. REF50xx With Load Capacitor 8.2.2.1 Detailed Design Procedure 8.2.2.1.1 Load Capacitance To determine how much noise the reference voltage is contributing in a real application, this design uses the circuit presented in Figure 28. For the same conditions as power supply, input decoupling, and load current, measure the output noise for different output decoupling or load capacitors. The load capacitor type will change the low-pass filter frequency that is created on the output. This filter is determined by an added capacitor value and two parasitic components: the open-loop output impedance of the internal amplifier to the reference voltage, and the ESR of the external capacitor. Figure 29 shows a fast-Fourier-transform (FFT) plot of the output signal of the reference voltage circuit with a 10F ceramic capacitor load. The output noise level peaks at around 9 kHz because of the response of the internal amplifier of the circuit to the capacitive load (CL). This peaking is the main contributor to the overall measured noise. This output noise, measured with an analog meter over a frequency range of up to 80 kHz, is approximately 16.5 VRMS. If the voltage-reference circuit was connected to the input of an ADC, the measured noise across a 65-kHz frequency range would be 138 VPP. This noise level makes this solution adequate for 8- to 14-bit converters. 14 Submit Documentation Feedback Copyright (c) 2010-2015, Texas Instruments Incorporated Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP www.ti.com SBOS471B - APRIL 2010 - REVISED JUNE 2015 Typical Applications (continued) Figure 29. REF50xx FFT Plot of the Noise With 10-F Load Capacitor and 10- ESR Every capacitor can be represented with a complicated equivalent model, which is voltage and frequency dependent with a large number of passive components. For the purposes of this design, this model is limited to the few components. The biggest impact on the creation of the low-pass filter and stability analysis is the simplified model of equivalent series inductance and resistance. Considering good layout practice and inherently low equivalent series inductance of today's components, this model in the future analysis will be presented only by equivalent capacitance and series resistance. VCC RO ESR CL P = 1 2p * (R + ESR) * CL Z = 1 2p * ESR * CL Figure 30. Equivalent SCH Of REF50xx With Load Capacitor for Stability Analysis When evaluating the impact of ESR and CL on the performance the reference voltage, it is important to include the effect of the open-loop output resistance (RO) of the output amplifier. The combination of RO, ESR, and CL modifies the open-loop response curve by introducing one pole (fP) and one zero (fZ). The values RO, ESR, and CL determine the corner frequency of the added pole fP; and the values of ESR and CL determine the corner frequency of the added zero. The introduction of the external ESR-CL on the output of the reference voltage modifies the output amplifier open-loop gain curve. The added pole modifies the open-loop gain curve of the reference voltage output amplifier by introducing a -20 dB/decade change at the frequency fP to the already -20 dB/decade slope of the open-loop gain curve, making the slope equal to -40 dB/decade. The added zero at frequency fZ changes the open-loop gain curve back to -20 dB/decade. Copyright (c) 2010-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP 15 REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 www.ti.com Typical Applications (continued) Table 1. Noise Measurement Results for Different Load Capacitors NOISE 22 kHz LP-5P 30 kHz LP-3P 80 kHz LP-3P >500 kHz GND 0.8 1 1.8 4.9 1 F 37.8 41.7 53.7 9,017 2.2 F (cer) 41.7 46.2 55.1 60.8 10 F 33.4 33.4 35.2 38.5 10 F (cer) 37.1 37.2 37.8 39.1 20 F (cer) 33.1 33.1 33.2 34.5 47 F 23.2 23.8 24.1 26.5 UNIT VRMS Table 1 shows the measured noise values for different frequency bandwidths as well as different values and types of external capacitors. These measurements show that low-ESR (approximately 100-m) ceramic capacitors tend to increase the noise, compared to normal-ESR (approximately 2-) tantalum capacitors. This tendency is caused by a stability issue with the output amplifier and gain peaking in the amplifier frequency response. 8.2.2.1.2 Bandgap Noise Reduction R2 R1 VOUT 10k 1.2V TRIM 1k Figure 31. REF50xx Internal Structure of Trim/NR Pin The internal schematic of the REF50xx device shows that the trim pin allows direct access to the bandgap output. Figure 31 shows the trim pin connection to the internal bandgap circuit through a resistor. Adding a capacitor on the trim pin creates a lowpass filter that has a broadband attenuation of -21 dB. For example, a small 1-F capacitor adds a pole at 14.5 Hz and a zero at 160 Hz. If more filtering is needed, a larger value capacitor can be added, which will lower the filter cutoff frequency and the noise contributed by the bandgap. 16 Submit Documentation Feedback Copyright (c) 2010-2015, Texas Instruments Incorporated Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP www.ti.com SBOS471B - APRIL 2010 - REVISED JUNE 2015 Table 2. Measured Noise (VRMS) for Four Bandwidths NOISE 22 kHz (LOW-PASS 30 kHz (LOW-PASS 5-POLE) 3-POLE) 80 kHz (LOWPASS 3-POLE) > 500 kHz GND 0.8 1 1.8 4.6 2.2 F (ceramic) 42.5 47.2 61.2 68.3 2.2 F + 1 F 17.5 19.4 22.6 24.5 10 F (ceramic) 34.4 35.6 37.7 44.5 10 F + 1 F 14.1 14.4 14.9 16.4 20 F (ceramic) 34.8 34.9 35.1 35.2 20 F + 1 F 14.4 14.4 14.7 15.1 UNIT VRMS Adding a 1-F capacitor in this example filters the noise contribution of the bandgap and lowers the total noise by a factor of 2.5 times. 8.3 System Example 8.3.1 Data Acquisition Data acquisition systems often require stable voltage references to maintain accuracy. The REF50xx family features low noise, very low drift, and high initial accuracy for high-performance data converters. Figure 32 shows the REF5040 in a basic data acquisition system. +5V Input Signal 0V to 4V +5V R1 50W VDD +IN OPA365 ADS8326 C1 1.2nF -IN REF GND REF5040 VIN +5V VOUT CBYPASS 1mF C2 22mF GND Figure 32. Basic Data Acquisition System During the design of the data acquisition system, equal consideration must be given to the buffering analog input signal as well as the reference voltage. Having a properly designed input buffer with an associated RC filter is a necessary requirement, but does not ensure the maximum performance. REF5040 ESR 10uF 47uF REFIN CS 124 W ADS8326 0-4V OPA365 CLK SDO 1nF Figure 33. Complete Data Acquisition System Using REF50xx Three measurements using different components of the output are shown for this data acquisition system. Copyright (c) 2010-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP 17 REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 www.ti.com System Example (continued) Table 3. Data Acquisition Measurement Results for Different Conditions OPA365 124 , 1 nF 124 , 1 nF 124 , 100 F REF5040 10 F 10 F + 47 F 10 F + 47 F TRIM 0 F 1 F 1 F UNIT Resolution 16 16 16 States 65536 65536 65536 Bits VREF 4.096 4.096 4.096 V LSB 62.5 62.5 62.5 V VIN 4.02 4.02 4.02 V Data Std 1.07 0.53 0.41 LSB Noise 67.0 33.4 25.8 VRMS Noise 442.3 220.5 170.2 VPP SNR 86.7 92.8 95.0 dB FTT Points 32768 32768 32768 Noise Flor -128.8 -134.9 -131.7 dB Once the correct components for data acquisition system from Figure 33 are selected, measurement results can be compared to the ADS8326 data sheet specifications. Table 4. AC Performance for Data Acquisition System from Figure 33 REF5040 ADS8326 ADS8326B SYSTEM SYSTEM DATA SHEET DATA SHEET LOW ESR 10 F + 47 F TRIM UNIT 1F SNR 91 91.5 90.6 92.2 dB SINAD 87.5 88 85.7 89.5 dB SFDR 94 95 88.3 98.4 dB THD -90 -91 -87.3 -92.9 dB ENOB 14.28 14.35 13.94 14.58 Bits Table 3 shows improvements on the FFT for a properly designed system. 18 Submit Documentation Feedback Copyright (c) 2010-2015, Texas Instruments Incorporated Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP www.ti.com SBOS471B - APRIL 2010 - REVISED JUNE 2015 9 Power Supply Recommendations The maximum voltage drop between the input and output pin is 0.2 V. The minimum power supply voltage for the specific REF50xx device depends on the value of the output voltage, (VINMIN = VOUT + 0.2 V). The exception to this rule is the REF5020, which requires a minimum 2.7-V power supply for proper operation. The maximum power supply voltage for the REF50xx series is 18 V. TI recommends adding a bypass capacitor of 1 F to 10 F at the input to compensate for the layout and power supply source impedance. 9.1 Basic Connections Figure 34 shows the typical connections for the REF50xx. TI recommends a supply bypass capacitor ranging from 1 F to 10 F. A 1-F to 50-F output capacitor (CL) must be connected from VOUT to GND. The ESR value of CL must be less than or equal to 1.5 to ensure output stability. To minimize noise, the recommended ESR of CL is between 1 and 1.5 . +VSUPPLY REF50xx DNC CBYPASS 1mF to 10mF VIN TEMP DNC NC VOUT GND TRIM/NR VOUT CL 1mF to 50mF Figure 34. Basic Connections 9.2 Low Dropout Voltage The REF50xx family of voltage references features extremely low dropout voltage. With the exception of the REF5020, which has a minimum supply requirement of 2.7 V, these references can be operated with a supply of 200 mV above the output voltage in an unloaded condition. For loaded conditions, a typical dropout voltage versus load plot is shown in Figure 6 in Typical Characteristics. 10 Layout 10.1 Layout Guidelines * * * * Place the power-supply bypass capacitor as closely as possible to the VIN pin and ground pins. The recommended value of this bypass capacitor is 1 F to 10 F. If necessary, additional decoupling capacitance can be added to compensate for noisy or high-impedance power supplies. Place a 1-F noise filtering capacitor between the NR pin and ground. The output must be decoupled with a 1-F to 50-F capacitor. In series with load capacitor, add an ESR of 1 for the best noise performance. A high-frequency, 1-F capacitor can be added in parallel between the output and ground to filter noise and help with switching loads as data converters. Copyright (c) 2010-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP 19 REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 www.ti.com 10.2 Layout Example ESR Low ESR Capacitor Bypass Capacitor VIH TMP VOUT GND Trim/NR Low ESR Capacitor VOUT GND Noise Reduction Capacitor Figure 35. Recommended Layout for REF50xx 10.3 Power Dissipation The REF50xx family is specified to deliver current loads of 10 mA over the specified input voltage range. The temperature of the device increases according to the equation: TJ = TA + PD x RJA where * * * * TJ = Junction temperature (C) TA = Ambient temperature (C) PD = Power dissipated (W) RJA = Junction-to-ambient thermal resistance (C/W) (3) The REF50xx junction temperature must not exceed the absolute maximum rating of 150C. 20 Submit Documentation Feedback Copyright (c) 2010-2015, Texas Instruments Incorporated Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP www.ti.com SBOS471B - APRIL 2010 - REVISED JUNE 2015 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: * 0.05uV/degC (max), Single-Supply CMOS Zero-Drift Series Operational Amplifier, SBOS282 * REF5020 PSpice Model, SLIM160 * REF5020 TINA-TI Reference Design, SLIM159 * REF5020 TINA-TI Spice Model, SLIM158 * INA270 PSpice Model, SBOM485 * INA270 TINA-TI Reference Design, SBOC246 * INA270 TINA-TI Spice Model, SBOM306 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 5. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY REF5020-EP Click here Click here Click here Click here Click here REF5025-EP Click here Click here Click here Click here Click here REF5040-EP Click here Click here Click here Click here Click here REF5050-EP Click here Click here Click here Click here Click here 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright (c) 2010-2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP 21 REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP SBOS471B - APRIL 2010 - REVISED JUNE 2015 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright (c) 2010-2015, Texas Instruments Incorporated Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP PACKAGE OPTION ADDENDUM www.ti.com 8-Sep-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) REF5020MDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5020EP REF5025MDTEP ACTIVE SOIC D 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5025EP REF5040MDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5040EP REF5050MDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5050EP V62/10613-01XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5020EP V62/10613-02XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5040EP V62/10613-03XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5050EP V62/10613-04XE ACTIVE SOIC D 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5025EP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Sep-2017 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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OTHER QUALIFIED VERSIONS OF REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP : * Catalog: REF5020, REF5025, REF5040, REF5050 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing REF5020MDREP SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 REF5025MDTEP SOIC D 8 250 180.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 REF5040MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 REF5050MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) REF5020MDREP SOIC D 8 2500 367.0 367.0 35.0 REF5025MDTEP SOIC D 8 250 210.0 185.0 35.0 REF5040MDREP SOIC D 8 2500 367.0 367.0 35.0 REF5050MDREP SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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