ADS8326
REF5040
REF
VOUT
GND
+IN
- IN
VIN
+5 V
OPA365
Input
Signal
0 V to 4 V
+5 V +5 V
VDD
GND
CBYPASS
1 µF
R1
50 Ω
C1
1.2 nF
C2
22 µf
Product
Folder
Sample &
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Technical
Documents
Tools &
Software
Support &
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REF50xx-EP Low-Noise, Very Low Drift, Precision Voltage Reference
1 Features 3 Description
The REF50xx is a family of low-noise, very low-drift,
1• Low Temperature Drift: very high precision voltage references. These
5 ppm/°C (Maximum) references are capable of both sinking and sourcing,
• High Accuracy: and are very robust with regard to line and load
0.08% (Maximum) changes.
• Low Noise: 3 μVPP/V Excellent temperature drift and high accuracy are
• High Output Current: ±10 mA achieved using proprietary design techniques. These
features, combined with very low noise, make the
• Available in Military (–55°C to 125°C) REF50xx family ideal for use in high-precision data
Temperature Range (1) acquisition systems.
• Extended Product Life Cycle They are offered in SOIC-8 packages, and are
• Extended Product-Change Notification specified from –55°C to 125°C.
• Product Traceability Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)
• 16-Bit Data Acquisition Systems REF50xx-EP SOIC (8) 4.90 mm × 3.91 mm
• ATE Equipment (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Industrial Process Control
• Medical Instrumentation
• Optical Control Systems
• Precision Instrumentation
• Controlled Baseline
• One Assembly/Test Site
• One Fabrication Site
(1) Custom temperature ranges available
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
8.1 Application Information............................................ 13
1 Features.................................................................. 18.2 Typical Applications ............................................... 13
2 Applications ........................................................... 18.3 System Example..................................................... 17
3 Description............................................................. 19 Power Supply Recommendations...................... 19
4 Revision History..................................................... 29.1 Basic Connections .................................................. 19
5 Pin Configuration and Functions......................... 39.2 Low Dropout Voltage .............................................. 19
6 Specifications......................................................... 310 Layout................................................................... 19
6.1 Absolute Maximum Ratings ..................................... 310.1 Layout Guidelines ................................................. 19
6.2 ESD Ratings.............................................................. 310.2 Layout Example .................................................... 20
6.3 Recommended Operating Conditions....................... 410.3 Power Dissipation ................................................. 20
6.4 Thermal Information.................................................. 411 Device and Documentation Support................. 21
6.5 Electrical Characteristics: Per Device....................... 411.1 Documentation Support ....................................... 21
6.6 Electrical Characteristics: All Devices....................... 511.2 Related Links ........................................................ 21
6.7 Typical Characteristics.............................................. 611.3 Community Resources.......................................... 21
7 Detailed Description............................................ 10 11.4 Trademarks........................................................... 21
7.1 Overview................................................................. 10 11.5 Electrostatic Discharge Caution............................ 21
7.2 Functional Block Diagram....................................... 10 11.6 Glossary................................................................ 21
7.3 Feature Description................................................. 10 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 12 Information........................................................... 22
8 Application and Implementation ........................ 13
4 Revision History
Changes from Revision A (October 2012) to Revision B Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 3
• Changed title of Supply Voltage to Low Dropout Voltage ................................................................................................... 19
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1
2
3
4
8
7
6
5
DNC(1)
NC(2)
TRIM/NR
DNC(1)
VIN
TEMP
GND
VOUT
REF50xx
(1) DNC = Do not connect.
(2) NC = No internal connection.
NOTES:
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5 Pin Configuration and Functions
D Package
8- Pin SOIC
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
DNC 1 — Do not connect
Power supply voltage. Range from VOUT + 0.2 V up to 18 V. Recommended bypass
VIN 2 Power capacitor from 1 µF up to 10 µF
TEMP 3 O Temperature monitoring pin provides a temperature-dependent voltage output
GND 4 Power System ground
Output adjustment and noise reduction input. Connecting 1 µF to this pin will create low pas
TRIM/NR 5 I filter at the bandgap and reduce output noise
Very accurate, factory-trimmed voltage output. Recommended bypass capacitor from 1 µF
VOUT 6 O up to 50 µF with ESR between 1 and 1.5 Ω
NC 7 — No internal connection
DNC 8 — Do not connect
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage VIN 18 V
Output short-circuit 30 mA
Operating temperature –55 125 °C
Junction temperature, TJ150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1000
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIN VOUT + 0.2 V 18 V
IOUT –10 10 mA
6.4 Thermal Information REF502x-EP
THERMAL METRIC(1) D (SOIC) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 97.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 42.2 °C/W
RθJB Junction-to-board thermal resistance 34.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics: Per Device
At TA= 25°C, ILOAD = 0, CL= 1 μF, and VIN = (VOUT + 0.2 V) to 18 V, unless otherwise noted.
TA= 25°C TA= –55°C to 125°C
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
REF5020 (VOUT = 2.048V)(1)
OUTPUT VOLTAGE
Output Voltage VOUT 2.7 V < VIN < 18 V 2.048 V
Initial Accuracy –0.05% 0.05%
Over Temperature –0.08% 0.08%
NOISE
Output Voltage Noise f = 0.1 Hz to 10 Hz 6 μVPP
REF5025 (VOUT = 2.5 V)
OUTPUT VOLTAGE
Output Voltage VOUT 2.5 V
Initial Accuracy –0.05% 0.05%
NOISE
Output Voltage Noise f = 0.1 Hz to 10 Hz 7.5 μVPP
REF5040 (VOUT = 4.096V)
OUTPUT VOLTAGE
Output Voltage VOUT 4.096 V
Initial Accuracy –0.05% 0.05%
Over Temperature –0.08% 0.08%
NOISE
Output Voltage Noise f = 0.1 Hz to 10 Hz 12 μVPP
REF5050 (VOUT = 5 V)
OUTPUT VOLTAGE
Output Voltage VOUT 5 V
Initial Accuracy –0.05% 0.05%
Over Temperature –0.08% 0.08%
NOISE
Output Voltage Noise f = 0.1 Hz to 10 Hz 15 μVPP
(1) For VOUT ≤2.5 V, the minimum supply voltage is 2.7 V.
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6.6 Electrical Characteristics: All Devices
At TA= 25°C, ILOAD = 0, CL= 1 μF, and VIN = (VOUT + 0.2 V) to 18 V, unless otherwise noted.
TA= 25°C TA= –55°C to 125°C
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
OUTPUT VOLTAGE TEMPERATURE DRIFT
Output Voltage Temperature Drift dVOUT/dT
REF5025 4 6.5 ppm/°C
REF5050 4 6.5 ppm/°C
All other devices 3 5 ppm/°C
LINE REGULATION
Line Regulation dVOUT/dVIN
REF5020(1) VIN = 2.7 V to 18V 0.1 1 ppm/V
All other devices VIN = VOUT + 0.2 V 0.1 1 ppm/V
Over Temperature 1 3 ppm/V
LOAD REGULATION
Load Regulation dVOUT/dILOAD
REF5020 –10 mA < ILOAD < +10 mA, VIN = 20 30 ppm/mA
3 V
All other devices –10 mA < ILOAD < +10 mA, VIN = 20 30 ppm/mA
VOUT + 0.75 V
Over Temperature 60 ppm/mA
SHORT-CIRCUIT CURRENT
Short-Circuit Current ISC VOUT = 0 25 mA
TEMP PIN
Voltage Output At TA= 25°C 575 mV
Temperature Sensitivity 2.64 mV/°C
TURNON SETTLING TIME
Turnon Settling Time To 0.1% with CL= 1 μF 200 μs
POWER SUPPLY
Supply Voltage VIN See Note (1) VOUT + 18 V
0.2(1)
Quiescent Current 0.8 1 mA
Over Temperature 1.25 mA
TEMPERATURE RANGE
Specified Range –55 125 °C
Operating Range –55 125 °C
Thermal Resistance θJA 150 °C/W
(1) For VOUT ≤2.5 V, the minimal supply voltage is 2.7 V.
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10
Frequency(Hz)
160
140
120
100
80
60
40
20
0
PSRR(dB)
100k100 1k 10k
-15 -10 -5
LoadCurrent(mA)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
DropoutVoltage(V)
150 5 10
+125 C°
+25 C°
- °40 C
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
OutputInitialAccuracy(%)
Population(%)
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
Drift(ppm/ C)°
Population(%)
0
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
5.50
6.00
6.50
7.00
7.50
8.00
Drift(ppm/ C)°
Population(%)
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6.7 Typical Characteristics
At TA= 25°C, ILOAD = 0, and VIN = VOUT + 0.2 V, unless otherwise noted. For VOUT ≤2.5 V, the minimum supply voltage is 2.7
V.
0°C to 85°C –40°C to 125°C
Figure 1. Temperature Drift Figure 2. Temperature Drift
Figure 3. Output Voltage Initial Accuracy Figure 4. Output Voltage Accuracy vs Temperature
Figure 5. Power-Supply Rejection Ratio vs Frequency Figure 6. Dropout Voltage vs Load Current
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-50 -25
Temperature( C)°
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
LineRegulation(ppm/V)
1250 25 50 75 100
-50 -25
Temperature( C)°
35
30
25
20
15
10
5
0
Short-CircuitCurrent(mA)
1250 25 50 75 100
Sourcing
Sinking
-50 -25
Temperature( C)°
1050
1000
950
900
850
800
750
700
650
600
QuiescentCurrent(mA)
1250 25 50 75 100
-50 -25
Temperature( C)°
0.9
0.8
0.7
0.6
0.5
0.4
0.3
TEMPPinOutputVoltage(V)
1250 25 50 75 100
-10 -5
Load Current (mA)
2.50125
2.50100
2.50075
2.50050
2.50025
2.50000
2.49975
2.49950
2.49925
2.49900
2.49875
Output Voltage (V)
100 5
+125 C°
+25 C°
- °40 C
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Typical Characteristics (continued)
At TA= 25°C, ILOAD = 0, and VIN = VOUT + 0.2 V, unless otherwise noted. For VOUT ≤2.5 V, the minimum supply voltage is 2.7
V.
Figure 7. REF5025 Output Voltage vs Load Current Figure 8. Temp Pin Output vs Voltage Temperature
Figure 10. Quiescent Current vs Input Voltage
Figure 9. Quiescent Current vs Temperature
Figure 11. Line Regulation vs Temperature Figure 12. Short-Circuit Current vs Temperature
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20 s/divm
-10mA
+10mA+10mA
ILOAD
VOUT
2mV/div
10mA/div
100 s/divm
-1mA -1mA
+1mA
ILOAD
VOUT
5mV/div
1mA/div
400 µs/div
5V/div
1V/div
VOUT
VIN
20 s/divm
-1mA -1mA
+1mA
ILOAD
VOUT
5mV/div
1mA/div
1s/div
1 V/divm
40µs/div
2V/div
1V/div
VOUT
VIN
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Typical Characteristics (continued)
At TA= 25°C, ILOAD = 0, and VIN = VOUT + 0.2 V, unless otherwise noted. For VOUT ≤2.5 V, the minimum supply voltage is 2.7
V.
REF5025, CL= 1 μF
Figure 14. Start-up
Figure 13. NOISE
REF5025, CL= 10 μF CL= 1 μF, IOUT = 1 mA
Figure 15. Start-up Figure 16. Load Transient
CL= 1 μF, IOUT = 10 mA CL= 10 μF, IOUT = 1 mA
Figure 17. Load Transient Figure 18. Load Transient
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100 s/divm
VOUT
VIN
5mV/div
500mV/div
20ms/div
VOUT
VIN
5mV/div
500mV/div
100 s/divm
-10mA -10mA
+10mA
ILOAD
VOUT
2mV/div
10mA/div
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Typical Characteristics (continued)
At TA= 25°C, ILOAD = 0, and VIN = VOUT + 0.2 V, unless otherwise noted. For VOUT ≤2.5 V, the minimum supply voltage is 2.7
V.
CL= 10 μF, IOUT = 10 mA CL= 1 μF
Figure 19. Load Transient Figure 20. Line Transient
CL= 10 μF
Figure 21. Line Transient
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DNC
TEMP VOUT
VIN
GND
DNC
NC
TRIM/NR
REF50xx
+VSUPPLY
10kW
1kW
470kW
R5
60kW
REF50xx
TEMP VOUT
GND
TRIM/NR
VIN
aT
aT
(10 Am
at+25 C)°
R2 R1
R3
R4
10kW
1kW
1.2V
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7 Detailed Description
7.1 Overview
The REF50xx devices are low-noise, low-drift, very high precision voltage references. These references can both
sink and source, and are very robust with regard to line and load changes.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Output Adjustment Using The TRIM/NR Pin
The REF50xx provides a very accurate, factory-trimmed voltage output. However, VOUT can be adjusted using
the trim and noise reduction pin (TRIM/NR, pin 5). Figure 22 shows a typical circuit that allows an output
adjustment of ±15 mV
Figure 22. VOUT Adjustment Using the TRIM/NR Pin
The REF50xx allows access to the bandgap through the TRIM/NR pin. Placing a capacitor from the TRIM/NR pin
to GND (see Figure 24) in combination with the internal R3and R4resistors creates a low-pass filter. A
capacitance of 1 μF creates a low-pass filter with the corner frequency between 10 Hz and 20 Hz. Such a filter
decreases the overall noise measured on the VOUT pin by half. Higher capacitance results in a lower filter cutoff
frequency, further reducing output noise. Use of this capacitor increases start-up time.
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DNC
TEMP VOUT
VIN
GND
DNC
NC
TRIM/NR
REF50xx
VTEMP
2.6mV/ C°OPA(1)
NOTE:(1)Lowdriftopamp,suchastheOPA333,OPA335,orOPA376.
+V
6
OUTMAX OUTMIN
OUT
V V
Drift 10 (ppm)
V Temp Range
æ ö
-
= ´
ç ÷
´
è ø
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Feature Description (continued)
7.3.2 Low Temperature Drift
The REF50xx is designed for minimal drift error, which is defined as the change in output voltage over
temperature. The drift is calculated using the box method, as described by Equation 1:
(1)
The REF50xx features a maximum drift coefficient of 3 ppm/°C for the high-grade version, and 8 ppm/°C for the
standard-grade.
7.3.3 Temperature Monitoring
The temperature output terminal (TEMP, pin 3) provides a temperature-dependent voltage output with
approximately 60-kΩsource impedance. As seen in Figure 8, the output voltage follows the nominal relationship:
VTEMP PIN = 509 mV + 2.64 × T(°C) (2)
This pin indicates general chip temperature, accurate to approximately ±15°C. Although it is not generally
suitable for accurate temperature measurements, it can be used to indicate temperature changes or for
temperature compensation of analog circuitry. A temperature change of 30°C corresponds to an approximate 79
mV change in voltage at the TEMP pin.
The TEMP pin has high output impedance (see Functional Block Diagram). Loading this pin with a low-
impedance circuit induces a measurement error; however, it does not have any effect on VOUT accuracy. To
avoid errors caused by low-impedance loading, buffer the TEMP pin output with a suitable low-temperature drift
operational amplifiers, such as the OPA333,OPA335,orOPA376, as shown in Figure 23.
Figure 23. Buffering the TEMP Pin Output
7.3.4 Noise Performance
Typical 0.1-Hz to 10-Hz voltage noise for each member of the REF50xx family is specified in the Electrical
Characteristics: Per Device table. The noise voltage increases with output voltage and operating temperature.
Additional filtering can be used to improve output noise levels, although take care to ensure the output
impedance does not degrade performance.
For additional information about how to minimize noise and maximize performance in mixed-signal applications
such as data converters, refer to the series of Analog Applications Journal articles entitled, How a Voltage
Reference Affects ADC Performance. This three-part series is available for download from the TI website under
three literature numbers: SLYT331,SLYT339, and SLYT355, respectively.
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DNC
TEMP VOUT
VIN
GND
DNC
NC
TRIM/NR
REF50xx
C1
1 Fm
+VSUPPLY
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Feature Description (continued)
Figure 24. Noise Reduction Using the TRIM/NR Pin
7.4 Device Functional Modes
The REF50xx is powered on when the voltage on the VIN pin is greater than VOUT + 0.2 V, except for the
REF5020 and REF5025, where the minimum supply voltage is 2.7 V. The maximum input voltage for the
REF50xx is 18 V. Use a supply bypass capacitor ranging from 1 μF to 10 μF. The total capacitive load at the
output must be between 1 μF to 50 μF to ensure best output stability.
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-2V
+2V
+5V
NOTE: Bypass capacitors not shown.
R1
10kWR2
10kW
-5V
OPA735
+5V
DNC
TEMP VOUT
VIN
GND
DNC
NC
TRIM/NR
REF5020
1 Fm
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The REF50xx devices are low-noise, precision bandgap voltage references that are specifically designed for
excellent initial voltage accuracy and drift. View the Functional Block Diagram of the REF50xx.
When designing circuits with a voltage reference, output noise is one of the main concerns. The main source of
voltage noise in the reference voltages originates from the bandgap and output amplifier, which contribute
significantly to the overall noise. During the design process, it is important to minimize these sources of voltage
noise.
8.2 Typical Applications
8.2.1 Negative Reference Voltage
For applications requiring a negative and positive reference voltage, the REF50xx and OPA735 can be used to
provide a dual-supply reference from a 5-V supply. Figure 25 shows the REF5020 used to provide a 2.5-V supply
reference voltage. The low-drift performance of the REF50xx complements the low offset voltage and zero drift of
the OPA735 to provide an accurate solution for split-supply applications. Care must be taken to match the
temperature coefficients of R1and R2.
Figure 25. The REF5020 and OPA735 Create Positive and Negative Reference Voltages
8.2.1.1 Design Requirements
When using REF50xx in the design, it is important to select proper capacitive load that will not create gain
peaking adding noise to the output voltage. At the same time, the capacitor must be selected to provide required
filtering performance for the system. In addition, input bypass capacitor and noise reduction capacitors must be
added for optimum performances.
8.2.1.2 Detailed Design Procedure
Proper design procedure will require first to select output capacitor. If the ESR of the capacitor is not in 1-Ω
range additional resistor must be added in series with the load capacitor. Next, add a 1-µF capacitor to the NR
pin to reduce internal noise of the REF50xx. Measuring output noise will confirm if the design has met the initial
target.
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NC
VIN
TEMP
GND
REF5040
18NC
Variable
+4.096V
C
1µF - 50µF
OUT
+5V
C
10µF
IN
2
3
4
NC
VOUT
TRIM
7
6
5
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Typical Applications (continued)
8.2.1.3 Application Curves
Figure 26. Noise Measurements of Properly Design Figure 27. FFT of Data Acquisition System Design With
REF50xx Data Acquisition System from Figure 33 REF50xx from Figure 33
8.2.2 Positive Reference Voltage
Figure 28. REF50xx With Load Capacitor
8.2.2.1 Detailed Design Procedure
8.2.2.1.1 Load Capacitance
To determine how much noise the reference voltage is contributing in a real application, this design uses the
circuit presented in Figure 28. For the same conditions as power supply, input decoupling, and load current,
measure the output noise for different output decoupling or load capacitors. The load capacitor type will change
the low-pass filter frequency that is created on the output. This filter is determined by an added capacitor value
and two parasitic components: the open-loop output impedance of the internal amplifier to the reference voltage,
and the ESR of the external capacitor.
Figure 29 shows a fast-Fourier-transform (FFT) plot of the output signal of the reference voltage circuit with a 10-
μF ceramic capacitor load. The output noise level peaks at around 9 kHz because of the response of the internal
amplifier of the circuit to the capacitive load (CL).
This peaking is the main contributor to the overall measured noise. This output noise, measured with an analog
meter over a frequency range of up to 80 kHz, is approximately 16.5 μVRMS. If the voltage-reference circuit was
connected to the input of an ADC, the measured noise across a 65-kHz frequency range would be 138 μVPP.
This noise level makes this solution adequate for 8- to 14-bit converters.
14 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP
VCC
ESR
CL
RO
P
L
1
ƒ2 • (R ESR) • C
=
p +
Z
L
1
ƒ2 • ESR • C
=
p
REF5020-EP
,
REF5025-EP
,
REF5040-EP
,
REF5050-EP
www.ti.com
SBOS471B –APRIL 2010–REVISED JUNE 2015
Typical Applications (continued)
Figure 29. REF50xx FFT Plot of the Noise
With 10-µF Load Capacitor and 10-µΩESR
Every capacitor can be represented with a complicated equivalent model, which is voltage and frequency
dependent with a large number of passive components. For the purposes of this design, this model is limited to
the few components. The biggest impact on the creation of the low-pass filter and stability analysis is the
simplified model of equivalent series inductance and resistance. Considering good layout practice and inherently
low equivalent series inductance of today’s components, this model in the future analysis will be presented only
by equivalent capacitance and series resistance.
Figure 30. Equivalent SCH Of REF50xx With Load Capacitor for Stability Analysis
When evaluating the impact of ESR and CLon the performance the reference voltage, it is important to include
the effect of the open-loop output resistance (RO) of the output amplifier. The combination of RO, ESR, and CL
modifies the open-loop response curve by introducing one pole (fP) and one zero (fZ). The values RO, ESR, and
CLdetermine the corner frequency of the added pole fP; and the values of ESR and CLdetermine the corner
frequency of the added zero.
The introduction of the external ESR-CL on the output of the reference voltage modifies the output amplifier
open-loop gain curve. The added pole modifies the open-loop gain curve of the reference voltage output amplifier
by introducing a –20 dB/decade change at the frequency fPto the already –20 dB/decade slope of the open-loop
gain curve, making the slope equal to –40 dB/decade. The added zero at frequency fZchanges the open-loop
gain curve back to –20 dB/decade.
Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP
VOUT
TRIM
R2 R1
10k
1k
1.2V
REF5020-EP
,
REF5025-EP
,
REF5040-EP
,
REF5050-EP
SBOS471B –APRIL 2010–REVISED JUNE 2015
www.ti.com
Typical Applications (continued)
Table 1. Noise Measurement Results for Different Load Capacitors
22 kHz 30 kHz 80 kHz
NOISE >500 kHz UNIT
LP-5P LP-3P LP-3P
GND 0.8 1 1.8 4.9
1 µF 37.8 41.7 53.7 9,017
2.2 µF (cer) 41.7 46.2 55.1 60.8
10 µF 33.4 33.4 35.2 38.5 µVRMS
10 µF (cer) 37.1 37.2 37.8 39.1
20 µF (cer) 33.1 33.1 33.2 34.5
47 µF 23.2 23.8 24.1 26.5
Table 1 shows the measured noise values for different frequency bandwidths as well as different values and
types of external capacitors. These measurements show that low-ESR (approximately 100-mΩ) ceramic
capacitors tend to increase the noise, compared to normal-ESR (approximately 2-Ω) tantalum capacitors. This
tendency is caused by a stability issue with the output amplifier and gain peaking in the amplifier frequency
response.
8.2.2.1.2 Bandgap Noise Reduction
Figure 31. REF50xx Internal Structure of Trim/NR Pin
The internal schematic of the REF50xx device shows that the trim pin allows direct access to the bandgap
output. Figure 31 shows the trim pin connection to the internal bandgap circuit through a resistor. Adding a
capacitor on the trim pin creates a lowpass filter that has a broadband attenuation of −21 dB.
For example, a small 1-μF capacitor adds a pole at 14.5 Hz and a zero at 160 Hz. If more filtering is needed, a
larger value capacitor can be added, which will lower the filter cutoff frequency and the noise contributed by the
bandgap.
16 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP
ADS8326
CS
CLK
SDO
1nF
124 W
10uF
ESR
47uF
0-4V
OPA365
REF5040
REFIN
ADS8326
REF5040
REF
VOUT
GND
+IN
-IN
VIN
+5V
OPA365
Input
Signal
0Vto4V
+5V +5V
VDD
GND
CBYPASS
1 Fm
R1
50W
C1
1.2nF
C2
22 Fm
REF5020-EP
,
REF5025-EP
,
REF5040-EP
,
REF5050-EP
www.ti.com
SBOS471B –APRIL 2010–REVISED JUNE 2015
Table 2. Measured Noise (µVRMS) for Four Bandwidths
22 kHz (LOW-PASS 30 kHz (LOW-PASS 80 kHz (LOW-
NOISE > 500 kHz UNIT
5-POLE) 3-POLE) PASS 3-POLE)
GND 0.8 1 1.8 4.6
2.2 µF (ceramic) 42.5 47.2 61.2 68.3
2.2 µF + 1 µF 17.5 19.4 22.6 24.5
10 µF (ceramic) 34.4 35.6 37.7 44.5 µVRMS
10 µF + 1 µF 14.1 14.4 14.9 16.4
20 µF (ceramic) 34.8 34.9 35.1 35.2
20 µF + 1 µF 14.4 14.4 14.7 15.1
Adding a 1-μF capacitor in this example filters the noise contribution of the bandgap and lowers the total noise by
a factor of 2.5 times.
8.3 System Example
8.3.1 Data Acquisition
Data acquisition systems often require stable voltage references to maintain accuracy. The REF50xx family
features low noise, very low drift, and high initial accuracy for high-performance data converters. Figure 32
shows the REF5040 in a basic data acquisition system.
Figure 32. Basic Data Acquisition System
During the design of the data acquisition system, equal consideration must be given to the buffering analog input
signal as well as the reference voltage. Having a properly designed input buffer with an associated RC filter is a
necessary requirement, but does not ensure the maximum performance.
Figure 33. Complete Data Acquisition System Using REF50xx
Three measurements using different components of the output are shown for this data acquisition system.
Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP
REF5020-EP
,
REF5025-EP
,
REF5040-EP
,
REF5050-EP
SBOS471B –APRIL 2010–REVISED JUNE 2015
www.ti.com
System Example (continued)
Table 3. Data Acquisition Measurement Results for Different Conditions
OPA365 124 Ω, 1 nF 124 Ω, 1 nF 124 Ω, 100 µF
REF5040 10 µF 10 µF + 47 µF 10 µF + 47 µF UNIT
TRIM 0 µF 1 µF 1 µF
Resolution 16 16 16 Bits
States 65536 65536 65536
VREF 4.096 4.096 4.096 V
LSB 62.5 62.5 62.5 µV
VIN 4.02 4.02 4.02 V
Data Std 1.07 0.53 0.41 LSB
Noise 67.0 33.4 25.8 µVRMS
Noise 442.3 220.5 170.2 µVPP
SNR 86.7 92.8 95.0 dB
FTT Points 32768 32768 32768
Noise Flor –128.8 –134.9 –131.7 dB
Once the correct components for data acquisition system from Figure 33 are selected, measurement results can
be compared to the ADS8326 data sheet specifications.
Table 4. AC Performance for Data Acquisition System from Figure 33
ADS8326 ADS8326B SYSTEM SYSTEM
REF5040 DATA SHEET DATA SHEET LOW ESR 10 µF + 47 µF UNIT
TRIM 1µF
SNR 91 91.5 90.6 92.2 dB
SINAD 87.5 88 85.7 89.5 dB
SFDR 94 95 88.3 98.4 dB
THD –90 –91 –87.3 –92.9 dB
ENOB 14.28 14.35 13.94 14.58 Bits
Table 3 shows improvements on the FFT for a properly designed system.
18 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP
DNC
TEMP VOUT
VIN
GND
DNC
NC
TRIM/NR
REF50xx
CBYPASS
1 Fto10 Fm m
CL
1 Fto50 Fm m
+VSUPPLY
VOUT
REF5020-EP
,
REF5025-EP
,
REF5040-EP
,
REF5050-EP
www.ti.com
SBOS471B –APRIL 2010–REVISED JUNE 2015
9 Power Supply Recommendations
The maximum voltage drop between the input and output pin is 0.2 V. The minimum power supply voltage for the
specific REF50xx device depends on the value of the output voltage, (VINMIN = VOUT + 0.2 V). The exception to
this rule is the REF5020, which requires a minimum 2.7-V power supply for proper operation. The maximum
power supply voltage for the REF50xx series is 18 V. TI recommends adding a bypass capacitor of 1 μF to 10
μF at the input to compensate for the layout and power supply source impedance.
9.1 Basic Connections
Figure 34 shows the typical connections for the REF50xx. TI recommends a supply bypass capacitor ranging
from 1 μF to 10 μF. A 1-μF to 50-μF output capacitor (CL) must be connected from VOUT to GND. The ESR value
of CLmust be less than or equal to 1.5 Ωto ensure output stability. To minimize noise, the recommended ESR of
CLis between 1 Ωand 1.5 Ω.
Figure 34. Basic Connections
9.2 Low Dropout Voltage
The REF50xx family of voltage references features extremely low dropout voltage. With the exception of the
REF5020, which has a minimum supply requirement of 2.7 V, these references can be operated with a supply of
200 mV above the output voltage in an unloaded condition. For loaded conditions, a typical dropout voltage
versus load plot is shown in Figure 6 in Typical Characteristics.
10 Layout
10.1 Layout Guidelines
• Place the power-supply bypass capacitor as closely as possible to the VIN pin and ground pins. The
recommended value of this bypass capacitor is 1 μF to 10 μF. If necessary, additional decoupling
capacitance can be added to compensate for noisy or high-impedance power supplies.
• Place a 1-µF noise filtering capacitor between the NR pin and ground.
• The output must be decoupled with a 1-µF to 50-µF capacitor. In series with load capacitor, add an ESR of 1
Ωfor the best noise performance.
• A high-frequency, 1-µF capacitor can be added in parallel between the output and ground to filter noise and
help with switching loads as data converters.
Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP
Low ESR
Capacitor
ESR
VIH
TMP
GND
VOUT
Trim/NR
Bypass
Capacitor
Noise
Reduction
Capacitor
Low ESR
Capacitor
VOUT
GND
REF5020-EP
,
REF5025-EP
,
REF5040-EP
,
REF5050-EP
SBOS471B –APRIL 2010–REVISED JUNE 2015
www.ti.com
10.2 Layout Example
Figure 35. Recommended Layout for REF50xx
10.3 Power Dissipation
The REF50xx family is specified to deliver current loads of ±10 mA over the specified input voltage range. The
temperature of the device increases according to the equation:
TJ= TA+ PD× RθJA
where
• TJ= Junction temperature (°C)
• TA= Ambient temperature (°C)
• PD= Power dissipated (W)
• RθJA = Junction-to-ambient thermal resistance (°C/W) (3)
The REF50xx junction temperature must not exceed the absolute maximum rating of 150°C.
20 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP
REF5020-EP
,
REF5025-EP
,
REF5040-EP
,
REF5050-EP
www.ti.com
SBOS471B –APRIL 2010–REVISED JUNE 2015
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•0.05uV/degC (max), Single-Supply CMOS Zero-Drift Series Operational Amplifier,SBOS282
• REF5020 PSpice Model, SLIM160
• REF5020 TINA-TI Reference Design, SLIM159
• REF5020 TINA-TI Spice Model, SLIM158
• INA270 PSpice Model, SBOM485
• INA270 TINA-TI Reference Design, SBOC246
• INA270 TINA-TI Spice Model, SBOM306
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
REF5020-EP Click here Click here Click here Click here Click here
REF5025-EP Click here Click here Click here Click here Click here
REF5040-EP Click here Click here Click here Click here Click here
REF5050-EP Click here Click here Click here Click here Click here
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP
REF5020-EP
,
REF5025-EP
,
REF5040-EP
,
REF5050-EP
SBOS471B –APRIL 2010–REVISED JUNE 2015
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: REF5020-EP REF5025-EP REF5040-EP REF5050-EP
PACKAGE OPTION ADDENDUM
www.ti.com 8-Sep-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
REF5020MDREP ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5020EP
REF5025MDTEP ACTIVE SOIC D 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5025EP
REF5040MDREP ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5040EP
REF5050MDREP ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5050EP
V62/10613-01XE ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5020EP
V62/10613-02XE ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5040EP
V62/10613-03XE ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5050EP
V62/10613-04XE ACTIVE SOIC D 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 5025EP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 8-Sep-2017
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF REF5020-EP, REF5025-EP, REF5040-EP, REF5050-EP :
•Catalog: REF5020, REF5025, REF5040, REF5050
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
REF5020MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
REF5025MDTEP SOIC D 8 250 180.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
REF5040MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
REF5050MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Sep-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
REF5020MDREP SOIC D 8 2500 367.0 367.0 35.0
REF5025MDTEP SOIC D 8 250 210.0 185.0 35.0
REF5040MDREP SOIC D 8 2500 367.0 367.0 35.0
REF5050MDREP SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Sep-2015
Pack Materials-Page 2
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Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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