LP2997M/NOPB - Texas Instruments

VTT

LP2997

PVIN

VDDQ

VREF

AVIN

VREF =0.9V

VSENSE

GND

AVIN = 2.5V

VTT

= 0.9V

VDDQ = 1.8V

CIN COUT

CREF

LP2997

www.ti.com

SNVS295F –MAY 2004–REVISED APRIL 2013

LP2997 DDR-II Termination Regulator

Check for Samples: LP2997

1FEATURES DESCRIPTION

The LP2997 linear regulator is designed to meet the

2• Source and Sink Current JEDEC SSTL-18 specifications for termination of

• Low Output Voltage Offset DDR-II memory. The device contains a high-speed

• No External Resistors Required operational amplifier to provide excellent response to

load transients. The output stage prevents shoot

• Linear Topology through while delivering 500mA continuous current

• Suspend to Ram (STR) Functionality and transient peaks up to 900mA in the application as

• Low External Component Count required for DDR-II SDRAM termination. The LP2997

also incorporates a VSENSE pin to provide superior

• Thermal Shutdown load regulation and a VREF output as a reference for

• Available in SOIC-8, SO PowerPAD-8 Packages the chipset and DIMMs.

An additional feature found on the LP2997 is an

APPLICATIONS active low shutdown (SD) pin that provides Suspend

• DDR-II Termination Voltage To RAM (STR) functionality. When SD is pulled low

• SSTL-18 Termination the VTT output will tri-state providing a high

impedance output, but, VREF will remain active. A

power savings advantage can be obtained in this

mode through lower quiescent current.

Typical Application Circuit

Figure 1. Typical Application Circuit

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

VDDQ

PVIN

AVIN

VSENSE

VREF

GND VTT

GND

VDDQ

PVIN

AVIN

VSENSE

VREF

GND VTT

LP2997

SNVS295F –MAY 2004–REVISED APRIL 2013

www.ti.com

Connection Diagram

Figure 2. SO PowerPAD-8 Layout Figure 3. SOIC-8 Layout

See Package Number DDA (R-PDSO-G8) See Package Number D0008A

PIN DESCRIPTIONS

SOIC-8 Pin or Name Function

SO PowerPAD-8 Pin

1 GND Ground

2 SD Shutdown

3 VSENSE Feedback pin for regulating VTT.

4 VREF Buffered internal reference voltage of VDDQ/2

5 VDDQ Input for internal reference equal to VDDQ/2

6 AVIN Analog input pin

7 PVIN Power input pin

8 VTT Output voltage for connection to termination resistors

EP Exposed pad thermal connection Connect to Ground

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)(2)

AVIN to GND −0.3V to +6V

PVIN to GND -0.3V to AVIN

VDDQ(3) −0.3V to +6V

Storage Temp. Range −65°C to +150°C

Junction Temperature 150°C

Lead Temperature (Soldering, 10 sec) 260°C

SOIC-8 Thermal Resistance (θJA) 151°C/W

SO PowerPAD-8 Thermal Resistance (θJA) 43°C/W

Minimum ESD Rating(4) 1kV

(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which

the device is intended to be functional, but does not ensure specific performance limits. For specific specifications and test conditions

see Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.

(4) The human body model is a 100pF capacitor discharged through a 1.5kΩresistor into each pin.

Operating Range

Junction Temp. Range(1) 0°C to +125°C

AVIN to GND 2.2V to 5.5V

(1) At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at

θJA = 151.2° C/W junction to ambient with no heat sink.

Product Folder Links: LP2997

LP2997

www.ti.com

SNVS295F –MAY 2004–REVISED APRIL 2013

Electrical Characteristics

Specifications with standard typeface are for TJ= 25°C and limits in boldface type apply over the full Operating

Temperature Range (TJ= 0°C to +125°C)(1). Unless otherwise specified, AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V.

Symbol Parameter Conditions Min Typ Max Units

VREF VREF Voltage PVIN = VDDQ = 1.7V 0.837 0.860 0.887

PVIN = VDDQ = 1.8V 0.887 0.910 0.937 V

PVIN = VDDQ = 1.9V 0.936 0.959 0.986

ZVREF VREF Output Impedance IREF = -30 to +30 μA 2.5 kΩ

VTT VTT Output Voltage IOUT = 0A

PVIN = VDDQ = 1.7V 0.822 0.856 0.887

PVIN = VDDQ = 1.8V 0.874 0.908 0.939

PVIN = VDDQ = 1.9V 0.923 0.957 0.988 V

IOUT = ±0.5A(2)

PVIN = VDDQ = 1.7V 0.828 0.856 0.890

PVIN = VDDQ = 1.8V 0.878 0.908 0.940

PVIN = VDDQ = 1.9V 0.928 0.957 0.990

VosTT/VTT VTT Output Voltage Offset IOUT = 0A -25 025

(VREF-VTT) IOUT = -0.5A -25 025 mV

IOUT = +0.5A -25 025

IQQuiescent Current(3) IOUT = 0A(3) 320 500 µA

ZVDDQ VDDQ Input Impedance 100 kΩ

ISD Quiescent Current in SD = 0V 115 150 µA

Shutdown(3)

IQ_SD Shutdown Leakage Current SD = 0V 2 5µA

VIH Minimum Shutdown High 1.9 V

Level

VIL Maximum Shutdown Low 0.8 V

Level

ISENSE VSENSE Input Current 13 nA

TSD Thermal Shutdown See(4) 165 Celsius

TSD_HYS Thermal Shutdown 10 Celsius

Hysteresis

(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using

Statistical Quality Control (SQC) methods. The limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) VTT load regulation is tested by using a 10 ms current pulse and measuring VTT.

(3) Quiescent current defined as the current flow into AVIN.

(4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal

resistance, θJA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die

temperature and the regulator will go into thermal shutdown.

Product Folder Links: LP2997

0 1 2 3 4 5 6

VDDQ (V)

0.5

1.5

2.5

VTT (V)

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

100

150

200

250

300

350

400

IQ (uA)

0oC

125oC

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

0.5

1.5

2.5

3.5

VSD (V)

0 1 2 3 4 5 6

VDDQ (V)

0.5

1.5

2.5

VREF (V)

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

100

150

200

250

300

350

400

IQ (uA)

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

150

300

450

600

750

900

1050

IQ (uA)

LP2997

SNVS295F –MAY 2004–REVISED APRIL 2013

www.ti.com

Typical Performance Characteristics

Iq vs AVIN in SD Iq vs AVIN

Figure 4. Figure 5.

VIH and VIL VREF vs VDDQ

Figure 6. Figure 7.

VTT vs VDDQ Iq vs AVIN in SD Temperature

Figure 8. Figure 9.

Product Folder Links: LP2997

VTT

PVIN

VDDQ

GND

AVIN

VSENSE

50k

VREF

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

1.2

1.4

1.6

1.8

2.2

2.4

OUTPUT CURRENT (A)

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

150

300

450

600

750

900

1050

IQ (uA)

0oC

25oC

85oC

2 2.5 3 3.5 4 4.5 5 5.5

AVIN (V)

0.2

0.4

0.6

0.8

1.2

1.4

OUTPUT CURRENT (A)

LP2997

www.ti.com

SNVS295F –MAY 2004–REVISED APRIL 2013

Typical Performance Characteristics (continued)

Maximum Sourcing Current vs AVIN

Iq vs AVIN Temperature (VDDQ = 1.8V, PVIN = 1.8V)

Figure 10. Figure 11.

Maximum Sinking Current vs AVIN

(VDDQ = 1.8V)

Figure 12.

Block Diagram

Product Folder Links: LP2997

LP2997

SNVS295F –MAY 2004–REVISED APRIL 2013

www.ti.com

DESCRIPTION

The LP2997 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-18. The

output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The

output stage has been designed to maintain excellent load regulation while preventing shoot through. The

LP2997 also incorporates two distinct power rails that separates the analog circuitry from the power output stage.

This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the LP2997

to provide a termination solution for the next generation of DDR-SDRAM memory (DDRII).

Pin Descriptions

AVIN AND PVIN AVIN and PVIN are the input supply pins for the LP2997. AVIN is used to supply all the internal control circuitry. PVIN,

however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the capability to work off

separate supplies, under the condition that AVIN is always greater than or equal to PVIN. For SSTL-18 applications, it is recommended to

connect PVIN to the 1.8V rail used for the memory core and AVIN to a rail within its operating range of 2.2V to 5.5V (typically a 2.5V

supply). PVIN should always be used with either a 1.8V or 2.5V rail. This prevents the thermal limit from tripping because of excessive

internal power dissipation. If the junction temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to

the manual shutdown where VTT is tri-stated and VREF remains active. A lower rail such as 1.5V can be used but it will reduce the maximum

output current, therefore it is not recommended for most termination schemes.

VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor

divider of two internal 50kΩresistors. This ensures that VTT will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a

remote sense. This can be achieved by connecting VDDQ directly to the 1.8V rail at the DIMM instead of PVIN. This ensures that the

reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-18 applications

VDDQ will be a 1.8V signal, which will create a 0.9V termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT

over temperature).

VSENSE The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination

resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the LP2997 then the long trace will

cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. The VSENSE pin can be used to

improve this performance, by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus.

If remote load regulation is not used then the VSENSE pin must still be connected to VTT. Care should be taken when a long VSENSE trace is

implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small

0.1uF ceramic capacitor placed next to the VSENSE pin can help filter any high frequency signals and preventing errors.

SHUTDOWN The LP2997 contains an active low shutdown pin that can be used for suspend to RAM functionality. In this condition the VTT

output will tri-state while the VREF output remains active providing a constant reference signal for the memory and chipset. During shutdown

VTT should not be exposed to voltages that exceed PVIN. With the shutdown pin asserted low the quiescent current of the LP2997 will drop,

however, VDDQ will always maintain its constant impedance of 100kΩfor generating the internal reference. Therefore, to calculate the total

power loss in shutdown both currents need to be considered. For more information refer to the Thermal Dissipation section. The shutdown

pin also has an internal pull-up current; therefore, to turn the part on the shutdown pin can either be connected to AVIN or left open

VREF VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference

voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high impedance, there should be little current

drawn from VREF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A

ceramic capacitor in the range of 0.1 µF to 0.01 µF is recommended. This output remains active during the shutdown state and thermal

shutdown events for the suspend to RAM functionality.

VTT VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the

output precisely to VDDQ / 2. The LP2997 is designed to handle continuous currents of up to +/- 0.5A with excellent load regulation. If a

transient is expected to last above the maximum continuous current rating for a significant amount of time, then the bulk output capacitor

should be sized large enough to prevent an excessive voltage drop. If the LP2997 is to operate in elevated temperatures for long durations

care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal de-rating should always be used.

(Please refer to the Thermal Dissipation section) If the junction temperature exceeds the thermal shutdown point than VTT will tri-state until

the part returns below the temperature hysteresis trip-point

COMPONENT SELECTIONS

INPUT CAPACITOR

The LP2997 does not require a capacitor for input stability, but it is recommended for improved performance

during large load transients to prevent the input rail from dropping. The input capacitor should be located as

close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A

typical value recommended for AL electrolytic capacitors is 22 µF. Ceramic capacitors can also be used. A value

in the range of 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the

LP2997 is placed close to the bulk capacitance from the output of the 1.8V DC-DC converter. For the AVIN pin, a

small 0.1uF ceramic capacitor is sufficient to prevent excessive noise from coupling into the device.

Product Folder Links: LP2997

0 200 400 600 800 1000

TJA

AIRFLOW (Linear Feet per Minute)

SOP Board

JEDEC Board

150

160

140

170

180

100

110

120

130

LP2997

www.ti.com

SNVS295F –MAY 2004–REVISED APRIL 2013

OUTPUT CAPACITOR

The LP2997 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance).

This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely

on the application and the requirements for load transient response of VTT. As a general recommendation the

output capacitor should be sized above 100 µF with a low ESR for SSTL applications with DDR-SDRAM. The

value of ESR should be determined by the maximum current spikes expected and the extent at which the output

voltage is allowed to droop. Several capacitor options are available on the market and a few of these are

highlighted below:

AL - It should be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which

indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance

specified at a higher frequency (100 kHz) should be used for the LP2997. To improve the ESR several AL

electrolytics can be combined in parallel for an overall reduction. An important note to be aware of is the extent

at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their ESR rapidly

increase at cold temperatures.

Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100 µF range, but they have

excellent AC performance for bypassing noise because of very low ESR (typically less than 10 mΩ). However,

some dielectric types do not have good capacitance characteristics as a function of voltage and temperature.

Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with

another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic

capacitors.

Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These

offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance

are critical, although their cost is typically higher than any other capacitors.

Thermal Dissipation

Since the LP2997 is a linear regulator any current flow from VTT will result in internal power dissipation

generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature,

care should be taken to derate the part dependent on the maximum expected ambient temperature and power

dissipation. The maximum allowable internal temperature rise (TRmax) can be calculated given the maximum

ambient temperature (TAmax) of the application and the maximum allowable junction temperature (TJmax).

TRmax = TJmax −TAmax (1)

From this equation, the maximum power dissipation (PDmax) of the part can be calculated:

PDmax = TRmax /θJA (2)

The θJA of the LP2997 will be dependent on several variables: the package used; the thickness of copper; the

number of vias and the airflow. For instance, the θJA of the SOIC-8 is 163°C/W with the package mounted to a

standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value

can be reduced to 151.2°C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard.

Figure 13 shows how the θJA varies with airflow for the two boards mentioned.

Figure 13. θJA vs Airflow (SOIC-8)

Product Folder Links: LP2997

VTT

LP2997

PVIN

VDD

VREF

AVIN

VREF =0.9V

VSENSE

GND

AVIN = 2.5V

VTT =0.9V

VDD

Q = 1.8V

7P F

0.01 PF

0 F

LP2997

SNVS295F –MAY 2004–REVISED APRIL 2013

www.ti.com

Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an

internal ground plane. Using larger traces and more copper on the top side of the board can also help. With

careful layout it is possible to reduce the θJA further than the nominal values shown in Figure 13.

Optimizing the θJA and placing the LP2997 in a section of a board exposed to lower ambient temperature allows

the part to operate with higher power dissipation. The internal power dissipation can be calculated by summing

the three main sources of loss: output current at VTT, either sinking or sourcing, and quiescent current at AVIN

and VDDQ. During the active state (when shutdown is not held low) the total internal power dissipation can be

calculated from the following equations:

PD= PAVIN + PVDDQ + PVTT (3)

Where,

PAVIN = IAVIN * VAVIN (4)

PVDDQ = VVDDQ * IVDDQ = VVDDQ2x RVDDQ (5)

To calculate the maximum power dissipation at VTT both conditions at VTT need to be examined, sinking and

sourcing current. Although only one equation will add into the total, VTT cannot source and sink current

simultaneously.

PVTT = VVTT x ILOAD (Sinking) or (6)

PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing) (7)

The power dissipation of the LP2997 can also be calculated during the shutdown state. During this condition the

output VTT will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any

current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at AVIN

and the constant impedance that is seen at the VDDQ pin.

PD= PAVIN + PVDDQ (8)

PAVIN = IAVIN x VAVIN (9)

PVDDQ = VVDDQ * IVDDQ = VVDDQ2x RVDDQ (10)

Typical Application Circuits

Several different application circuits have been shown to illustrate some of the options that are possible in

configuring the LP2997. Graphs of the individual circuit performance can be found in the Typical Performance

Characteristics section in the beginning of the datasheet. These curves illustrate how the maximum output

current is affected by changes in AVIN and PVIN.

Figure 14 shows the recommended circuit configuration for DDR-II applications. The output stage is connected to

the 1.8V rail and the AVIN pin can be connected to either a 2.5V, 3.3V or 5V rail.

This circuit permits termination in a minimum amount of board space and component count. Capacitor selection

can be varied depending on the number of lines terminated and the maximum load transient. However, with

motherboards and other applications where VTT is distributed across a long plane it is advisable to use multiple

bulk capacitors and addition to high frequency decoupling. The bulk output capacitors should be situated at both

ends of the VTT plane for optimal placement. Large aluminum electrolytic capacitors are used for their low ESR

and low cost.

Figure 14. Recommended DDR-II Termination

Product Folder Links: LP2997

LP2997

www.ti.com

SNVS295F –MAY 2004–REVISED APRIL 2013

PCB Layout Considerations

1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.

2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For

motherboard applications an ideal location would be at the center of the termination bus.

3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the

most accurate point for creating the reference voltage.

4. For improved thermal performance excessive top side copper should be used to dissipate heat from the

package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these

can be located underneath the package if manufacturing standards permit.

5. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A

0.1uF ceramic capacitor located close to the SENSE can also be used to filter any unwanted high frequency

signal. This can be an issue especially if long SENSE traces are used.

6. VREF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This

capacitor should be located as close as possible to the VREF pin.

Product Folder Links: LP2997

LP2997

SNVS295F –MAY 2004–REVISED APRIL 2013

www.ti.com

REVISION HISTORY

Changes from Revision E (April 2013) to Revision F Page

• Changed layout of National Data Sheet to TI format ............................................................................................................ 9

Product Folder Links: LP2997

PACKAGE OPTION ADDENDUM

www.ti.com 23-Aug-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LP2997M NRND SOIC D 8 95 TBD Call TI Call TI 0 to 125 L2997

LP2997M/NOPB ACTIVE SOIC D 8 95 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 125 L2997

LP2997MR NRND SO PowerPAD DDA 8 95 TBD Call TI Call TI 0 to 125 L2997

LP2997MR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR 0 to 125 L2997

LP2997MRX NRND SO PowerPAD DDA 8 TBD Call TI Call TI 0 to 125 L2997

LP2997MRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS

& no Sb/Br) CU SN Level-3-260C-168 HR 0 to 125 L2997

LP2997MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 125 L2997

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

PACKAGE OPTION ADDENDUM

www.ti.com 23-Aug-2017

Addendum-Page 2

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP2997MRX/NOPB SO

Power

PAD

DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LP2997MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP2997MRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0

LP2997MX/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2017

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

TYP

6.2

5.8

1.7 MAX

6X 1.27

8X 0.51

0.31

3.81

TYP

0.25

0.10

0 - 8

0.15

0.00

2.34

2.24

2.34

2.24

0.25

GAGE PLANE

1.27

0.40

NOTE 3

5.0

4.8

B4.0

3.8

4218825/A 05/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008A

PLASTIC SMALL OUTLINE

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MS-012.

PowerPAD is a trademark of Texas Instruments.

0.25 C A B

PIN 1 ID

AREA

NOTE 4

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.400

EXPOSED

THERMAL PAD

www.ti.com

EXAMPLE BOARD LAYOUT

(5.4)

(1.3) TYP

( ) TYP

VIA

0.2

(R ) TYP0.05

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

8X (1.55)

8X (0.6)

6X (1.27)

(2.95)

NOTE 9

(4.9)

NOTE 9

(2.34)

SOLDER MASK

OPENING

(1.3)

TYP

4218825/A 05/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008A

PLASTIC SMALL OUTLINE

SYMM

SEE DETAILS

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

METAL COVERED

BY SOLDER MASK

SOLDER MASK

DEFINED PAD

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(R ) TYP0.05

8X (1.55)

8X (0.6)

6X (1.27)

(5.4)

(2.34)

BASED ON

0.125 THICK

STENCIL

4218825/A 05/2016

PowerPAD SOIC - 1.7 mm max heightDDA0008A

PLASTIC SMALL OUTLINE

1.98 X 1.980.175

2.14 X 2.140.150

2.34 X 2.34 (SHOWN)0.125

2.62 X 2.620.1

SOLDER STENCIL

OPENING

STENCIL

THICKNESS

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

SYMM

BASED ON

0.125 THICK

STENCIL

BY SOLDER MASK

METAL COVERED SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its

semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers

should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated

circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and

services.

Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is

accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced

documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements

different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the

associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers

remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have

full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products

used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with

respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous

consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and

take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will

thoroughly test such applications and the functionality of such TI products as used in such applications.

TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,

including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to

assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any

way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource

solely for this purpose and subject to the terms of this Notice.

TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI

products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,

enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically

described in the published documentation for a particular TI Resource.

Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that

include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE

TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY

RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or

endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR

REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO

ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL

PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,

INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF

PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,

DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN

CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN

ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949

and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.

Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such

products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards

and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must

ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in

life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.

Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life

support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all

medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.

TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).

Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications

and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory

requirements in connection with such selection.

Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-

compliance with the terms and provisions of this Notice.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

LP2997M LP2997M/NOPB LP2997MR LP2997MR/NOPB LP2997MRX LP2997MRX/NOPB LP2997MX

LP2997MX/NOPB