8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
1
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
GENERAL DESCRIPTION
The ICS8516 is a low skew, high performance
1-to-16 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8516 CLK, nCLK pair can accept
any differential input levels and translates them to 3.3V LVDS
output levels. Utilizing Low Voltage Differential Signaling
(LVDS), the ICS8516 provides a low power, low noise, point-
to-point solution for distributing clock signals over controlled
impedances of 100Ω.
Dual output enable inputs allow the ICS8516 to be used in a
1-to-16 or 1-to-8 input/output mode.
Guaranteed output and part-to-part skew specifications make
the ICS8516 ideal for those applications demanding well
defined performance and repeatability.
BLOCK DIAGRAM PIN ASSIGNMENT
FEATURES
•Sixteen differential LVDS outputs
•CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•Maximum output frequency: 700MHz
•Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
•Translates any single-ended input signal to LVDS
with resistor bias on nCLK input
•Multiple output enable inputs for disabling unused
outputs in reduced fanout applications
•LVDS compatible
•Output skew: 90ps (maximum)
•Part-to-part skew: 500ps (maximum)
• Propagation delay: 2.4ns (maximum)
• Additive phase jitter, RMS: 148fs (typical)
•3.3V operating supply
•0°C to 70°C ambient operating temperature
•Available in both standard and lead-free RoHS compliant
packages
HiPerClockS™
ICS
48-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
OE1
OE2
CLK
nCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
VDD
nQ5
Q5
nQ4
Q4
VDD
GND
nQ3
Q3
nQ2
Q2
VDD
VDD
nQ10
Q10
nQ11
Q11
VDD
GND
nQ12
Q12
nQ13
Q13
VDD
nQ14
Q14
nQ15
Q15
GND
CLK
nCLK
GND
Q0
nQ0
Q1
nQ1
ICS8516
Q9
nQ9
Q8
nQ8
GND
OE2
OE1
GND
nQ7
Q7
nQ6
Q6
DATA SHEET
ICS8516
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
1
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK
DISTRIBUTION CHIP
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
2
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
,21,6,1
63,13,52 V
DD
rewoP.snipylppusevitisoP
3,25Q,5QntuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
5,44Q,4QntuptuO.slevelecaf
retniSDVL.riaptuptuolaitnereffiD
,02,71,7
44,14,03 DNGrewoP.dnuorgylppusrewoP
9,83Q,3QntuptuO.slevelecafretniS
DVL.riaptuptuolaitnereffiD
11,012Q,2QntuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
41,311Q,1QntuptuO.sle
velecafretniSDVL.riaptuptuolaitnereffiD
61,510Q,0QntuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
81KLCnt
upnIpulluP.tupnikcolclaitnereffidgnitrevnI
91KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
22,1251Qn,51
QtuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
42,3241Qn,41QtuptuO.slevelecafretniSDVL.riaptuptuolaitne
reffiD
72,6231Qn,31QtuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
92,8221Qn,21QtuptuO.slevelecafretniSDVL
.riaptuptuolaitnereffiD
33,2311Qn,11QtuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
53,4301Qn,01QtuptuO.sl
evelecafretniSDVL.riaptuptuolaitnereffiD
83,739Qn,9QtuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
04,9
38Qn,8QtuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
34,241EO,2EOtupnIpulluP
;51Qn,51Qurht8Qn,8Qstuptuosl
ortnoc2EO.elbanetuptuO
.7Qn,7Qurht0Qn,0Qstuptuoslortnoc1EO
.slevelecafretniLTTVL/SOMCVL
64,547Q,7QntuptuO.s
levelecafretniSDVL.riaptuptuolaitnereffiD
84,746Q,6QntuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
:ET
ON pulluP dna nwodlluP .seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
2
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
3
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 2. PIN CHARACTERISTICS
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
1EO2EO7Q:0Q7Qn:0Qn51Q:8Q51Qn:8Qn
00 ZiHZiHZiHZiH
10 EVITCAEVITCAZiHZiH
01 ZiHZiHEVITCAEVITCA
11 EVITCAEVITCAEVITCAEVITCA
.B
3elbaTnidebircsedsastupniKLCndnaKLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
stupnIstuptuO edoMtuptuOottupnIytiraloP
KLCKLCn51Q:0Q51Qn:0Qn
01WOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN
10 HGIHWO
LlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN
11ETON;desaiBH
GIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN
1ETON;desaiB0HGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
1ETON;desaiB1W
OLHGIHlaitnereffiDotdednEelgniSgnitrevnI
."sleveLdednEelgniStpeccAottupnIlaitnereffiDehtgniriW",noitcesno
itamrofnInoitacilppAehtotreferesaelP:1ETON
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
C
DP
ecnaticapaCnoitapissiDrewoP
)tuptuorep( 4Fp
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
3
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
4
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP 531.33.3564.3V
I
DD
tnerruCylppuSrewoPcitatS R
L
001= Ω531561Am
daoLoN0657Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCV
NI
V=
DD
V564.3=051Aµ
KLCnV
NI
V=
DD
V564.3=5Aµ
I
LI
tnerruCwoLtupnI KLCV
DD
V,V564.3=
NI
V0=5-Aµ
KLCnV
DD
V,V564.3=
NI
V0=051-Aµ
V
PP
egatloVkaeP-ot-kaeP 51.03.1V
V
RMC
;egatloVtupnIedoMnommoC
2,1ETON 5.0+DNGV
DD
58.0-V
VsiKLCn,KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:1ETON
DD
.V3.0+
tsadenifedsiegatlovedomnommoC:2ETONV
HI
.
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI2EO,1EO2V
DD
3.0+V
V
LI
egatloVwoLtupnI2EO,1EO3.0-8.0V
I
HI
tnerruChgiHtupnI2EO,1EOV
DD
V=
NI
V564.3=5Aµ
I
LI
tnerruCwoLtupnI2EO,1EOV
DD
V,V564.3=
NI
V0=051-Aµ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, VO-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
4
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
5
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DO
egatloVtuptuOlaitnereffiD 052004006Vm
ΔV
DO
V
DO
egnahCedutingaM 05Vm
V
SO
egatloVtesffO 521.14.16.1V
ΔV
SO
V
SO
egnahCedutingaM 05Vm
I
ZO
tnerruCegakaeLecnadepmIhgiH 01-01+Aµ
I
FFO
egakaeLffOrewoP 1-1+Aµ
I
DSO
tnerruCtiucriCtrohStuptuOlaitnereffiD 5.5-Am
I
SO
I/
BSO
tnerruCtiucriCtrohStuptuO 21-Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
f
XAM
ycneuqerFtuptuO 007zHM
t
DP
1ETON;yaleDnoitagaporP 6.10.24.2sn
t)o(ks4,2ETON;wekStuptuO 09sp
t)pp(ks4,3ETON;wekStraP-ot-traP 005sp
ttij ;SMR,re
ttiJesahPevitiddAreffuB
noitceSrettiJesahPevitiddAotrefer
:egnaRnoitargetnI
zHM02-zHk21 841sf
t
R
t/
F
emiTllaF/esiRtuptuO%08ot%02001055sp
cdoelcyCytuDtuptuO 540555%
t
LZP
t,
HZP
5ETON;emiTelbanEtuptuO 5sn
t
ZLP
t,
ZHP
5ETON;emiTelbasiDtuptuO 5sn
.tniopgnissorctuptuolaitnereffidehtottniopgnissorctupnilaitnereffidehtmorfde
rusaeM:1ETON
.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
.stnio
pssorclaitnereffidtuptuoehttaderusaeM
segatlovylppusemasehttagnitareposecivedtnereffidnostuptuoneewteb
wekssadenifeD:3ETON
derusaemerastuptuoeht,ecivedhcaenostupnifoepytemasehtgnisU.snoitidnocdaollauqehtiw
dna
.stniopssorclaitnereffidehtta
.56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:5ETON
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
5
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
6
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
ADDITIVE PHASE JITTER
Additive Phase Jitter @ 155.52MHz
(12kHz to 20MHz)
= 148fs typical
-50
-60
-70
-80
-90
-100
-100
-120
-130
-140
-150
-160
1k 10k 100k 1M 10M 100M
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the dBc Phase Noise. This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
ratio of the power in the 1Hz band to the power in the funda-
mental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the fre-
quency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
6
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
7
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
PARAMETER MEASUREMENT INFORMATION
PART-TO-PART SKEW
PROPAGATION DELAY OUTPUT RISE/FALL TIME
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
OD
t
sk(o)
nQx
nQ
nQy
Qy
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVDS
Power Supply
+-
Float GND
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
VDD
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
nCLK
CLK
nQ0:nQ15
Q0:Q15
t
PD
3.3V ± 5%
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
7
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
8
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OFFSET VOLTAGE SETUP
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
nQ0:nQ15
Q0:Q15
POWER OFF LEAKAGE SETUP
DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP
OUTPUT SHORT CIRCUIT CURRENT SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
out
out
LVDS
DC Input
➤
➤
➤
V
OS
/Δ V
OS
V
DD
➤
➤
➤
100
out
out
LVDS
DC Input V
OD
/Δ V
OD
V
DD
out
out
LVD S
DC Input
➤
I
OSD
V
DD
out
LVD S
DC Input
➤
IOS
➤
IOSB
VDD
out
LVD S
➤
I
OFF
V
DD
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
8
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
9
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VDD
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVDS – Like OUTPUT
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
9
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
10
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 2A to 2E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 2A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
10
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
11
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
LVDS DRIVER T ERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers re-
quire a matched load termination of 100Ω across near the
receiver input. For a multiple LVDS outputs buffer, if only par-
tial outputs are used, it is recommended to terminate the un-
used outputs.
FIGURE 3. TYPICAL LVDS DRIVER T ERMINATION
3.3V
R1
100
Zo = 50 Ohm
LVDS_Driver
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
3.3V
FIGURE 4. ICS8516 LVDS BUFFER SCHEMATIC EXAMPLE
C5
0.1u
(U1-12)
Zo = 50 Ohm
Zo = 50 Ohm
(U1-25)
LVDS_input
+
-
(U1-31)
Zo = 50 Ohm
C3
0.1u
C6
0.1u
U1
8516
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
VDD
nQ5
Q5
nQ4
Q4
VDD
GND
nQ3
Q3
nQ2
Q2
VDD
nQ1
Q1
nQ0
Q0
GND
nCLK
CLK
GND
Q15
nQ15
Q14
nQ14
VDD
nQ10
Q10
nQ11
Q11
VDD
GND
nQ12
Q12
nQ13
Q13
VDD
Q6
nQ6
Q7
nQ7
GND
OE1
OE2
GND
nQ8
Q8
nQ9
Q9
Zo = 50 Ohm
R16
100
Zo = 50 Ohm
VDD=3.3V
LVDS_input
+
-
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
VDD=3.3V
R10
100
C4
0.1u
C2
0.1u
LVDS_Driver
R17
100
LVDS_input
+
-
(U1-1)
Decoupling capacitors located near the power pins
(U1-6) (U1-36)
R1
100
C1
0.1u
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of ICS8516. In this ex-
ample, the input is driven by an LVDS driver. For LVDS buffer,
it is recommended to terminate the unused outputs for better
signal integrity. The decoupling capacitors should be physi-
cally located near the power pin.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
11
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
12
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8516 is: 1821
TABLE 6. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
12
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
13
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 7. PACKAGE DIMENSIONS
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
LOBMYS CBB
MUMINIMLANIMONMUMIXAM
N84
A----06.1
1A 50.0--51.0
2A 53.104.154.1
b71.022.072.0
c90.0--02.0
DCISAB00.9
1D CISAB00.7
2D .feR05.5
ECISAB00.9
1E CISAB00.7
2E .feR05.5
eCISAB05.0
L54.006.057.
0
θθ
θ
θθ 0
°
-- 7
°
ccc ----80.0
Reference Document: JEDEC Publication 95, MS-026
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
13
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
14
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
YF6158SCIYF6158SCIPFQLdaeL84yartC°07otC°0
TYF6158SCIY
F6158SCIPFQLdaeL84leer&epat0001C°07otC°0
FLYF6158SCIFLYF6158SCIPFQL"eerF-daeL"daeL84yartC°07otC°0
TFLYF6158SCIF
LYF6158SCIPFQL"eerF-daeL"daeL84leer&epat0001C°07otC°0
.tnailpmocSHoReradnanoitarugifnoceerF-bPehterarebmu
ntrapehtotxiffus"FL"nahtiwderedroeratahtstraP:ETON
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
14
8516FY www.icst.com/products/hiperclocks.html REV. B FEBRUARY 21, 2006
15
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
TEEHSYROTSIHNOISIVER
veRelbaTegaPegnahCfonoitpircseDetaD
A1T2
8
.84urht74snipdedda-elbatnoitpircseDniP
.noitces
noitamrofnInoitacilppAehtninoitanimreTrevirDSDVLdeddA 30/13/3
A1T2 84,74&64,54rofsemannipdehctiws-elbaTnoit
pircseDniP 30/6/5
A
2T
8T
3
9
21
Cdegnahc-elbaTscitsiretcarahCniP
NI
.lacipytFp4ot.xamFp4morf
.noitcesecafretnItupnIkcolClaitnereffiDdetadpU
.srebmuntrapeerF-daeLdedda-elba
TnoitamrofnIgniredrO
40/03/7
B5T
1
5
6
9
.tellubrettiJesahPevitiddAdedda-noitceSerutaeF
.rettiJesahPevitiddAd
edda-elbaTscitsiretcarahCCA
.noitcesrettiJesahPevitiddAdeddA
deddA sniPtuptuOdnatupnIdesunUrofsnoitadnem
moceR
60/12/2
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD
IDT™ / ICS™ LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP ICS8516
15
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
XX-XXXX-XXXXX
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
clockhelp@idt.com
408-284-8200
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
ICS280
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER TSD
MK1491-14
OPTi ACPI Firestar Clock Source TSD
ICS1890
Auto-Negotiation Advertisement Register (register 4 [0x04]) TSD
ICS1527
Video Clock Synthesizer TSD
ICS8302-01
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT TSD
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP TSD