DS05-11052-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
4 × 512 K × 32 BIT
SYNCHRONOUS DYNAMIC RAM
MB811L643242B-10/-12/-15/-10L/-12L/-15L
CMOS 4-Bank × 524,288-Word × 32 Bit
Synchronous Dynamic Random Access Memory
■DESCRIPTION
The Fujitsu MB811L643242B is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing
67,108,864 memory cells accessible in a 32-bit format. The MB811L643242B features a fully synchronous
operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which
enables high perf ormance and simple user interface coe xistence . The MB811L643242B SDRAM is designed to
reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing
constraints, and may improve data bandwidth of memory as much as 5 times more than a standard DRAM.
The MB811L643242B is ideally suited for workstations, personal computers, laser printers, high resolution graphic
adapters/accelerators and other applications where an e xtremely large memory and bandwidth are required and
where a simple interface is needed.
■PRODUCT LINE & FEATURES
Parameter MB811L643242B
-10/-10L -12/-12L -15/-15L
CL - tRCD - tRP CL = 2 2 - 2 - 2 clk min. 2 - 2 - 2 clk min. 2 - 2 - 2 clk min.
CL = 3 3 - 3 - 3 clk min. 3 - 3 - 3 clk min. 3 - 3 - 3 clk min.
Clock Frequency 100 MHz max. 84 MHz max. 67 MHz max.
Burst Mode Cycle Time CL = 2 15 ns min. 17 ns min. 20ns min.
CL = 3 10 ns min. 12 ns min. 15 ns min.
Access Time from Clock CL = 2 8 ns max. 8 ns max. 8 ns max.
CL = 3 8 ns max. 8 ns max. 8 ns max.
Operating Current 130 mA max. 120 mA max. 110 mA max.
Power Down Mode Current (ICC2P) 2 mA max.(std version) / 1.5 mA max.(L version)
Self Refresh Current (ICC6) 2 mA max.(std. version) / 0.5 mA max.(L version)
• Single +2.5 V Supply ±0.2 V tolerance
• LVTTL compatible I/O interface
• 4 K refresh cycles every 64 ms
• Four bank operation
• Burst read/write operation and burst
read/single write operation capability
• Programmable burst type, burst length, and
CAS latency
• Auto-and Self-refresh (every 15.6 µs)
• CKE power down mode
• Output Enable and Input Data Mask
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2
MB811L643242B-10/-12/-15/-10L/-12L/-15L
■PACKAGE
Package and Ordering Information
– 86-pin plastic (400 mil) TSOP-II, order as MB811L643242B-×××FN (standard-version) or
MB811L643242B-×××LFN (L-version)
(FPT-86P-M01)
86-pin plastic TSOP(II)
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3
MB811L643242B-10/-12/-15/-10L/-12L/-15L
■PIN ASSIGNMENTS AND DESCRIPTIONS
86-Pin TSOP(II)
(TOP VIEW)
<Normal Bend: FPT-86P-M01>
74
73
72
71
70
69
68
67
66
86
85
84
83
82
81
80
79
78
77
1
2
3
4
5
9
10
6
7
8
13
14
15
16
17
18
19
20
21
22
76
75
11
12
65
64
63
62
61
60
23
24
25
26
27
58
57
56
55
54
53
52
51
50
29
30
31
32
33
34
35
36
37
38
59
28
49
48
47
46
45
44
39
40
41
42
43
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
N.C.
VDD
DQM0
WE
CAS
RAS
CS
N.C.
A12
A11
A10/AP
A0
A1
A2
DQM2
VDD
N.C.
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
N.C.
VSS
DQM1
N.C.
N.C.
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
N.C.
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
Pin Number Symbol Function
1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81 VDD, VDDQ Supply Voltage
2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36,
37, 39, 40, 42, 45, 47, 48, 50, 51, 53,
54, 56, 74, 76, 77, 79, 80, 82, 83, 85 DQ0 to DQ31 Data I/O
6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84,
86 VSS, VSSQ Ground
14, 21, 30, 57, 69, 70, 73 N.C. No Connection
17 WE Write Enable
18 CAS Column Address Strobe
19 RAS Row Address Strobe
20 CS Chip Select
22, 23 A11 (BA1), A12 (BA0) Bank Select (Bank Address)
24 AP Auto Precharge Enable
24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 A0 to A10 Address Input • Row: A0 to A10
• Column: A0 to A7
67 CKE Clock Enable
68 CLK Clock Input
16, 28, 59, 71 DQM0 to DQM3Input Mask/Output Enable
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MB811L643242B-10/-12/-15/-10L/-12L/-15L
■BLOCK DIAGRAM
Fig. 1 – MB811L643242B BLOCK DIAGRAM
BANK-1
VDD
VSS/VSSQ
CLK
CKE
A0 to A10,
A10/AP
DQ0
to
DQ31
COMMAND
DECODER
CLOCK
BUFFER
ADDRESS
BUFFER/
REGISTER
I/O DATA
BUFFER/
REGISTER
MODE
REGISTER
RAS
CAS
WE
DRAM
CORE
(2,048 × 256 × 32)
COL.
ADDR.
RAS
CAS
WE
CS
BANK-0
I/O
ROW
ADDR.
To each block
CONTROL
SIGNAL
LATCH
VDDQ
BANK-2
BANK-3
A11 (BA1)
A12 (BA0)
COLUMN
ADDRESS
COUNTER
DQM0
to
DQM3
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5
MB811L643242B-10/-12/-15/-10L/-12L/-15L
■FUNCTIONAL TRUTH TABLE Note 1
COMMAND TRUTH TABLE Note 2, 3, and 4
Notes: *1. V = Valid, L = Logic Low, H = Logic High, X = either L or H.
*2. All commands assumes no CSUS command on previous rising edge of clock.
*3. All commands are assumed to be valid state transitions.
*4. All inputs are latched on the rising edge of clock.
*5. NOP and DESL commands have the same effect on the part.
*6. READ , READ A, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to STATE DIAGRAM.
*7. A CTV command should only be issued after corresponding bank has been precharged (PRE or PALL
command).
*8. Required after power up.
*9. MRS command should only be issued after all banks have been precharged (PRE or PALL command).
Refer to STATE DIAGRAM.
Function Notes Symbol CKE CS RAS CAS WE A12,
A11
(BA) A10
(AP) A9
to
A8
A7
to
A0
n-1 n
Device Deselect *5 DESL H X H X X X X X X X
No Operation *5 NOP H X L H H H X X X X
Burst Stop BST H X L H H L X X X X
Read *6READHXLHLHVLXV
Read with Auto-precharge *6 READA H X L H L H V H X V
Write *6 WRIT H X L H L L V L X V
Write with Auto-precharge *6 WRITA H X L H L L V H X V
Bank Active *7 ACTV H X L L H H V V V V
Precharge Single Bank PRE H X L L H L V L X X
Precharge All Banks PALL H X L L H L X H X X
Mode Register Set *8, 9 MRS H X L L L L L L V V
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6
MB811L643242B-10/-12/-15/-10L/-12L/-15L
DQM TRUTH TABLE
Notes: *1. i = 0, 1, 2, 3
*2. DQM0 for DQ0 to DQ7, DQM1 for DQ8 to DQ15, DQM2 for DQ16 to DQ23, DQM3 for DQ24 to DQ31,
CKE TRUTH TABLE
Notes: *1. The CSUS command requires that at least one bank is active. Refer to STATE DIAGRAM.
*2. REF and SELF commands should only be issued after all banks hav e been precharged (PRE or PALL
command). Refer to STATE DIAGRAM.
*3. SELF and PD commands should only be issued after the last read data have been appeared on DQ.
*4. NOP or DSEL commands should only be issued after CSUS and PRE(or PALL) commands asserted
at the same time.
Function Symbol CKE DQMi
n-1 n
Data Write/Output Enable ENBi H X L
Data Mask/Output Disable MASKi H X H
Current
State Function Notes Symbol CKE CS RAS CAS WE A12,
A11
(BA) A10
(AP) A9
to
A0
n-1 n
Bank Active Clock Suspend Mode Entry*1, 4 CSUS H L X X X X X X X
Any
(Except Idle) Clock Suspend Continue *1 L L X X X X X X X
Clock
Suspend Clock Suspend Mode Exit L H X X X X X X X
Idle Auto-refresh Command *2 REF H H L L L H X X X
Idle Self-refresh Entry *2, 3 SELF H L L L L H X X X
Self Refresh Self-refresh Exit SELFX LHL H H H X X X
LHH X X X X X X
Idle Power Down Entry *3 PD HLL H H H X X X
HLH X X X X X X
Power Do wn Power Do wn Exit LHL H H H X X X
LHH X X X X X X
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7
MB811L643242B-10/-12/-15/-10L/-12L/-15L
OPERATION COMMAND TABLE (Applicable to single bank)
(Continued)
Current
State CS RAS CAS WE Addr Command Function Notes
Idle HXXX X DESL NOP
LHHH X NOP NOP
L H H L X BST NOP
L H L H BA, CA, AP READ/READA Illegal *2
L H L L BA, CA, AP WRIT/WRITA Illegal *2
L L H H BA, RA ACTV Bank Active after tRCD
L L H L BA, AP PRE/PALL NOP *6
L L L H X REF/SELF Auto-refresh or Self-refresh *3
LLLL MODE MRS Mode Register Set
(Idle after tRSC)*3, 7
Bank Active H X X X X DESL NOP
LHHH X NOP NOP
L H H L X BST NOP
L H L H BA, CA, AP READ/READA Begin Read; Determine AP
L H L L BA, CA, AP WRIT/WRITA Begin Write; Determine AP
L L H H BA, RA ACTV Illegal *2
L L H L BA, AP PRE/PALL Precharge; Determine Precharge Type
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal
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8
MB811L643242B-10/-12/-15/-10L/-12L/-15L
(Continued)
Current
State CS RAS CAS WE Addr Command Function Notes
Read HXXX X DESL NOP (Continue Burst to End → Bank
Active)
LHHH X NOP NOP (Continue Burst to End → Bank
Active)
L H H L X BST Burst Stop → Bank Active
L H L H BA, CA, AP READ/READA Terminate Burst, New Read;
Determine AP
L H L L BA, CA, AP WRIT/WRITA Terminate Burst, Start Write;
Determine AP *4
L L H H BA, RA ACTV Illegal *2
L L H L BA, AP PRE/PALL Terminate Burst, Precharge → Idle;
Determine Precharge Type
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal
Write HXXX X DESL NOP (Continue Burst to End →
Bank Active)
LHHH X NOP NOP (Continue Burst to End →
Bank Active)
L H H L X BST Burst Stop → Bank Active
L H L H BA, CA, AP READ/READA Terminate Burst, Start Read;
Determine AP *4
L H L L BA, CA, AP WRIT/WRITA Terminate Burst, New Write;
Determine AP
L L H H BA, RA ACTV Illegal *2
L L H L BA, AP PRE/PALL Terminate Burst, Precharge;
Determine Precharge Type
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal
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9
MB811L643242B-10/-12/-15/-10L/-12L/-15L
(Continued)
Current
State CS RAS CAS WE Addr Command Function Notes
Read with
Auto-
precharge HXXX X DESL NOP (Continue Burst to End →
Precharge → Idle)
LHHH X NOP NOP (Continue Burst to End →
Precharge → Idle)
L H H L X BST Illegal
L H L H BA, CA, AP READ/READA Illegal *2
L H L L BA, CA, AP WRIT/WRITA Illegal *2
L L H H BA, RA ACTV Illegal *2
L L H L BA, AP PRE/PALL Illegal *2
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal
Write with
Auto-
precharge HXXX X DESL NOP (Continue Burst to End →
Precharge → Idle)
LHHH X NOP NOP (Continue Burst to End →
Precharge → Idle)
L H H L X BST Illegal
L H L H BA, CA, AP READ/READA Illegal *2
L H L L BA, CA, AP WRIT/WRITA Illegal *2
L L H H BA, RA ACTV Illegal *2
L L H L BA, AP PRE/PALL Illegal *2
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal
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MB811L643242B-10/-12/-15/-10L/-12L/-15L
(Continued)
Current
State CS RAS CAS WE Addr Command Function Notes
Pre-
charging H X X X X DESL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L X BST NOP (Idle after tRP)
L H L H BA, CA, AP READ/READA Illegal *2
L H L L BA, CA, AP WRIT/WRITA Illegal *2
L L H H BA, RA ACTV Illegal *2
L L H L BA, AP PRE/PALL NOP (PALL may affect other
bank) *5
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal
Bank
Activating H X X X X DESL NOP (Bank Active after tRCD)
L H H H X NOP NOP (Bank Active after tRCD)
L H H L X BST NOP (Bank Active after tRCD)
L H L H BA, CA, AP READ/READA Illegal *2
L H L L BA, CA, AP WRIT/WRITA Illegal *2
L L H H BA, RA ACTV Illegal *2
L L H L BA, AP PRE/PALL Illegal *2
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal
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MB811L643242B-10/-12/-15/-10L/-12L/-15L
(Continued)
ABBREVIATIONS:
RA = Row Address BA = Bank Address
CA = Column Address AP = Auto Precharge
Current
State CS RAS CAS WE Addr Command Function Notes
Refreshing H X X X X DESL NOP (Idle after tRC)
L H H X X NOP/BST NOP (Idle after tRC)
LHLX X READ/READA/
WRIT/WRITA Illegal
LLHX X ACTV/
PRE/PALL Illegal
LLLX X REF/SELF/
MRS Illegal
Mode
Register
Setting
H X X X X DESL NOP (Idle after tRSC)
L H H H X NOP NOP (Idle after tRSC)
L H H L X BST Illegal
LHLX X READ/READA/
WRIT/WRITA Illegal
LLXX X ACTV/PRE/
PALL/REF/
SELF/MRS Illegal
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MB811L643242B-10/-12/-15/-10L/-12L/-15L
COMMAND TRUTH TABLE FOR CKE
(Continued)
Current
State CKE
n-1 CKE
nCS RAS CAS WE Addr Function Notes
Self-
refresh HXXXXX X Invalid
LHHXXX X Exit Self-refresh
(Self-refresh Recovery → Idle after tRC)
LHLHHH X Exit Self-refresh
(Self-refresh Recovery → Idle after tRC)
LHLHHL X Illegal
LHLHLX X Illegal
L H L L X X X Illegal
L L X X X X X NOP (Maintain Self-refresh)
Self-
refresh
Recovery
LXXXXX X Invalid
H H H X X X X Idle after tRC
H H L H H H X Idle after tRC
H H L H H L X Illegal
H H L H L X X Illegal
H H L L X X X Illegal
HHXXXX X Illegal
HLXXXX X Illegal
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13
MB811L643242B-10/-12/-15/-10L/-12L/-15L
(Continued)
Current
State CKE
n-1 CKE
nCS RAS CAS WE Addr Function Notes
Power
Down HXXXXX X Invalid
LHHXXX X Exit Power Down Mode → Idle
LHLHHH X
L L X X X X X NOP (Maintain Power Down Mode)
L H L L X X X Illegal
LHLHLX X Illegal
All
Banks
Idle
H H H X X X MODE Refer to the Operation Command Table.
H H L H X X MODE Refer to the Operation Command Table.
H H L L H X MODE Refer to the Operation Command Table.
H H L L L H X Auto-refresh
H H L L L L MODE Refer to the Operation Command Table.
H L H X X X X Power Down
H L L H H H X Power Down
HLLHHL X Illegal
H L L H L X X Illegal
H L L L H X X Illegal
HLLLLH X Self-refresh
HLLLLL X Illegal
LXXXXX X Invalid
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14
MB811L643242B-10/-12/-15/-10L/-12L/-15L
(Continued)
Notes: *1. All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle.
Illegal means don’t used command. If used, power up sequence be asserted after power shut down.
*2. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state
of that bank.
*3. Illegal if any bank is not idle.
*4. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Refer to TIMING DIAGRAM -11 & -12.
*5. NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP).
*6. SELF command should only be issued after the last read data have been appeared on DQ.
*7. MRS command should only be issued on condition that all DQ are in Hi-Z.
Current
State CKE
n-1 CKE
nCS RAS CAS WE Addr Function Notes
Bank Active
Bank
Activating
Read/Write
H H X X X X X Refer to the Operation Command Table.
H L X X X X X Begin Clock Suspend next cycle
LXXXXX X Invalid
Clock
Suspend HXXXXX X Invalid
L H X X X X X Exit Clock Suspend next cycle
L L X X X X X Maintain Clock Suspend
Any State
Other Than
Listed
Above
LXXXXX X Invalid
H H X X X X X Refer to the Operation Command Table.
HLXXXX X Illegal
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15
MB811L643242B-10/-12/-15/-10L/-12L/-15L
■FUNCTIONAL DESCRIPTION
SDRAM BASIC FUNCTION
Three major diff erences between this SDRAM and con ventional DRAMs are: synchroniz ed operation, b urst mode,
and mode register.
The synchronized operation is the fundamental difference. An SDRAM uses a clock input for the synchronization,
where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each
operation of DRAM is determined by their timing phase diff erences while each operation of SDRAM is determined
by commands and all operations are referenced to a positive clock edge. Fig. 2 shows the basic timing diagram
differences between SDRAMs and DRAMs.
The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column
addresses for the first access is set, following addresses are automatically generated by the internal column address
counter.
The mode register is to justify the SDRAM operation and function into desired system conditions. MODE REGISTER
TABLE shows how SDRAM can be configured for system requirement by mode register programming.
CLOCK (CLK) and CLOCK ENABLE (CKE)
All input and output signals of SDRAM use register type buffers. A CLK is used as a trigger for the register and
internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the
CLK. CKE is a high activ e clock enab le signal. When CKE = Low is latched at a cloc k input during activ e cycle, the
next clock will be internally masked. During idle state (all banks have been precharged), the Power Down mode
(standby) is entered with CKE = Low and this will make extremely low standby current.
CHIP SELECT (CS)
CS enables all commands inputs , RAS, CAS , and WE, and address input. When CS is High, command signals are
negated but internal operation such as b urst cycle will not be suspended. If such a control isn’t needed, CS can be
tied to ground level.
COMMAND INPUT (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operation, such as Row address
strobe by RAS . Instead, each combination of RAS, CAS , and WE input in conjunction with CS input at a rising edge
of the CLK determines SDRAM operation. Refer to FUNCTIONAL TRUTH TABLE in page 5.
ADDRESS INPUT (A0 to A10)
Address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. A total of twenty
one address input signals are required to decode such a matrix. SDRAM adopts an address multiple xer in order to
reduce the pin count of the address line. At a Bank Active command (ACTV), eleven Row addresses are initially
latched and the remainder of eight Column addresses are then latched by a Column address strobe command of
either a Read command (READ or READA) or Write command (WRIT or WRITA).
BANK SELECT (A12, A11)
This SDRAM has four banks and each bank is organized as 512 K words by 32-bit.
Bank selection by A12, A11 occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT
or WRITA), and precharge command (PRE).
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MB811L643242B-10/-12/-15/-10L/-12L/-15L
DATA INPUT AND OUTPUT (DQ0 to DQ31)
Input data is latched and written into the memory at the clock following the write command input. Data output is
obtained by the following conditions followed by a read command input:
tRAC ; from the bank active command when tRCD (min) is satisfied. (This parameter is reference only.)
tCAC ; from the read command when tRCD is greater than tRCD (min). (This parameter is reference only.)
tAC ; from the clock edge after tRAC and tCAC.
The polarity of the output data is identical to that of the input. Data is valid between access time (determined by
the three conditions above) and the next positive clock edge (tOH).
DATA I/O MASK (DQM)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and when
DQM0 to DQM3 = High is latched by a clock, input is masked at the same clock and output will be masked at the
second clock later while internal burst counter will increment b y one or will go to the ne xt stage depending on burst
type. DQM0, DQM1, DQM2, DQM3, controls DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23, DQ24 to DQ31, respectively.
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address
and by automatic strobing column address. Access time and cycle time of Burst mode is specified as tAC and tCK,
respectiv ely. The internal column address counter operation is determined by a mode register which defines b urst
type and burst count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or to mov e from the current burst
mode to the ne xt stage while the remaining burst count is more than 1, the f ollowing combinations will be required:
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode
is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to
the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant
address (= 0). The interleave mode is a scrambled decoding scheme for A0 and A2. If the first access of column
address is even (0), the next address will be odd (1), or vice-versa.
(Continued)
Current Stage Next Stage Method (Assert the following command)
Burst Read Burst Read Read Command
Burst Read Burst Write 1st Step Mask Command (Normally 3 clock cycles)
2nd Step Write Command after lOWD
Burst Write Burst Write Write Command
Burst Write Burst Read Read Command
Burst Read Precharge Precharge Command
Burst Write Precharge Precharge Command
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17
MB811L643242B-10/-12/-15/-10L/-12L/-15L
(Continued)
When the full burst operation is executed at single write mode, Auto-precharge command is valid only at write
operation.
The burst type can be selected either sequential or interlea v e mode. But only the sequential mode is usab le to the
full column burst. The sequential mode is an incremental decoding scheme within a boundary address to be
determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary
address and then wraps round to least significant address (= 0).
FULL COLUMN BURST AND BURST STOP COMMAND (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full column
bu rst mode is repeatedly access to the same column. If burst mode reaches end of column address , then it wr aps
round to first column address (= 0) and continues to count until interrupted by the ne ws read (READ) /write (WRIT),
precharge (PRE), or burst stop (BST) command. The selection of Auto-precharge option is illegal during the full
column burst operation except write command at BURST READ & SINGLE WRITE mode.
The BST command is applicable to terminate the burst oper ation. If the BST command is asserted during the burst
mode, its operation is terminated immediately and the internal state moves to Bank Active.
When read mode is interrupted by BST command, the output will be in High-Z.
For the detail rule, please refer to TIMING DIAGRAM – 8.
When write mode is interrupted by BST command, the data to be applied at the same time with BST command will
be ignored.
BURST READ & SINGLE WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this
mode, burst read operation does not be affected by this mode.
Burst
Length Starting Column
Address
A2 A1 A0Sequential Mode Interleave
2X X 0 0 – 1 0 – 1
X X 1 1 – 0 1 – 0
4
X 0 0 0 – 1 – 2 – 3 0 – 1 – 2 – 3
X 0 1 1 – 2 – 3 – 0 1 – 0 – 3 – 2
X 1 0 2 – 3 – 0 – 1 2 – 3 – 0 – 1
X 1 1 3 – 0 – 1 – 2 3 – 2 – 1 – 0
8
0 0 0 0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 0 – 1 – 2 – 3 – 4 – 5 – 6 – 7
0 0 1 1 – 2 – 3 – 4 – 5 – 6 – 7 – 0 1 – 0 – 3 – 2 – 5 – 4 – 7 – 6
0 1 0 2 – 3 – 4 – 5 – 6 – 7 – 0 – 1 2 – 3 – 0 – 1 – 6 – 7 – 4 – 5
0 1 1 3 – 4 – 5 – 6 – 7 – 0 – 1 – 2 3 – 2 – 1 – 0 – 7 – 6 – 5 – 4
1 0 0 4 – 5 – 6 – 7 – 0 – 1 – 2 – 3 4 – 5 – 6 – 7 – 0 – 1 – 2 – 3
1 0 1 5 – 6 – 7 – 0 – 1 – 2 – 3 – 4 5 – 4 – 7 – 6 – 1 – 0 – 3 – 2
1 1 0 6 – 7 – 0 – 1 – 2 – 3 – 4 – 5 6 – 7 – 4 – 5 – 2 – 3 – 0 – 1
1 1 1 7 – 0 – 1 – 2 – 3 – 4 – 5 – 6 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0
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18
MB811L643242B-10/-12/-15/-10L/-12L/-15L
PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
SDRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations. Precharge
rewrites the bit line and to reset the internal Row address line and is e x ecuted b y the Precharge command (PRE).
With the Precharge command, SDRAM will automatically be in standby state after precharge time (tRP).
The precharged bank is selected by combination of AP and A11, A12 when Precharge command is asserted. If AP
= High, all banks are precharged regardless of A11, A12 (PALL). If AP = Low, a bank to be selected by A11, A12 is
precharged (PRE).
The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command
assertion.
This auto precharge is entered by AP = High when a read or write command is asserted. Refer to FUNCTIONAL
TRUTH TABLE.
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates
Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command. The
Auto-refresh command should also be asserted every 16 µs or a total 4096 refresh commands within a 64 ms period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the
refresh function until cancelled by SELFX.
The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once
SDRAM enters the self-refresh mode, all inputs except for CKE will be “don’t care” (either logic high or low level
state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF
command should only be issued after last read data has been appeared on DQ
Notes: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be
asserted prior to the self-refresh mode entry.
SELF-REFRESH EXIT (SELFX)
To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No Operation command (NOP)
or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High within one
tRC period after tCKSP
. Refer to Timing Diagram-16 for the detail.
It is recommended to assert an Auto-refresh command just after the tRC period to avoid the violation of refresh period.
Notes: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be
asserted after the self-refresh exit.
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation fields;
Burst Length, Burst Type, CAS latency, and Operation Code. Refer to MODE REGISTER TABLE in page 33.
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address
line. Once a mode register is prog rammed, the contents of the register will be held until re-programmed b y another
MRS command (or part loses power). MRS command should only be issued on condition that all DQ is in Hi-Z.
The condition of the mode register is undefined after the power-up stage. It is required to set each field after
initialization of SDRAM. Refer to POWER-UP INITIALIZATION below.
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19
MB811L643242B-10/-12/-15/-10L/-12L/-15L
POWER-UP INITIALIZATION
The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On
Sequence to execute read or write operation.
1. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input.
2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 µs.
3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL).
4. Assert minimum of 2 Auto-refresh command (REF).
5. Program the mode register by Mode Register Set command (MRS).
In addition, it is recommended DQM and CKE to trac k VDD to insure that output is High-Z state. The Mode Register
Set command (MRS) can be set before 2 Auto-refresh command (REF).
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20
MB811L643242B-10/-12/-15/-10L/-12L/-15L
CAS Latency = 2
RAS
CAS
DQ
DQ
tSI
Burst Length = 4
Active Read/Write Precharge
<SDRAM>
tHI
H : Read
L : Write
BA (A11, A12)
RA BA (A11, A12)
CA
Row Address Select Column Address Select
Fig. 2 – BASIC TIMING FOR CONVENTIONAL DRAM VS SYNCHRONOUS DRAM
Address
CLK
CS
RAS
CAS
CKE
WE
H
<Conventional DRAM>
BA (A11, A12)
AP (A10)
Precharge
HH
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21
MB811L643242B-10/-12/-15/-10L/-12L/-15L
MODE
REGISTER
SET
SELF
REFRESH
IDLE
READ
SUSPEND
BANK
ACTIVE
AUTO
REFRESH
POWER
DOWN
BANK
ACTIVE
SUSPEND
Fig. 3 – STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)
WRITE
WRITE
SUSPEND
POWER
ON PRECHARGE
READ
WRITE WITH
AUTO
PRECHARGE
READ WITH
AUTO
PRECHARGE
WRIT READ
READ
WRIT
BST BST
MRS SELF
SELFX
REF
ACTV
CKE
CKE\(CSUS)
CKE
CKE READ
WRIT
READA WRITA READA
CKE
WRITA
PRE or PALL
PRE or
PALL
POWER
APPLIED DEFINITION OF ALLOWS
Manual
Input Automatic
Sequence
WRITA READA
PRE or
PALL PRE or
PALL
CKE\(PD)
READ
SUSPEND
CKE
WRITE
SUSPEND CKE\
CKE\(CSUS)
CKE\(CSUS)
CKE\(CSUS)
CKE\(CSUS)
Note: CKE\ means CKE goes Low-level from High-level.
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22
MB811L643242B-10/-12/-15/-10L/-12L/-15L
■BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR 1 BANK OPERATION
Notes: *1. If tRP(min.)<CL×tCK, minimum latency is a sum of (BL+CL)×tCK.
*2. Assume all banks are in Idle state.
*3. Assume output is in High-Z state.
*4. Assume tRAS(min.) is satisfied.
*5. Assume no I/O conflict.
*6. Assume after the last data have been appeared on DQ.
*7. If tRP(min.)<(CL-1)×tCK, minimum latency is a sum of (BL+CL-1)×tCK.
Illegal Command
Second
command
(same
bank)
*4 *4
First
command
MRS tRSC tRSC tRSC tRSC tRSC tRSC tRSC
ACTV tRCD tRCD tRCD tRCD tRAS tRAS 1
READ 11 *5
1*5
1*4
1*4
1 1
READA
*1,2
BL
+
tRP
BL
+
tRP
*4
BL
+
tRP
*4
BL
+
tRP
*2
BL
+
tRP
*2,7
BL
+
tRP
WRIT tWR tWR 11 *4
tDPL
*4
tDPL 1
WRITA
*2
BL-1
+
tDAL
BL-1
+
tDAL
*4
BL-1
+
tDAL
*4
BL-1
+
tDAL
*2
BL-1
+
tDAL
*2
BL-1
+
tDAL
PRE
*2,3
tRP tRP 1*4
1*2
tRP
*2,6
tRP 1
PALL
*3
tRP tRP 11t
RP
*6
tRP 1
REF tRC tRC tRC tRC tRC tRC tRC
SELFX tRC tRC tRC tRC tRC tRC tRC
MRS
ACTV
READ
READA
WRIT
WRITA
PRE
PALL
REF
SELF
BST
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23
MB811L643242B-10/-12/-15/-10L/-12L/-15L
■ MULTI BANK OPERATIVE COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
Notes: *1. If tRP(min.)<CL×tCK, minimum latency is a sum of (BL+CL)×tCK.
*2. Assume bank of the object is in Idle sate.
*3. Assume output is in High-Z sate.
*4. tRRD(min.) of other bank (second command will be asserted) is satisfied.
*5. Assume other bank is in active, read or write state.
*6. Assume tRAS(min.) is satisfied.
*7. Assume other banks are not in READA/WRITA state.
*8. Assume after the last data have been appeared on DQ.
*9. If tRP(min.)<(CL-1)×tCK, minimum latency is a sum of (BL+CL-1)×tCK.
*10. Assume no I/O conflict.
Second
command
(other
bank)
*5 *5,6 *5 *5,6
First
command
MRS tRSC tRSC tRSC tRSC tRSC tRSC tRSC
ACTV
*2
tRRD
*7
1*7
1*7
1*7
1*6,7
1*7
tRAS 1
READ
*2,4
111 *10
1*10
1*6
1*6
1 1
*9
READA
*1,2
BL+
tRP
*2,4
1*6
1*6
1*6,10
1*6,10
1*6
1*6
BL+
tRP
*2
BL+
tRP
*2,9
BL+
tRP
WRIT
*2,4
11111 *6
1*6
tDPL 1
*9
WRITA
*2
BL-1
+
tDAL
*2,4
1
*6
1
*6
1
*6
1
*6
1
*6
1
*6
BL-1
+
tDAL
*2
BL-1
+
tDAL
*2
BL-1
+
tDAL
PRE
*2,3
tRP
*2,4
1*7
1*7
1*7
1*7
1*6,7
1*7
1*2
tRP
*2,8
tRP 1
*5
PALL
*3
tRP tRP 11t
RP
*8
tRP 1
REF tRC tRC tRC tRC tRC tRC tRC
SELFX tRC tRC tRC tRC tRC
MRS
ACTV
READ
READA
WRIT
WRITA
PRE
PALL
REF
SELF
BST
Illegal Command
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24
MB811L643242B-10/-12/-15/-10L/-12L/-15L
■MODE REGISTER TABLE
A2A1A0Burst Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
2
4
8
Reserved
Reserved
Reserved
Full Column
0
1
0
1
0
1
0
1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
BT = 0 BT = 1
A11 A10 A9A8A7A6A5A4A3A2ADDRESS
Op-
code 0 0 CL BT BL MODE
REGISTER
A3Burst Type
Sequential (Wrap round, Binary-up)
Interleave (Wrap round, Binary-up)
0
1
A6A5A4CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MODE REGISTER SET
A9Op-code
Burst Read & Burst Write
Burst Read & Single Write
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Notes: *1. When A9 = 1, burst length at Write is always one regardless of BL value.
*2. BL = 1 and Full Column are not applicable to the interleave mode.
*3. A7 = 1 and A8 = 1 is reserved for vender test.
A1A0
0
A12
00
*3
*3
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25
MB811L643242B-10/-12/-15/-10L/-12L/-15L
■ABSOLUTE MAXIMUM RATINGS (See WARNING)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Notes:
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
■CAPACITANCE (TA = 25°C, f = 1 MHz)
Parameter Symbol Value Unit
Voltage of VDD Supply Relative to VSS VDD, VDDQ –0.5 to +3.6 V
Voltage at Any Pin Relative to VSS VIN, VOUT –0.5 to +3.6 V
Short Circuit Output Current IOUT ±50 mA
Power Dissipation PD1.0 W
Storage Temperature TSTG –55 to +125 °C
Parameter Notes Symbol Min. Typ. Max. Unit
Supply Voltage VDD, VDDQ 2.3 2.5 2.7 V
VSS, VSSQ 000V
Input High Voltage *1 VIH 1.7 — VDD + 0.5 V
Input Low Voltage *2 VIL –0.5 — 0.7 V
Ambient Temperature TA0—70
°C
Parameter Symbol Min. Typ. Max. Unit
Input Capacitance, Except for CLK CIN1 2.5 — 5.0 pF
Input Capacitance for CLK CIN2 2.5 — 4.0 pF
I/O Capacitance CI/O 4.0 — 6.5 pF
*2. Undershoot limit: VIL (min)
3.6V
VIH
VIL Pulse width ≤ 5 ns
*1. Overshoot limit: VIH (max)
50% of pulse amplitude
VIH
VIL
-1.5V
pulse width measured at 50% of pulse amplitude.
= 3.6V for pulse width <= 5 ns acceptable, = VDD -1.5V for pulse width <= 5 ns acceptable,
pulse width measured at 50% of pulse amplitude.
50% of pulse amplitude
Pulse width ≤ 5 ns
VIHmin
VILmax
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26
MB811L643242B-10/-12/-15/-10L/-12L/-15L
■DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note 1, 2
(Continued)
Parameter Symbol Condition Value Unit
Min. Max.
Output High Voltage VOH(DC) IOH = –1 mA 2.0 — V
IOH = –2 mA 1.7 —
Output Low Voltage VOL(DC) IOL = 1 mA — 0.4 V
IOL = 2 mA — 0.7
Input Leakage Current (Any Input) ILI 0 V ≤ VIN ≤ VDD;
All other pins not under
test = 0 V –5 5 µA
Output Leakage Current ILO 0 V ≤ VIN ≤ VDD;
Data out disabled –5 5 µA
Operating Current
(Average Power
Supply Current)
MB811L643242B
-10/-10L
ICC1
Burst: Length = 1
tRC = min, tCK = min
One bank active
Output pin open
Addresses changed up to
1-time during tRC (min)
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—
130
mA
MB811L643242B
-12/-12L 120
MB811L643242B
-15/-15L 110
Precharge Standby
Current
(Power Supply
Current)
MB811L643242B
-10/-12/-15 ICC2P
CKE = VIL
All banks idle
tCK = min
Power down mode
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—2
mA
MB811L643242B
-10L/-12L/-15L —1.5
MB811L643242B
-10/-12/-15 ICC2PS
CKE = VIL
All banks idle
CLK = VIH or VIL
Power down mode
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—2.0
mA
MB811L643242B
-10L/-12L/-15L —1.5
ICC2N
CKE = VIH
All banks idle, tCK = 15 ns
NOP commands only,
Input signals (except to
CMD) are changed 1 time
during 30 ns
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—20mA
ICC2NS
CKE = VIH
All banks idle
CLK = VIH or VIL
Input signal are stable
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—10mA
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27
MB811L643242B-10/-12/-15/-10L/-12L/-15L
(Continued)
Parameter Sym-
bol Condition Value Un
it
Min. Max
.
Active Standby
Current
(Power Supply
Current)
MB811L643242B
-10/-12/-15 ICC3P
CKE = VIL
Any bank active
tCK = min
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—2m
A
MB811L643242B
-10L/-12L/-15L 1.5
MB811L643242B
-10/-12/-15 ICC3PS
CKE = VIL
Any bank active
CLK = VIH or VIL
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—2m
A
MB811L643242B
-10L/-12L/-15L 1.5
ICC3N
CKE = VIH
Any bank active
tCK = 15 ns
NOP commands only,
Input signals (except to
CMD) are changed 1
time during 30 ns
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—40
m
A
ICC3NS
CKE = VIH
Any bank idle
CLK = VIH or VIL
Input signals are stab le
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—20
m
A
Burst mode Current
(Average Power
Supply Current)
MB811L643242B-10/-10L
ICC4
tCK = min
Burst Length = 4
Output pin open
All banks active
Gapless data
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—
195
m
A
MB811L643242B-12/-12L 165
MB811L643242B-15/-15L 135
Refresh Current #1
(Average Power
Supply Current)
MB811L643242B-10
ICC5
Auto-refresh;
tCK = min
tRC = min
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—
195
m
A
MB811L643242B-12 180
MB811L643242B-15 165
MB811L643242B-10L 130
MB811L643242B-12L 115
MB811L643242B-15L 105
Refresh Current #2
(Average Power
Supply Current)
MB811L643242B
-10/12/15 ICC6
Self-refresh;
tCK = min
CKE ≤ 0.2 V
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VDD
—2m
A
MB811L643242B
-10L/12L/15L 0.5
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28
MB811L643242B-10/-12/-15/-10L/-12L/-15L
■AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note 2, 4, 5
Parameter Notes Symbol MB811L643242B
-10/10L MB811L643242B
-12/12L MB811L643242B
-15/15L Unit
Min. Max. Min. Max. Min. Max.
Clock Period CL = 2 tCK2 15 —17 —20 —ns
CL = 3 tCK3 10 12 15 ns
Clock High Time *6 tCH 3—4—4—ns
Clock Low Time *6 tCL 3—4—4—ns
Input Setup Time *6 tSI 2—3—3—ns
Input Hold Time *6 tHI 1—1—1—ns
Access Time
from Clock
(tCK = min)
*6,7,8,9 CL = 2 tAC2 —8—8—8ns
CL = 3 tAC3 888ns
Output in Low-Z *6 tLZ 3—3—3—ns
Output in High-Z *6,10 CL = 2 tHZ2 383838ns
CL = 3 tHZ3 888ns
Output Hold Time *6,9 CL = 2 tOH 3—3—3—
ns
CL = 3 ns
Time between Auto-Refresh
command interval tREFI — 15.6 — 15.6 — 15.6 µs
Time between Refresh tREF —64—64—64ms
Transition Time tT0.5 10 0.5 10 0.5 10 ns
CKE Setup Time f or Power
Down Exit Time *6 tCKSP 3—3—3—ns
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29
MB811L643242B-10/-12/-15/-10L/-12L/-15L
BASE VALUES FOR CLOCK COUNT/LATENCY
CLOCK COUNT FORMULA Note 11
Parameter Notes Symbol MB811L643242B
-10/10L MB811L643242B
-12/12L MB811L643242B
-15/15L Unit
Min. Max. Min. Max. Min. Max.
RAS Cycle Time *10 tRC 90 — 100 — 110 — ns
RAS Precharge Time tRP 30 — 35 — 40 — ns
RAS Active Time tRAS 60 110000 65 110000 70 110000 ns
RAS to CAS
Delay Time tRCD 40 — 40 — 40 — ns
Write Recovery Time tWR 10 — 12 — 15 — ns
RAS to RAS Bank Active Delay
Time tRRD 20 — 20 — 20 — ns
Data-in to Precharge Lead Time tDPL 10 — 12 — 15 — ns
Data-in to Active/Refresh
Command Period
CL=2 tDAL2 1 cyc +
tRP —1 cyc +
tRP —1 cyc +
tRP —ns
CL=3 tDAL3 2 cyc +
tRP —2 cyc +
tRP —2 cyc +
tRP —ns
Mode Resister Set Cycle Time tRSC 20 — 24 — 30 — ns
Clock ≥ (Round off a whole number)
Base Value
Clock Period
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30
MB811L643242B-10/-12/-15/-10L/-12L/-15L
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
Notes: *1. ICC depends on the output termination or load conditions, clock cycle rate, signal clocking rate; the
specified values are obtained with the output open and no termination register.
*2. An initial pause (DESL or NOP) of 100 µs is required after power-up followed by a minimum of two
Auto-refresh cycles.
*3. This value is for reference only.
*4. AC characteristics assume tT = 1 ns and 30pF of capacitive.
*5. 1.2 V is the reference level for measuring timing of input signals. T ransition times are measured between
VIH (min) and VIL (max). (See Fig. 5)
*6. If input signal transition time is longer than 1ns , (tT/2–0.5) ns should be added to tAC (max), tHZ (max),
tCKSP (min), (tT/2–0.5) ns should be subtracted from tLZ(min), tHZ(min), tOH(min), and (tT–1.0) ns should
be added to tCH (min), tCL (min), tSI (min), tHI (min).
*7. Maximum value of CL = 2 depends on tCK.
*8. tAC also specifies the access time at burst mode except for first access.
*9. tAC and tOH are the specs value under AC test load circuit show in Fig4.
*10. Specified where output buffer is no longer driven.
*11. Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP).
*12. All base values are measured from the clock edge at the command input to the clock edge f or the ne xt
command input. All clock counts are calculated by a simple formula: clock count equals base value
divided by clock period (round off to a whole number).
Parameter Notes Symbol MB811L643242B
-10/10L MB811L643242B
-12/12L MB811L643242B
-15/15L Unit
CKE to Clock Disable lCKE 111cycle
DQM to Output in High-Z lDQZ 222cycle
DQM to Input Data Delay lDQD 000cycle
Last Output to Write Command
Delay lOWD 222cycle
Write Command to Input Data Delay lDWD 000cycle
Precharge to Output
in High-Z Delay CL = 2 lROH2 222cycle
CL = 3 lROH3 333cycle
Burst Stop Command to
Output in High-Z Delay CL = 2 lBSH2 222cycle
CL = 3 lBSH3 333cycle
CAS to CAS Delay (min) lCCD 111cycle
CAS Bank Delay (min) lCBD 111cycle
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31
MB811L643242B-10/-12/-15/-10L/-12L/-15L
Output
Note: By adding appropriate correlation factors to the test conditions , tA C and tOH measured when the Output is coupled to
the Output Load Circuit are within specifications.
Fig. 4 – EXAMPLE OF AC TEST LOAD CIRCUIT
R1 = 50 Ω
CL = 30 pF
LVTTL
1.2 V
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32
MB811L643242B-10/-12/-15/-10L/-12L/-15L
tSI tHI
tCH
tCK
tAC tHZ
tOH
tLZ
tCL
CLK
Input
(Control,
Addr. & Data)
Output
2.0 V 1.2 V
0.4 V
1.2 V 2.0 V
0.4 V
1.2 V
2.0 V
0.4 V
Note: Reference level of input signal is 1.2 V for LVTTL.
Access time is measured at 1.2 V fo r LVTTL.
Fig. 5 – TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME
CLK
CKE
tCKSP (min)
NOP
Don’t Care
Don’t Care
Command
1 clock (min)
NOP ACTV
Fig. 6 – TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT
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33
MB811L643242B-10/-12/-15/-10L/-12L/-15L
Fig. 7 – TIMING DIAGRAM, PULSE WIDTH
tRC, tRP
, tRAS, tRCD, tWR, tREF
,
tDPL, tDAL, tRSC, tRRD, tCKSP
COMMAND COMMAND
CLK
Input
(Control)
Note: These parameters are a limit value of the r ising edge of the clock from one command input to next input. tCKSP is the
latency value from the rising edge of CKE.
Measurement reference voltage is 1.2 V.
Fig. 8 – TIMING DIAGRAM, ACCESS TIME
tRAC
tCAC
tAC
CLK
RAS
CAS
DQ
(Output)
tRCD
Q (Valid)
(CAS Latency –1) × tCK
Note: tRAC and tCAC are reference values. Data can be obtained after both tCAC = (CL-1) × tCK and tAC is satisfied.
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34
MB811L643242B-10/-12/-15/-10L/-12L/-15L
TIMING DIAGRAM – 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4)
Q1 Q2 (NO CHANGE) Q3 (NO CHANGE) Q4
D1 NOT
WRITTEN D2 NOT
WRITTEN D3 D4
CLK
CKE
CLK
(Internal)
DQ
(Read)
DQ
(Write)
Notes: *1. The latency of CKE (lCKE) is one clock.
*2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output
data remain the same data.
*3. During the write mode, data at the next clock of CSUS command is ignored.
*1
*3 *3
*1
*2 *2
*2 *2
ICKE (1 clock) ICKE (1 clock)
*2
TIMING DIAGRAM – 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT
NOP PD(NOP) DON’T CARE NOP ACTV
CLK
CKE
Command
1 clock
(min)
*1 *2 *3 NOP *3
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.
*2. Precharge command can be posted in conjunction with CKE after the last read data have been appeared on DQ.
*3. It is recommended to apply NOP command in conjunction with CKE.
*4. The ACTV command can be latched after tCKSP (min) + 1 clock (min).
tCKSP
(min)
tREF (max)
*4
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35
MB811L643242B-10/-12/-15/-10L/-12L/-15L
TIMING DIAGRAM – 3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
RAS
CAS
ROW
ADDRESS COLUMN
ADDRESS
Address
ICCD
(1 clock)
tRCD (min)
Note: CAS to CAS delay can be one or more clock period.
ICCD ICCD ICCD
COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
TIMING DIAGRAM – 4 : DIFFERENT BANK ADDRESS INPUT DELAY
tRRD (min)
CLK
RAS
CAS
ROW
ADDRESS
Address
Bank 0 Bank 3 Bank 3 Bank 3Bank 0 Bank 0
A11, A12(BA)
tRCD (min)
ICBD
(1 clock) ICBD
COLUMN
ADDRESS
ROW
ADDRESS COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
tRCD (min) or more
Note: CAS Bank delay can be one or more clock period.
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36
MB811L643242B-10/-12/-15/-10L/-12L/-15L
TIMING DIAGRAM – 5 : DQM0 - DQM3 - INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
CLK
DQM0-DQM3
(@ Read)
DQ
(@ Read)
DQM0-DQM3
(@ Write)
DQ
(@ Write)
Q1 Q2 Hi-Z Q4 End of burst
D1 MASKED D3 D4 End of burst
IDQZ (2 clocks)
IDQD (same clock)
TIMING DIAGRAM – 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK)
tRAS (min)
CLK
Command ACTV PRE
Note: PRECHARGE means ’ PRE’ or ’PALL’.
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37
MB811L643242B-10/-12/-15/-10L/-12L/-15L
TIMING DIAGRAM – 7 : READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4)
CLK
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Hi-Z
Q1
PRECHARGE
Q1 Q2
Q1 Q2 Q3
Q1 Q2 Q3 Q4
Hi-Z
Hi-Z
No effect (end of burst)
Note: In case of CL = 2, the lROH is 2 clocks.
In case of CL = 3, the lROH is 3 clocks.
PRECHARGE means ’ PRE’ or ’PALL’.
IROH (2 clocks)
IROH (2 clocks)
IROH (2 clocks)
PRECHARGE
PRECHARGE
PRECHARGE
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38
MB811L643242B-10/-12/-15/-10L/-12L/-15L
TIMING DIAGRAM – 8 : READ INTERRUPTED BY BURST STOP (EXAMPLE @ BL = Full Column)
CLK
Command
(CL = 2)
DQ
Command
(CL = 3)
DQ QnQn+1
Hi-Z
Hi-Z
Qn+2
Qn-1
Qn-2
QnQn+1
Qn–1
Qn–2
lBSH (2 clocks)
lBSH (3 clocks)
BST
BST
TIMING DIAGRAM – 9 : WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ CL = 2)
CLK
Command
DQ LAST
DATA-IN Masked
by BST
BST COMMAND
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39
MB811L643242B-10/-12/-15/-10L/-12L/-15L
TIMING DIAGRAM – 10 : WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 3)
tRP (min)
tDPL (min)
CLK
Command
DQ
ACTV
DATA-IN LAST
DATA-IN MASKED
by Precharge
Note: The precharge command (PRE) should only be issued after the tDPL of final data input is satisfied.
PRECHARGE means ’ PRE’ or ’PALL’.
PRECHARGE
TIMING DIAGRAM – 11 : READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 3, BL = 4)
CLK
Command
DQM
(DQM0-DQM3)
DQ Q1Masked D1D2
*1 *2 *3
WRIT
Notes: *1. First DQM makes high-impedance state High-Z between last output and first input data.
*2. Second DQM makes internal output data mask to avoid bus contention.
*3. Third DQM in illustrated above also makes internal output data mask. If burst read ends (final data output) at or after the
second clock of burst write, this third DQM is required to avoid internal bus contention.
IDWD (same clock)
IOWD (2 clocks)
IDQZ (2 clocks)
READ
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40
MB811L643242B-10/-12/-15/-10L/-12L/-15L
TIMING DIAGRAM – 12 : WRITE TO READ TIMING (EXAMPLE @ CL = 3, BL = 4)
CLK
Command
DQ
DQM
DQM0-DQM3
Note: Read command should be issued after tWR of final data input is satisfied.
WRIT READ
D1 Q1 Q2
D3
Masked
by READ
tWR (min)
D2
(CL-1) × tCK tAC (max)
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41
MB811L643242B-10/-12/-15/-10L/-12L/-15L
READA ACTVNOP or DESLACTV
Q1 Q2
tRAS (min)
2 clocks
(same value as BL)
tRP (min)
TIMING DIAGRAM – 13 : READ WITH AUTO-PRECHARGE
(EXAPLE @ CL = 2, BL = 2 Applied to same bank)
CLK
Command
DQM
(DQM0-DQM3)
DQ
Notes: *1. Precharge at read with Auto-precharge command (READA) is star ted from number of clocks that is the same as
Burst Length (BL) after the READA command is asserted.
*2. Next ACTV command should be issued after BL+tRP (min) from READA command.
BL+tRP (min)
*1 *2
WRITA ACTVACTV
D1 D2
tDAL (min)
TIMING DIAGRAM – 14 : WRITE WITH AUTO-PRECHARGE
(EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
CLK
Command
DQM
(DQM0-DQM3)
DQ
NOP or DESL
Notes: *1. Precharge at write with Auto-precharge is started after the tDPL from the end of burst.
*2. Even if the final data is masked by DQM, the precharge does not start the clock of final data input.
*3. Once auto precharge command is asserted, no new command within the same bank can be issued.
*4. Auto-precharge command doesn’t affect at full column burst operation except Burst READ & Single Write.
*5. Next command should be issued after BL+ tRP (min) at CL = 2, BL+1+tRP (min) at CL = 3 from WRITA command.
tRAS (min)
BL+tRP (min)
tDPL(min)*1
*5
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42
MB811L643242B-10/-12/-15/-10L/-12L/-15L
TIMING DIAGRAM – 15 : AUTO-REFRESH TIMING
tRC (min)
tRC (min)
CLK
Command
A11, A12(BA)
REF Command
NOP
BA
*1 NOP NOP REF NOP *4
DON’T CARE
Notes: *1. All banks should be precharged prior to the first Auto-refresh command (REF).
*2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter.
*3. Either NOP or DESL command should be asserted during tRC period while Auto-refresh mode.
*4. Any activ ation command such as A CTV or MRS command other than REF command should be asserted after tRC from the
last REF command.
*3
DON’T CARE
*4
TIMING DIAGRAM – 16 : SELF-REFRESH ENTRY AND EXIT TIMING
tRC (min)
tCKSP (min)
CLK
CKE
Command NOP
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry command (SELF).
*2. The Self-refresh Exit command (SELFX) is latched after tCKSP (min). It is recommended to apply NOP command in
conjunction with CKE.
*3. Either NOP or DESL command can be used during tRC period.
*4. CKE should be held high within one tRC period after tCKSP
.
*5. CKE level should be held less than 0.2 V during self-refresh mode.
SELF DON’T CARE SELFX Command
NOP *2 NOP *3
*1
tSI (min)
*4
*5
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43
MB811L643242B-10/-12/-15/-10L/-12L/-15L
TIMING DIAGRAM – 17 : MODE REGISTER SET TIMING
CLK
Command
Address
MRS NOP or DESL
MODE ROW
ADDRESS
ACTV
Notes: The Mode Register Set command (MRS) should only be asserted after all banks have been precharged.
tRSC (min)
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44
MB811L643242B-10/-12/-15/-10L/-12L/-15L
C
1996 FUJITSU LIMITED F86001S-1C-1
0.45/0.75
(.018/.030)
0~8˚
0.25(.010)
Details of "A" part
86 44
43
1
LEAD No.
INDEX
.009
−.002
+.002
−0.04
+0.05
0.22
M
0.10(.004)
22.22±0.10(.875±.004)*
0.50(.020)TYP 0.10(.004)
21.00(.827)REF
0.10±0.05
(.004±.002)
(STAND OFF)
1.20(.047)MAX
.006
−.001
+.002
−0.03
+0.05
0.145
10.16±0.10(.400±.004)
11.76±0.20(.463±.008)
"A"
■PACKAGE DIMENSION
C
1996 FUJITSU LIMITED F86001S-1C-1
0.45/0.75
(.018/.030)
0~8˚
0.25(.010)
Details of "A" part
86 44
43
1
LEAD No.
INDEX
.009
−.002
+.002
−0.04
+0.05
0.22
M
0.10(.004)
22.22±0.10(.875±.004)*
0.50(.020)TYP 0.10(.004)
21.00(.827)REF
0.10±0.05
(.004±.002)
(STAND OFF)
1.20(.047)MAX
.006
−.001
+.002
−0.03
+0.05
0.145
10.16±0.10(.400±.004)
11.76±0.20(.463±.008)
"A"
Dimensions in mm (inches)
(Mounting height)
86-pin plastic TSOP(II)
(FPT-86P-M01)
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45
MB811L643242B-10/-12/-15/-10L/-12L/-15L
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTR ONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9904
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inhereut chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
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