1
HGTP12N60A4, HGTG12N60A4,
HGT1S12N60A4S
600V, SMPS Series N-Channel IGBT
The HGTP12N60A4, HGTG12N60A4 and
HGT1S12N60A4S are MOS gated high voltage switching
devices combining the best features of MOSFETs and
bipolar transistors. These devices have the high input
impedance of a MOSFET and the low on-state conduction
loss of a bipolar transistor. The much lower on-state voltage
drop varies only moderately between 25oC and 150oC.
This IGBT is ideal for many high voltage switching
applications operating at high frequencies where low
conduction losses are essential. This device has been
optimized for high frequency switch mode power supplies.
Formerly Developmental Type TA49335.
Symbol
Features
• >100kHz Operation at 390V, 12A
• 200kHz Operation at 390V, 9A
• 600V Switching SOA Capability
• Typical Fall Time. . . . . . . . . . . . . . . . . 70ns at TJ = 125oC
• Low Conduction Loss
•
Temperature Compensating
SABER Model
http://www.intersil.com
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards
Packaging
JEDEC TO-220AB ALTERNATE VERSION
JEDEC TO-263AB
JEDEC STYLE TO-247
Ordering Information
PART NUMBER PACKAGE BRAND
HGTP12N60A4 TO-220AB 12N60A4
HGTG12N60A4 TO-247 12N60A4
HGT1S12N60A4S TO-263AB 12N60A4
NOTE: When ordering, use the entire part number. Add the suffix
9A to obtain the TO-263AB variant in tape and reel, e.g.
HGT1S12N60A4S9A
C
E
G
G
C
E
COLLECTOR
(FLANGE)
G
COLLECTOR
(FLANGE)
E
COLLECTOR
(FLANGE)
C
E
G
INTERSIL CORPORATION IGBT PRODUCT IS COVERED BY ONE OR MORE OF THE FOLLOWING U.S. PATENTS
4,364,073 4,417,385 4,430,792 4,443,931 4,466,176 4,516,143 4,532,534 4,567,641
4,587,713 4,598,461 4,605,948 4,618,872 4,620,211 4,631,564 4,639,754 4,639,762
4,641,162 4,644,637 4,682,195 4,684,413 4,694,313 4,717,679 4,743,952 4,783,690
4,794,432 4,801,986 4,803,533 4,809,045 4,809,047 4,810,665 4,823,176 4,837,606
4,860,080 4,883,767 4,888,627 4,890,143 4,901,127 4,904,609 4,933,740 4,963,951
4,969,027
Data Sheet May 1999 File Number
4656.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
2
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
HGTG12N60A4, HGTP12N60A4,
HGT1S12N60A4S UNITS
Collector to Emitter Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . BVCES 600 V
Collector Current Continuous
At TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC25 54 A
At TC = 110oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C110 23 A
Collector Current Pulsed (Note 1) . . . . . . . . . . . . . . . . . . . . . . . .ICM 96 A
Gate to Emitter Voltage Continuous. . . . . . . . . . . . . . . . . . . . . VGES ±20 V
Gate to Emitter Voltage Pulsed . . . . . . . . . . . . . . . . . . . . . . . . VGEM ±30 V
Switching Safe Operating Area at TJ = 150oC, Figure 2 . . . . .SSOA 60A at 600V
Power Dissipation Total at TC = 25oC . . . . . . . . . . . . . . . . . . . . . PD167 W
Power Dissipation Derating TC > 25oC . . . . . . . . . . . . . . . . . . . . . . . 1.33 W/oC
Operating and Storage Junction Temperature Range . . . . TJ, TSTG -55 to 150 oC
Maximum Lead Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . TPKG 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. Pulse width limited by maximum junction temperature.
Electrical Specifications TJ = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Collector to Emitter Breakdown Voltage BVCES IC = 250µA, VGE = 0V 600 - - V
Emitter to Collector Breakdown Voltage BVECS IC = 10mA, VGE = 0V 10 - - V
Collector to Emitter Leakage Current ICES VCE = 600V TJ = 25oC - - 250 µA
TJ = 125oC - - 2.0 mA
Collector to Emitter Saturation Voltage VCE(SAT) IC = 12A,
VGE = 15V TJ = 25oC - 2.0 2.7 V
TJ = 125oC - 1.6 2.0 V
Gate to Emitter Threshold Voltage VGE(TH) IC = 250µA, VCE = 600V - 5.6 - V
Gate to Emitter Leakage Current IGES VGE = ±20V - - ±250 nA
Switching SOA SSOA TJ = 150oC, RG = 10Ω, VGE = 15V
L = 100µH, VCE = 600V 60 - - A
Gate to Emitter Plateau Voltage VGEP IC = 12A, VCE = 300V - 8 - V
On-State Gate Charge Qg(ON) IC = 12A,
VCE = 300V VGE = 15V - 78 96 nC
VGE = 20V - 97 120 nC
Current Turn-On Delay Time td(ON)I IGBT and Diode at TJ = 25oC
ICE = 12A
VCE = 390V
VGE =15V
RG= 10Ω
L = 500µH
Test Circuit - (Figure 20)
-17- ns
Current Rise Time trI -8-ns
Current Turn-Off Delay Time td(OFF)I -96- ns
Current Fall Time tfI -18- ns
Turn-On Energy (Note 3) EON1 -55- µJ
Turn-On Energy (Note 3) EON2 - 160 - µJ
Turn-Off Energy (Note 2) EOFF -50 - µJ
HGTP12N60A4, HGTG12N60A4, HGT1S12N60A4SSP
3
Current Turn-On Delay Time td(ON)I IGBT and Diode at TJ = 125oC
ICE = 12A
VCE = 390V
VGE = 15V
RG= 10Ω
L = 500µH
Test Circuit - (Figure 20)
-17- ns
Current Rise Time trI -16- ns
Current Turn-Off Delay Time td(OFF)I - 110 170 ns
Current Fall Time tfI -7095ns
Turn-On Energy (Note 3) EON1 -55- µJ
Turn-On Energy (Note 3) EON2 - 250 350 µJ
Turn-Off Energy (Note 2) EOFF - 175 285 µJ
Thermal Resistance Junction To Case RθJC - - 0.75 oC/W
NOTES:
2. Turn-Off Energy Loss (EOFF) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending
at the point where the collector current equals zero (ICE = 0A). All devices were tested per JEDEC Standard No. 24-1 Method for Measurement
of Power Device Turn-Off Switching Loss. This test method produces the true total Turn-Off Energy Loss.
3. Values for two Turn-On loss conditions are shown for the convenience of the circuit designer. EON1 is the turn-on loss of the IGBT only. EON2
is the turn-on loss when a typical diode is used in the test circuit and the diode is at the same TJ as the IGBT. The diode type is specified in
Figure 20.
Electrical Specifications TJ = 25oC, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. DC COLLECTOR CURRENT vs CASE
TEMPERATURE FIGURE 2. MINIMUM SWITCHING SAFE OPERATING AREA
FIGURE 3. OPERATING FREQUENCY vs COLLECTOR TO
EMITTER CURRENT FIGURE 4. SHORT CIRCUIT WITHSTAND TIME
TC, CASE TEMPERATURE (oC)
ICE, DC COLLECTOR CURRENT (A)
50
10
0
40
20
30
25 75 100 125 150
60
50
VGE = 15V
VCE, COLLECTOR TO EMITTER VOLTAGE (V) 700
40
0
ICE, COLLECTOR TO EMITTER CURRENT (A)
10
20
300 400200100 500 600
0
50
60
30
70 TJ= 150oC, RG = 10Ω, VGE = 15V, L = 200µH
TCVGE
15V
75oC
fMAX, OPERATING FREQUENCY (kHz)
1
ICE, COLLECTOR TO EMITTER CURRENT (A)
10 3
300
3010 20
500
fMAX1 = 0.05 / (td(OFF)I + td(ON)I)
RØJC = 0.75oC/W, SEE NOTES
PC = CONDUCTION DISSIPATION
(DUTY FACTOR = 50%)
fMAX2 = (PD- PC) / (EON2 + EOFF)
TJ= 125oC, RG = 10Ω, L = 500µH, VCE = 390V
100
VGE, GATE TO EMITTER VOLTAGE (V)
ISC, PEAK SHORT CIRCUIT CURRENT (A)
tSC, SHORT CIRCUIT WITHSTAND TIME (µs)
9101112 15
0
2
10
16
50
125
175
300
tSC
ISC
20
250
13 14
4
6
8
12
14
18
75
100
150
200
225
275
VCE = 390V, RG = 10Ω, TJ= 125oC
HGTP12N60A4, HGTG12N60A4, HGT1S12N60A4SPD
4
FIGURE 5. COLLECTOR TO EMITTER ON-STATE VOLTAGE FIGURE 6. COLLECTOR TO EMITTER ON-STATE VOLTAGE
FIGURE 7. TURN-ON ENERGY LOSS vs COLLECTOR TO
EMITTER CURRENT FIGURE 8. TURN-OFF ENERGY LOSS vs
COLLECTOR TO EMITTER CURRENT
FIGURE 9. TURN-ON DELAY TIME vs COLLECTOR TO
EMITTER CURRENT FIGURE 10. TURN-ON RISE TIME vs COLLECTOR TO
EMITTER CURRENT
Typical Performance Curves
Unless Otherwise Specified (Continued)
0 0.5 1.0
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
ICE, COLLECTOR TO EMITTER CURRENT (A)
0
4
8
1.5 2 2.5
16
20
12
TJ = 125oC
TJ = 150oC
PULSE DURATION = 250µs
DUTY CYCLE < 0.5%, VGE = 12V
24
TJ = 25oC
ICE, COLLECTOR TO EMITTER CURRENT (A)
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
DUTY CYCLE < 0.5%, VGE = 15V
PULSE DURATION = 250µs
TJ = 150oC
TJ = 25oC
TJ = 125oC
0 0.5 1.0 1.5 2 2.5
4
8
16
12
20
24
0
EON2, TURN-ON ENERGY LOSS (µJ)
500
300
ICE, COLLECTOR TO EMITTER CURRENT (A)
400
200
600
0
700
64 10121416818202224
TJ = 125oC, VGE = 12V, VGE = 15V
RG = 10Ω, L = 500µH, VCE = 390V
TJ = 25oC, VGE = 12V, VGE = 15V
100
2
300
I
CE
, COLLECTOR TO EMITTER CURRENT (A)
E
OFF
, TURN-OFF ENERGY LOSS (µJ)
0
50
200
100
250
350
400
T
J
= 25
o
C, V
GE
= 12V OR 15V
T
J
= 125
o
C, V
GE
= 12V OR 15V
150
642 101214168 18202224
R
G
= 10Ω, L = 500µH, V
CE
= 390V
ICE, COLLECTOR TO EMITTER CURRENT (A)
td(ON)I, TURN-ON DELAY TIME (ns)
10
11
12
13
14
15
642 101214168 18202224
16
17
18
TJ = 25oC, TJ = 125oC, VGE = 15V
TJ = 25oC, TJ = 125oC, VGE = 12V
RG = 10Ω, L = 500µH, VCE = 390V
ICE, COLLECTOR TO EMITTER CURRENT (A)
trI, RISE TIME (ns)
0
4
16
12
8
642 101214168 18202224
20
32
28
24
RG = 10Ω, L = 500µH, VCE = 390V
TJ = 125oC, OR TJ = 25oC, VGE = 12V
TJ = 25oC OR TJ = 125oC, VGE = 15V
HGTP12N60A4, HGTG12N60A4, HGT1S12N60A4S
5
FIGURE 11. TURN-OFF DELAY TIME vs COLLECTOR TO
EMITTER CURRENT FIGURE 12. FALL TIME vs COLLECTOR TO EMITTER
CURRENT
FIGURE 13. TRANSFER CHARACTERISTIC FIGURE 14. GATE CHARGE WAVEFORMS
FIGURE 15. TOTAL SWITCHING LOSS vs CASE
TEMPERATURE FIGURE 16. TOTAL SWITCHING LOSS vs GATE RESISTANCE
Typical Performance Curves
Unless Otherwise Specified (Continued)
482
95
6
85
90
ICE, COLLECTOR TO EMITTER CURRENT (A)
td(OFF)I, TURN-OFF DELAY TIME (ns)
12
115
1614
105
110
10
100
VGE = 12V, VGE = 15V, TJ = 25oC
VGE = 12V, VGE = 15V, TJ = 125oC
RG = 10Ω, L = 500µH, VCE = 390V
18 20 22 24
ICE, COLLECTOR TO EMITTER CURRENT (A)
tfI, FALL TIME (ns)
10
30
20
50
70
40
60
RG = 10Ω, L = 500µH, VCE = 390V
TJ = 25oC, VGE = 12V OR 15V
TJ = 125oC, VGE = 12V OR 15V
482 6 12 161410 18 20 22 24
80
90
ICE, COLLECTOR TO EMITTER CURRENT (A)
0
50
100
1378910 12
VGE, GATE TO EMITTER VOLTAGE (V)
11
150
200
14 15
250
6
PULSE DURATION = 250µs
DUTY CYCLE < 0.5%, VCE = 10V
16
TJ = 125oC
TJ = -55oC
TJ = 25oC
VGE, GATE TO EMITTER VOLTAGE (V)
QG, GATE CHARGE (nC)
2
14
0
4
10
IG(REF) = 1mA, RL = 25Ω, TC = 25oC
VCE = 200V
VCE = 400V
6
8
12
16
VCE = 600V
10 20 30 40 6050 70 800
ICE = 24A
ICE = 12A
ICE = 6A
0
0.2
0.4
50 75 100
TC, CASE TEMPERATURE (oC)
0.6
1.0
12525 150
1.2
0.8
ETOTAL, TOTAL SWITCHING ENERGY LOSS (mJ)
ETOTAL = EON2 + EOFF
RG = 10Ω, L = 500µH, VCE = 390V, VGE = 15V
0.1 10 100
RG, GATE RESISTANCE (Ω)
1
5 1000
E
TOTAL
, TOTAL SWITCHING ENERGY LOSS (mJ)
ICE = 12A
ICE = 24A
ICE = 6A
10 TJ = 125oC, L = 500µH, VCE = 390V, VGE = 15V
ETOTAL = EON2 + EOFF
HGTP12N60A4, HGTG12N60A4, HGT1S12N60A4S
6
FIGURE 17. CAPACITANCE vs COLLECTOR TO EMITTER
VOLTAGE FIGURE 18. COLLECTOR TO EMITTER ON-STATE VOLTAGE
vs GATE TO EMITTER VOLTAGE
FIGURE 19. IGBT NORMALIZED TRANSIENT THERMAL RESPONSE, JUNCTION TO CASE
Test Circuit and Waveforms
FIGURE 20. INDUCTIVE SWITCHING TEST CIRCUIT FIGURE 21. SWITCHING TEST WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified (Continued)
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
C, CAPACITANCE (nF)
CRES
0 5 10 15 20 25
0
0.5
1.0
2.0
2.5
3.0
1.5
FREQUENCY = 1MHz
COES
CIES
VGE, GATE TO EMITTER VOLTAGE (V)
89
1.9 10 12
2.0
2.2
2.1
11 13 14 15 16
2.3
2.4
VCE, COLLECTOR TO EMITTER VOLTAGE (V)
ICE = 18A
ICE = 12A
ICE = 6A
DUTY CYCLE < 0.5%, VGE = 15V
PULSE DURATION = 250µs, TJ = 25oC
t1, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED THERMAL RESPONSE
10-2
10-1
100
10-5 10-3 10-2 10-1 100101
10-4
t1
t2
PD
DUTY FACTOR, D = t1 / t2
PEAK TJ = (PDX ZθJC X RθJC) + TC
SINGLE PULSE
0.1
0.2
0.5
0.05
0.01
0.02
RG = 10Ω
L = 500µH
VDD = 390V
+
-
RHRP660
tfI
td(OFF)I trI
td(ON)I
10%
90%
10%
90%
VCE
ICE
VGE
EOFF
EON2
HGTP12N60A4, HGTG12N60A4, HGT1S12N60A4S
7
Handling Precautions for IGBTs
Insulated Gate Bipolar Transistors are susceptible to gate-
insulation damage by the electrostatic discharge of energy
through the devices. When handling these devices, care
should be exercised to assure that the static charge built in
the handler’s body capacitance is not discharged through
the device. With proper handling and application procedures,
however, IGBTs are currently being extensively used in
production by numerous equipment manufacturers in
military, industrial and consumer applications, with virtually
no damage problems due to electrostatic discharge. IGBTs
can be handled safely if the following basic precautions are
taken:
1. Prior to assembly into a circuit, all leads should be kept
shorted together either by the use of metal shorting
springs or by the insertion into conductive material such
as “ECCOSORBD™ LD26” or equivalent.
2. When devices are removed by hand from their carriers,
the hand being used should be grounded by any suitable
means - for example, with a metallic wristband.
3. Tips of soldering irons should be grounded.
4. Devices should never be inserted into or removed from
circuits with power on.
5. GateVoltage Rating-Neverexceedthegate-voltagerat-
ing of VGEM. Exceeding the rated VGE can result in per-
manent damage to the oxide layer in the gate region.
6. Gate Termination - The gates of these devices are es-
sentially capacitors. Circuits that leave the gate open-cir-
cuited or floating should be avoided. These conditions
can result in turn-on of the device due to voltage buildup
on the input capacitor due to leakage currents or pickup.
7. Gate Protection - These devices do not have an internal
monolithic Zener diode from gate to emitter. If gate pro-
tection is required an external Zener is recommended.
Operating Frequency Information
Operating frequency information for a typical device
(Figure 3) is presented as a guide for estimating device
performance for a specific application. Other typical
frequency vs collector current (ICE) plots are possible using
the information shown for a typical unit in Figures 5, 6, 7, 8, 9
and 11. The operating frequency plot (Figure 3) of a typical
device shows fMAX1 or fMAX2; whichever is smaller at each
point. The information is based on measurements of a
typical device and is bounded by the maximum rated
junction temperature.
fMAX1 is defined by fMAX1 = 0.05/(td(OFF)I+ td(ON)I).
Deadtime (the denominator) has been arbitrarily held to 10%
of the on-state time for a 50% duty factor. Other definitions
are possible. td(OFF)I and td(ON)I are defined in Figure 21.
Device turn-off delay can establish an additional frequency
limiting condition for an application other than TJM.
fMAX2 is defined b y fMAX2 = (PD - PC)/(EOFF + EON2). The
allowable dissipation (PD) is defined by PD=(T
JM -T
C)/RθJC.
The sum of de vice s witching and conduction losses m ust not
e xceed PD. A 50% duty factor w as used (Figure 3) and the
conduction losses (PC) are approximated b y P C = (VCE x
ICE)/2.
EON2 and EOFF are defined in the switching waveforms
shown in Figure 21. EON2 is the integral of the
instantaneous power loss (ICE x VCE) during turn-on and
EOFF is the integral of the instantaneous power loss (ICE x
VCE) during turn-off. All tail losses are included in the
calculation for EOFF; i.e., the collector current equals zero
(ICE = 0).
HGTP12N60A4, HGTG12N60A4, HGT1S12N60A4S
ECCOSORBD™ is a trademark of Emerson and Cumming, Inc.
8
HGTP12N60A4, HGTG12N60A4, HGT1S12N60A4S
TO-263AB
SURFACE MOUNT JEDEC TO-263AB PLASTIC PACKAGE
TO-263AB
24mm TAPE AND REEL
MINIMUM PAD SIZE RECOMMENDED FOR
SURFACE-MOUNTED APPLICATIONS
EA1
A
H1
D
L
be
e1
L2
b1
L1
c
TERM. 4
13
13
L3
b2
TERM. 4 0.450
0.350
0.150
(3.81)
0.080 TYP (2.03)
0.700
(11.43)
(8.89)
(17.78)
0.062 TYP (1.58)
J1
SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX
A 0.170 0.180 4.32 4.57 -
A10.048 0.052 1.22 1.32 4, 5
b 0.030 0.034 0.77 0.86 4, 5
b10.045 0.055 1.15 1.39 4, 5
b20.310 - 7.88 - 2
c 0.018 0.022 0.46 0.55 4, 5
D 0.405 0.425 10.29 10.79 -
E 0.395 0.405 10.04 10.28 -
e 0.100 TYP 2.54 TYP 7
e10.200 BSC 5.08 BSC 7
H10.045 0.055 1.15 1.39 -
J10.095 0.105 2.42 2.66 -
L 0.175 0.195 4.45 4.95 -
L10.090 0.110 2.29 2.79 4, 6
L20.050 0.070 1.27 1.77 3
L30.315 - 8.01 - 2
NOTES:
1. These dimensions are within allowable dimensions of Rev. C of
JEDEC TO-263AB outline dated 2-92.
2. L3and b2dimensions established a minimum mounting surface
for terminal 4.
3. Solder finish uncontrolled in this area.
4. Dimension (without solder).
5. Add typically 0.002 inches (0.05mm) for solder plating.
6. L1 is the terminal length for soldering.
7. Positionofleadtobemeasured0.120inches(3.05mm)frombottom
of dimension D.
8. Controlling dimension: Inch.
9. Revision 11 dated 5-99.
2.0mm
4.0mm 1.75mm
1.5mm
DIA. HOLE
C
L
USER DIRECTION OF FEED
16mm
24mm
330mm 100mm
13mm
30.4mm
24.4mm
COVER TAPE
GENERAL INFORMATION
1. 800 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
ACCESS HOLE
40mm MIN.
9
HGTP12N60A4, HGTG12N60A4, HGT1S12N60A4S
TO-247
3 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE
LEAD 1 - GATE
LEAD 2 - COLLECTOR
LEAD 3 - EMITTER
TERM. 4 - COLLECTOR
A
b
b1
c
D
E
L
L1
ØR
12
e1
31
J1
ØS
Q
ØP
BACK VIEW
TERM. 4
3
e
b2
2
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.180 0.190 4.58 4.82 -
b 0.046 0.051 1.17 1.29 2, 3
b10.060 0.070 1.53 1.77 1, 2
b20.095 0.105 2.42 2.66 1, 2
c 0.020 0.026 0.51 0.66 1, 2, 3
D 0.800 0.820 20.32 20.82 -
E 0.605 0.625 15.37 15.87 -
e 0.219 TYP 5.56 TYP 4
e10.438 BSC 11.12 BSC 4
J10.090 0.105 2.29 2.66 5
L 0.620 0.640 15.75 16.25 -
L10.145 0.155 3.69 3.93 1
ØP 0.138 0.144 3.51 3.65 -
Q 0.210 0.220 5.34 5.58 -
ØR 0.195 0.205 4.96 5.20 -
ØS 0.260 0.270 6.61 6.85 -
NOTES:
1. Lead dimension and finish uncontrolled in L1.
2. Lead dimension (without solder).
3. Add typically 0.002 inches (0.05mm) for solder coating.
4. Positionofleadtobemeasured0.250inches(6.35mm)frombottom
of dimension D.
5. Positionofleadtobemeasured0.100inches(2.54mm)frombottom
of dimension D.
6. Controlling dimension: Inch.
7. Revision 1 dated 1-93.
10
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries .
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Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
HGTP12N60A4, HGTG12N60A4, HGT1S12N60A4S
TO-220AB
(Alternate Version)
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
E
ØP
D
L
L1
60o
b1
b
e
e1
H1
1J1
23
TERM. 4
Q
c
A1
A
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.170 0.180 4.32 4.57 -
A10.048 0.052 1.22 1.32 2, 4
b 0.030 0.034 0.77 0.86 2, 4
b10.045 0.055 1.15 1.39 2, 4
c 0.018 0.022 0.46 0.55 2, 4
D 0.590 0.610 14.99 15.49 -
E 0.395 0.405 10.04 10.28 -
e 0.100 TYP 2.54 TYP 5
e10.200 BSC 5.08 BSC 5
H10.235 0.255 5.97 6.47 -
J10.095 0.105 2.42 2.66 6
L 0.530 0.550 13.47 13.97 -
L10.110 0.130 2.80 3.30 3
ØP 0.149 0.153 3.79 3.88 -
Q 0.105 0.115 2.66 2.92 -
NOTES:
1. These dimensions are within allowable dimensions of Rev. J of
JEDEC TO-220AB outline dated 3-24-87.
2. Dimension (without solder).
3. Solder finish uncontrolled in this area.
4. Add typically 0.002 inches (0.05mm) for solder plating.
5. Position of lead to be measured 0.250 inches (6.35mm) from
bottom of dimension D.
6. Position of lead to be measured 0.100 inches (2.54mm) from
bottom of dimension D.
7. Controlling dimension: Inch.
8. Revision 3 dated 7-97.
