$< XILINX June 1, 1996 (Version 1.0) XC95180 In-System Programmable CPLD Advance Product Specification Features * 10 ns pin-to-pin logic delays on all pins . fCNT to 111 MHz * 180 macrocells with 4,000 usable gates e Up to 168 user I/O pins 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full voltage and temperature range Enhanced pin-locking architecture * Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals e Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs with 3.3 V or 5 V I/O capability e PCl compliant (-10 speed grade) Advanced 0.6 lum CMOS 5V FastFLASH technology Available in 160-pin PQFP, and 208-pin HQFP packages Description The XC95180 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of ten 36V18 Function Blocks, providing 4,000 usable gates with propagation delays of 10 ns. See Figure 1 for the architec- ture overview. Power Management Power dissipation can be reduced in the XC95180 by con- figuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: loc (mA) = MCyp (1.7) + MC; p (0.9) + MC (0.006 mA/MHz) f Where: MCyip = Macrocells in high-performance mode MC, p = Macrocells in low-power mode MC =Total number of macrocells used f = Clock frequency (MHz) June 1, 1996 (Version 1.0) 3-41XC95180 In-System Programmable CPLD > JTAG _ _ j JTAG Port 1 1, Controller <t > In-System Programming Controller A A A y Y Y - 36 | ~=Function vo K_ > 18, Block 1 vo Ko ] Macrocells vO kK >+-__J ho Ad y v0 K | z s 36 FE nection e Ss : Block 2 s Macrocells ie) 3 1to 18 e Blocks IK A A i vo KS w J 36, vo K-44 > 2 6 =) = Function 5 | 18, Block 3 vO K_ >} Pa Macrocells uw 1 to 18 Wok 3 A A A vOrGcK K_>}-* 36. y > > Function | 1 18, VO/GSR Ke : Block 4 Macrocells VO/GTS K > 4 1to 18 1 tf e e = 36. Function 18. Block 10 Macrocelts 110 18 Figure 1: XC95180 Architecture | __f = Note: Function Block outputs indicated by bold line drive directly to 1/O Blocks X5923 June 1, 1996 (Version 1.0)$< XILINX XC95180 I/O Pins alee Macrocell |PQ160|HQ208 psean Notes ace Macrocell |PQ160|HQ208 pecan Notes i 1 |39_ | 537 3 1 = 481 429 j 3 22 | 30 | 534 3 2 37 | 49 | 426 7 3 23 | at | 531 3 3 38. | 50 | 423 i 4 24 | a2 | 528 3 4 39. | 61 | 420 1 5 25. | 33 | 525 3 5 4) 55) 417 | TI 1 6 26 | 34 | 522 3 6 43 | 56 | 414 1 7 | 40 | 519 3 7 | 541 414 1 8 27 | 35 | 516 3 8 44 | 57 | 408 1 9 28 | 36 | 513 3 g 45. | 58 | 405 1 10 29 | 37 | 510 3 10 47 | 60 | 402 i Ti 30. | 38 | 507 3 17 48 | 61 | 399 1 12 32 | 43. | 504 3 12 49 | 63 | 396 1 13 =} a1 1501 3 13 | 62 | 393 1 14 33.) 44 | 498 | Ti) 3 14 50 | 64 | 390 i 15 34 | 45 | 495 3 15 52 | 70 | 387 1 16 35. | 46 | 492 1 11 3 16 53 | 71 | 384 1 17 36 | 47 | 489 3 17 56 | 74) 381 1 18 = 1 486 3 18 = =| 387 2 F ~ 14 | 483 4 1 = 196 | 375 2 2 6 7 | 480 1 1] 4 2 150 | 194 | 372 3 3 7 8 | 477 4 3 151 | 197 | 369 2 4 8 9 | 474 | 11] 4 4 152 | 198 | 366 2 5 9 10 | 471 4 5 153 | 199 | 363 3 6 1 | 15 | 468 4 6 154 | 200 | 360 3 7 =| 28 | 465 4 7 | 303 | 387 2 8 i2 | 16 | 462 4 8 165 | 201 | 354 2 9 13 | 17 | 459 4 9 156 | 202 | 351 2 10 14 | 18 | 456 4 10 | 208 | 348 3 11 15 | 19 | 453 4 Ti 158 | 205 | 345 2 12 16 | 20 | 450 4 12 159 | 206 | 342 | Th] 2 13 | 29 | 447 4 13 = 12 | 339 2 14 17 | 21 | 444 4 14 a 3 | 336 | Ti] 2 15 18 | 22 | 444 4 15 3 4 | 333 2 16 19 | 23 | 438 4 16 4 5 | 330 | 1] 2 17 21 | 25 | 435 4 17 5 6 | 327 3 18 = =| 432 4 18 = =| 324 Notes: [1] Global control pin Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global Signals are fixed. June 1, 1996 (Version 1.0) 3-43XC95180 In-System Programmable CPLD XC95180 I/O Pins (continued) Pureten Macrocell | PQ160|HQ208 Bscan Notes runetion Macrocell |PQ160|HQ208 escan Notes 5 i 66 38 7 1 =T 0 T a13 5 3 54. | 72 | 318 7 2 69 | 89 | 210 5 3 55 | 73) 315 7 3 72 | 95 | 207 5 4 57 | 75 | 312 7 4 74 | 97 | 204 5 5 58 | 76 | 309 7 5 76199) 201 5 6 59 | 77 | 306 7 6 77 | 100 | 198 5 7 =) 67} 308 7 7 =) 91} 195 5 8 60 | 78 | 300 7 8 78 | 102 | 192 5 9 62 | 62 | 297 7 9 79 | 103 | 189 5 10 =| 69 | 294 7 10 = | to1 | 186 5 11 63 | 63 | 201 7 11 B2 | 110 | 183 5 12 64 | 84 | 288 7 12 ga | 111 | 180 5 13 =| 80 | 285 7 13 =) 406 | 177 5 14 6 | 85 | 282 7 14 84 | 112) 174 5 5 66 | 86 | 279 7 15 8 | 113) 1714 5 16 67 | 87 | 276 7 16 ge. | 114) 168 5 17 68 | 88 | 273 7 17 a7 | 115 | 165 5 18 = =| 270 7 18 = =) 462 6 1 = 169 | 267 8 1 = 144 | 159 6 3 134 | 174 | 264 8 2 118 | 154 | 156 6 3 135 | 175 | 261 B 3 119 | 155 | 153 6 4 138 | 178 | 2568 8 4 22 | 158 | 150 6 5 139 | 170 | 255 8 5 123 | 159 | 147 6 6 140 | 180 | 252 8 6 124 | 160 | 144 6 7 = 783 | 249 8 7 a 6 5 143 | 182 | 246 8 8 125 | tei | 138 6 5 143 | 185 | 243 8 g 126 | 162 | 135 6 10 =) 789 | 240 B 10 | 165 | 132 6 11 144 | 186 | 237 8 Ti 128 | 164 | 129 6 12 145 | 187 | 234 8 12 129 | 166 | 126 6 13 =) t95 | 331 8 13 | 168 | 123 6 14 146 | 188 | 228 8 14 730 | 167 | 120 6 15 147 | 191 | 225 8 15 131 | 170 | 117 6 16 148 | 192 | 222 8 16 132 | 471 | 114 6 17 149 | 193 | 219 8 17 133. | 473 | 414 6 18 = | 216 8 18 = =| 108 3-44 June 1, 1996 (Version 1.0)$< XILINX XC95180 I/O Pins (continued) een Macrocell | PQ160|HQ208 pscan Notes Paneer Macrocell |PQ160|HQ208 Bsean Notes 9 1 = = 105 10 1 = = 51 9 2 ga. | 116 | 102 10 2 104. | 135 | 48 9 3 89 117 | 99 10 3 105 | 136 | 45 9 4 90 118 | 96 10 4 106 | 137 | 42 9 5 of 121 93 10 5 107 | 138 | 39 9 6 92 j22 | 90 10 6 ios | 139 | 36 9 7 = 107 | 87 10 7 = 120 | 33 9 8 93 | 123 | 284 10 8 io9 | 140 | 30 9 9 95 125 | 81 10 9 11 | 145 | 27 9 10 = 109 | 78 10 10 = 142 | 24 9 11 96 | 126 | 75 10 11 2 | 146 [21 9 12 97 | 127 | 72 10 12 113 | 147 18 9 13 = 119 | 69 10 13 = 143 | 15 9 14 98 | 128 | 66 10 14 114 | 148 12 9 15 tor | 131 63 10 15 115 | 149 9 9 16 1o2 | 133 | 60 10 16 116 | 150 6 9 17 103 | 134 | 57 10 17 117 | 152 3 9 18 = = 54 10 18 = = 0 XC95180 Global, JTAG and Power Pins Pin Type PQi60 HQ208 VO/GCKI 33 44 VO/GCK2 35 46 VOIGCK3 42 55 VO/GTS1 6 7 VO/GTS2 B 9g VO/GTS3 2 3 VO/GTS4 4 5 VOIGSR 159 206 TCK 75 98 TDI 7A 94 TDO 136 176 TS 73 96 VocinT DY 10,46,94, 157 11,59, 124,153,204 Vocio 3.3 V5 V 1,41,61,81,121,141 1,26,53,65,79,92,105, 132,157,172,181,184 GND 20,31,40,51,70,80, 2,13,24,27,42,52,68,81, 99,100,110,120,127, 93,104,108,129,130, 137,160 141,156,163,177, 190,207 No Connects - - June 1, 1996 (Version 1.0) 3-45