Floating Point To Integer Pipelined Converter ver 2.07 OVERVIEW The DFP2INT is the pipelined floating point to integer converter. The input and output numbers format is according to IEEE-754 standard. DFP2INT supports single precision real numbers and double word integers (4 Bytes). Convert operation is pipelined to 2 levels. Input data are fed every clock cycle. The first result appears after latency equal to 2 clock periods and next results are available each clock cycle. Full precision and accuracy are accomplished. DELIVERABLES APPLICATION Math coprocessors DSP algorithms Embedded arithmetic coprocessor Data processing & control KEY FEATURES Full IEEE-754 compliance Single precision real input numbers Double word output numbers(4 Bytes) Simple interface No programming required 2 levels pipelining Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurable All trademarks mentioned in this document are trademarks of their respective owners. Fully synthesizable, static synchronous design with no internal tri-states Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist One Year license for Encrypted Netlist only Unlimited Designs license for HDL Source Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs BLOCK DIAGRAM datai(31:0) Argument Checker Main FP Pipelined Unit Result Composer datao(31:0) ofo ufo ifo en rst clk Arguments Checker - performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit. Main FP Pipelined Unit - performs floating point to integer conversion. Gives the complex information about the results to Result Composer module. Result Composer - performs result rounding function, data alignment to IEEE-754 standard, and the final flags setting. SYMBOL datai(31:0) datao(31:0) ofo ufo ifo en rst clk PINS DESCRIPTION PIN TYPE DESCRIPTION clk Input Global system clock rst Input Global system reset en Input Enable computing datai[31:0] Input Data bus input datao[31:0] Output Data bus output ofo Output Overflow flag ufo Output Underflow flag ifo Output Invalid flag All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. PERFORMANCE CONTACTS The following table gives a survey about the Core area and performance in the LATTICE(R) devices after Place & Route (all key features have been included): For any modification or special request please contact to Digital Core Design or local distributors. Speed LUTs/PFUs Fmax grade ORCA 4 -3 418/63 75 MHz ispXPGA -4 369/114 83 MHz Core performance in LATTICE(R) devices Device Headquarters: Wroclawska 94 41-902 Bytom, POLAND @ddccdd..ppll e-mail: iinnffoo@ tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245,USA e-mail: iinnffooU USS@ @ddccdd..ppll tel. : +1 210 422 8268 fax : +1 210 679 7511 Distributors: MTC - Micro Tech Components GmbH AM Reitweg 15 89407 Dillingen, GERMANY MTTC Ciinnffoo@ @m mttcc..ddee e-mail : M tel. : +49 9071 7945-0 fax : +49 9071 7945-20 Territory: Germany, Austria, Switzerland All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.