SSM3J328R
2014-03-01
1
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSⅥ)
SSM3J328R
○ Power Management Switch Applications
• 1.5-V drive
• Low ON-resistance: RDS(ON) = 88.4mΩ (max) (@VGS = -1.5 V)
R
DS(ON) = 56.0mΩ (max) (@VGS = -1.8 V)
R
DS(ON) = 39.7mΩ (max) (@VGS = -2.5 V)
R
DS(ON) = 29.8mΩ (max) (@VGS = -4.5 V)
Absolute Maximum Ratings (Ta = 25°C)
Characteristic Symbol Rating Unit
Drain-source voltage VDSS -20 V
Gate-source voltage VGSS ± 8 V
DC ID (Note 1) -6.0
Drain current Pulse IDP (Note 1,2) -24.0 A
PD (Note 3) 1
Power dissipation t = 10s 2 W
Channel temperature Tch 150 °C
Storage temperature range Tstg −55 to 150 °C
Note: Using continuously under heavy loads (e.g. the application of high
temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: The channel temperature should not exceed 150°C during use.
Note 2: PW ≤ 10μs,Duty ≤ 1％
Note 3: Mounted on a FR4 board.
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2)
Marking Equivalent Circuit (Top view)
Unit: mm
0.17
+0.08
-0.07
2.9±0.2
0.95 0.95
0.42
+0.08
-0.05
1.8±0.1
2.4±0.1
12
3
A
0.05 M A
+0.08
-0.05
0.8
JEDEC ―
JEITA ―
TOSHIBA 2-3Z1A
Weight: 11 mg (typ.)
KFH
1 2
3
1 2
3
1: Gate
2: Source
3: Drain
SOT-23F
Start of commercial production
2010-08
SSM3J328R
2014-03-01
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Electrical Characteristics (Ta = 25°C)
Characteristic Symbol Test Conditions Min Typ. Max Unit
V (BR) DSS ID = -1 mA, VGS = 0 V -20 ⎯ ⎯ V
Drain-source breakdown voltage
V (BR) DSX ID = -1 mA, VGS = 5 V (Note 5) -15 ⎯ ⎯ V
Drain cut-off current IDSS V
DS = -20 V, VGS = 0 V ⎯ ⎯ -1 μA
Gate leakage current IGSS V
GS = ±8 V, VDS = 0 V ⎯ ⎯ ±1 μA
Gate threshold voltage Vth V
DS = -3 V, ID = -1 mA -0.3 ⎯ -1.0 V
Forward transfer admittance ⏐Yfs⏐ V
DS = -3 V, ID = -1.0 A (Note 4) 4.5 9.1 ⎯ S
ID = -3.0 A, VGS = -4.5 V (Note 4) ⎯ 24.9 29.8
ID = -2.5 A, VGS = -2.5 V (Note 4) ⎯ 31.1 39.7
ID = -1.5 A, VGS = -1.8 V (Note 4) ⎯ 38.8 56.0
Drain–source ON-resistance RDS (ON)
ID = -0.5 A, VGS = -1.5 V (Note 4) ⎯ 47.4 88.4
mΩ
Input capacitance Ciss ⎯ 840 ⎯
Output capacitance Coss ⎯ 118 ⎯
Reverse transfer capacitance Crss
VDS = -10 V, VGS = 0 V
f = 1 MHz ⎯ 99 ⎯
pF
Total gate charge Qg ⎯ 12.8 ⎯
Gate-source charge Qgs1 ⎯ 1.4 ⎯
Gate-drain charge Qgd
VDD = -10 V, IDS = -4.0 A,
VGS = -4.5 V ⎯ 3.0 ⎯
nC
Turn-on time ton ⎯ 32 ⎯
Switching time Turn-off time toff
VDD = -10 V, ID = -2.0 A
VGS = 0 to -2.5 V, RG = 4.7 Ω ⎯ 107 ⎯ ns
Drain-Source forward voltage VDSF I
D = 6.0 A, VGS = 0 V (Note 4) ⎯ 0.87 1.2 V
Note4: Pulse test
Note5: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the
drain-source breakdown voltage is lowered in this mode.
Switching Time Test Circuit
(a) Test Circuit
Notice on Usage
Let Vth be the voltage applied between gate and source that causes the drain current (ID) to be low (-1 mA for the
SSM3J328R). Then, for normal switching operation, VGS(on) must be higher than Vth, and VGS(off) must be lower than
Vth. This relationship can be expressed as: VGS(off) < Vth < VGS(on).
Take this into consideration when using the device.
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
Thermal resistance Rth (ch-a) and power dissipation PD vary depending on board material, board area, board thickness
and pad area. When using this device, please take heat dissipation into consideration.
VDD = -10 V
RG = 4.7 Ω
Duty ≤ 1%
VIN: tr, tf < 5 ns
Common Source
Ta = 25°C
IN
0
−2.5V
10 μs VDD
OUT
RG
RL
ton
10%
90%
−2.5 V
0 V
90%
10%
toff
trtf
VDS
(
ON
)
VDD
(c) VOUT
(b) VIN
SSM3J328R
2014-03-01
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0 -2 -4 -6
0
RDS (ON) – VGS
-8
60
− 25 °C
25 °C
140
Ta = 100 °C
120
80
40
20
ID =-0.5A
Common Source
Pulse test
100
ID – VGS
-100
-0.0001
0
-1
-10
-0.01
-0.1
-0.001
-2.0
−25 °C
Common Source
VDS = -3 V
Pulse test
Ta = 100 °C
25 °C
-0.5 -1.5 -1.0
RDS (ON) – Ta
120
0
−50
ID = -0.5 A / VGS = -1.5 V
0 50 150
20
40
60
80
100
-2.5 A / -2.5 V
-3.0 A / -4.5 V
-1.5 A / -1.8 V
140
Drain–source voltage VDS (V)
ID – VDS
Drain current ID (A)
0
-10
0 -0.2 -0.6 -0.8 -1
-6
-2
-4
Common Source
Ta = 25 °C
Pulse test
-1.8 V
-2.5 V
-0.4
VGS =-4.5 V
-8
RDS (ON) – VGS
RDS (ON) – ID
-1.5 V
0 -2 -4 -6
0-8
60
− 25 °C
25 °C
140
Ta = 100 °C
120
80
40
20
ID =-2.5A
Common Source
Pulse test
100
-8.00 -2.0 -4.0
0
-6.0
140
-1.5 V
-2.5 V
-1.8 V
120
100
80
40
20
60
-4.5 V
-10.0
100
Gate–source voltage VGS (V)
Drain current ID (A)
Gate–source voltage VGS (V)
Drain–source ON-resistance
RDS (ON) (mΩ)
Gate–source voltage VGS (V)
Drain–source ON-resistance
RDS (ON) (mΩ)
Drain current ID (A)
Drain–source ON-resistance
RDS (ON) (mΩ)
Ambient temperature Ta (°C)
Drain–source ON-resistance
RDS (ON) (mΩ)
Common Source
Ta = 25°C
Pulse test
Common Source
Pulse test
SSM3J328R
2014-03-01
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Capacitance C (pF) Switching time t (ns)
|Yfs| – ID
0.1
-100
1.0
10
100
-0.1 -1 -10
30
0.3
3.0
C – VDS
00
-2
10 20
-8
-6
-4
30
Common Source
ID = -4.0 A
Ta = 25 °C
Vth – Ta
-0.8
0
−50 0 150
-0.2
-0.4
-0.6
-1.0
50 100
VDD = -10 V
VDD = -16 V
t – ID IDR – VDS
100
0
1
10
0.01
0.1
0.001
0.2 0.6
0.4 1.0 0.8 1.2
Common Source
VGS = 0 V
Ta = 25 °C
Pulse test
G
D
S
IDR
100 °C
25 °C
−25 °C
Common Source
VDS = -3 V
Ta = 25 °C
Pluse test
-0.01
Common Source
VDS = -3 V
ID = -1 mA
10
-0.1 -1 -10 -100
1000
10000
3000
5000
300
500
100
50
30
Ciss
Crss
Coss
Common Source
Ta = 25 °C
f = 1 MHz
VGS = 0 V
1
-0.001
1000
-0.1
10000
-1 -10
100
tf
Common Source
VDD = -10 V
VGS = 0 to -2.5 V
Ta = 25 °C
RG = 4.7Ω
10
-0.01
toff
tr
ton
Ambient temperature Ta (°C)
Gate threshold voltage Vth (V)
Drain current ID (A)
Forward transfer admittance
⎪
Yfs
⎪
(S)
Drain–source voltage VDS (V) Total Gate Charge Qg (nC)
Gate–source voltage VGS (V)
Dynamic Input Characteristic
Drain current ID (A) Drain–source voltage VDS (V)
Drain reverse current IDR (A)
SSM3J328R
2014-03-01
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Pulse width tw (s)
Rth – tw
Transient thermal impedance Rth (°C/W )
0.001 10000.01 0.1 1 100
10
100
1000
1
10
Single pulse
a. Mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2)
b. Mounted on FR4 board
(25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 0.72 mm2×3)
b
a
Ambient temperature Ta (°C)
PD – Ta
Power dissipation PD (mW)
1600
0
400
120100 140
800
160 80 60 40 20 0 -20 -40
a
1200
a: Mounted on FR4 board
(25.4mm × 25.4mm × 1.6mm , Cu Pad : 645 mm2)
b: Mounted on FR4 board
(25.4mm × 25.4mm × 1.6mm , Cu Pad : 0.72 mm2 ×3)
b
SSM3J328R
2014-03-01
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RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
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responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
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