IN74AC323N - Integral

TECHNICAL DATA

401

8-Bit Bidirectional Universal

Shift Register with Parallel I/O

High-Speed Silicon-Gate CMOS

The IN74AC323 is identical in pinout to the LS/ALS323,

HC/HCT323. The device inputs are compatible with standard CMOS

outputs; with pullup resistors, they are compatible with LS/ALS

outputs.

The IN74AC323 features a multiplexed parallel input/output data

port to achieve full 8-bit handling in a 20 pin p ackage. Due to the large

output drive capability and the 3-state feature, this device is ideally

suited for interface with bus lines in a bus-oriented system.

Two Mode-Select inputs and two Output Enable inputs are used to

choose the mode of operation as listed in the Function Table.

Synchronous parallel loading is accomplished by taking both Mode-

Select lines, S1 and S2, high. This places the outputs in the high-

impedance state, which permits data applied to the data port to be

clocked into the register. Reading out of the register can be

accomplished when the outputs are enabled. The active-low

synchronous Reset overrides all other inputs.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA; 0.1 µA @ 25°C

• High Noise Immunity Characteristic of CMOS Devices

• Outputs Source / Si nk 24 mA

IN74AC323

ORDERING INFORMATION

IN74AC323N Plastic

IN74AC323DW SOIC

TA = -40° to 85° C for al l

packages

PIN ASSIGNMENT

LOGIC DIAGRAM

PIN 20=VCC

PIN 10 = GND

IN74AC323

402

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V

VIN DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V

VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V

IIN DC Input Current, per Pin ±20 mA

IOUT DC Outp ut Si nk/Source Current, per Pin ±50 mA

ICC DC Supply Current, VCC and GND Pins ±50 mA

PDPower Dissipation in Still Air, Plastic DIP+

SOIC Package+ 750

500 mW

Tstg Storage Temperature -65 to +150 °C

TLLead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package) 260 °C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

TJJunct ion Tempe rature ( PDIP) 140 °C

TAOperating Temperature, All Package Types -40 +85 °C

IOH Outp ut Current - Hi gh -24 mA

IOL Outp ut Curr ent - Low 24 mA

tr, tfInput Rise and Fall Time *

(except Schmitt Inputs) VCC =3.0 V

VCC =4.5 V

VCC =5.5 V

150

ns/V

* VIN from 30% to 70% VCC

Thi s device contains p rote ction c ircuitr y to guard a gainst damage due to hi gh static voltage s or electr ic

fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated

voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range

GND≤(VIN or VOUT)≤VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).

Unused outputs must be left open.

IN74AC323

403

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)

VCC Guaranteed Limits

Symbol Parameter Test Conditions V 25 °C-40

°C to

85°CUnit

VIH Minimum High-Level

Input Voltage VOUT=0.1 V or VCC-0.1 V 3.0

4.5

5.5

2.1

3.15

3.85

2.1

3.15

3.85

VIL Maxi mum L ow -

Level Input Voltage VOUT=0.1 V or VCC-0.1 V 3.0

4.5

5.5

0.9

1.35

1.65

0.9

1.35

1.65

VOH Minimum High-Level

Output Voltage IOUT ≤ -50 µA3.0

4.5

5.5

2.9

4.4

5.4

2.9

4.4

5.4

*VIN=VIH or VIL

IOH=-12 mA

IOH=-24 mA

3.0

4.5

5.5

2.56

3.86

4.86

2.46

3.76

4.76

VOL Maxi mum L ow-Level

Output Voltage IOUT ≤ 50 µA3.0

4.5

5.5

0.1

*VIN= VIH or VIL

IOL=12 mA

IOL=24 mA

3.0

4.5

5.5

0.36

0.44

IIN Maximum Input

Leakage Current VIN=VCC or GND 5.5 ±0.1 ±1.0 µA

IOZ Maximum Three-

State Leakage

Current

VIN (OE)= VIH or VIL

VIN =VCC or GND

VOUT =VCC or GND

5.5 ±0.6 ±6.0 µA

IOLD +Minimum Dynamic

Output Curre nt VOLD=1.65 V Max 5.5 75 mA

IOHD +Minimum Dynamic

Output Curre nt VOHD=3.85 V Min 5.5 -75 mA

ICC Maximum Quiescent

Supply Current

(per Package)

VIN=VCC or GND 5.5 8.0 80 µA

* All outputs loaded; thresholds on input associated with output under test.

+Maximum test duration 2.0 ms, one output loaded at a time.

Note: IIN and ICC @ 3.0 V are guaranteed to be less than or eq ual to the respective limit @ 5.5 V VCC

IN74AC323

404

AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=3.0 ns)

VCC*Guaranteed Limits

Symbol Parameter V 25 °C-40

°C to

85°CUnit

Min Max Min Max

fmax Maximum Clock Frequency (Figure 1) 3.3

5.0 90

130 80

105 MHz

tPLH Propagation Delay, Clock to QA’ or QH’

(Figure 1) 3.3

5.0 8.5

5.5 20.5

14.0 7.0

4.5 22.0

15.0 ns

tPHL Prop agatio n Delay, Clock to QA’ or Q H’

(Figure 1) 3.3

5.0 8.5

5.5 21.5

14.5 7.0

5.0 23.0

16.0 ns

tPLH Propagation Delay, Clock to QA thru QH

(Figure 1) 3.3

5.0 9.0

6.0 20.5

14.5 7.5

5.0 22.5

16.0 ns

tPHL Prop agatio n Delay, Clock to QA thru QH

(Figure 1) 3.3

5.0 10.0

6.5 23.0

16.0 8.5

6.0 24.5

17.5 ns

tPZH Propagation Delay , OE1, OE2 to QA thru QH

(Figure 3) 3.3

5.0 7.0

4.5 18.0

12.5 6.0

4.0 19.5

13.5 ns

tPZL Propagation Delay , OE1, OE2 to QA thru QH

(Figure 3) 3.3

5.0 7.0

5.0 18.0

12.5 6.0

4.0 20.5

14.0 ns

tPHZ Propagation Delay , OE1, OE2 to QA thru QH

(Figure 3) 3.3

5.0 6.5

3.5 18.5

14.0 5.5

3.0 19.5

15.0 ns

tPLZ Propagation Delay , OE1, OE2 to QA thru QH

(Figure 3) 3.3

5.0 5.5

3.5 17.0

12.5 4.5

2.0 19.0

13.5 ns

CIN Maximum Input Capacitance 5.0 4.5 4.5 pF

Typical @25°C,VCC=5.0 V

CPD Power Dissipation Capacitance 170 pF

*Voltage Range 3.3 V is 3.3 V ±0.3 V

Voltage Range 5.0 V is 5.0 V ±0.5 V

IN74AC323

405

TIMING REQUIREMENTS(CL=50pF,Input tr=tf=3.0 ns)

VCC*Guaranteed Limits

Symbol Parameter V 25 °C-40

°C to

85°CUnit

tsu Minimum Setup Time, Mode Select S1 or S2

to Clock (F igure 4) 3.3

5.0 8.0

5.0 8.5

5.5 ns

tsu Min imu m Setup Time, Data Input s PA thru PH

to Clock (F igure 4) 3.3

5.0 5.5

3.5 6.0

4.0 ns

tsu Min imu m Setup Time, Data Input s S A, SH to

Clock (Figur e 4) 3.3

5.0 6.5

4.0 7.0

4.5 ns

tsu Minimum Setup Time, Reset to Clock (Figure

2) 3.3

5.0 6.5

4.0 7.0

4.5 ns

thMin imu m Hold Time, Clock to Mode Sel ect

S1 or S2 (Figure 4) 3.3

5.0 0.5

1.0 0.5

1.0 ns

thMinimum Hold Time, Clock to Data Inputs PA

thru PH (Figure 4) 3.3

5.0 0

1.0 0

1.0 ns

thMinimum Hold Time, Clock to Data Inputs

SA, SH (Figure 4) 3.3

5.0 0

1.0 0.5

1.0 ns

thMinimum Hold T ime, Clock to Reset (Figure

2) 3.3

5.0 0

1.0 0

1.0 ns

twMinimum Pulse Wid t h, Clock (Fi gure 1 ) 3. 3

5.0 4.5

3.5 5.0

3.5 ns

twMinimum Pulse Width, Reset (Figur e 2) 3.3

5.0 4.5

3.5 5.0

3.5 ns

*Voltage Range 3.3 V is 3.3 V ±0.3 V

Voltage Range 5.0 V is 5.0 V ±0.5 V

IN74AC323

406

FUNCTION TABLE

Inputs Response

Mode Reset Mode

Select Output

Enables Clock Serial

Inputs PA/

PB/

PC/

PD/

PE/

PF/

PG/

PH/

QA’Q

H’

S2S1OE1 OE2 DADH

Reset L X L L L XXLLLLLLL L L L

L L X L L XXLLLLLLL L L L

LHHX X XXX Q

A through QH=Z L L

Shift

Right H L H H X D X Shift Right : QA through Q H=Z;

DA FA; FA FB; etc DQ

H L H X H D X Shift Right: QA through Q H=Z;

DA FA; FA FB; etc DQ

H L H L L D X Shift Ri ght: DA FA =QA;

FA FB =QB; etc DQ

Shift

Left H H L H X X D Shift Left: QA thr ough QH=Z;

DH FH; FH FG; etc QBD

H H L X H X D S hift Left : QA thro ugh QH=Z;

DH FH; FH FG; etc QBD

H H L L L X D S hift Left : DH FH =QH;

FH FG =QG; etc QBD

Parallel

Load H H H X X X X Parallel Load:PN FNPAPH

Hold H L L H X X X X Hold: QA through QH=Z; FN=FNPAPH

H L L X H X X X Hold: QA through QH=Z; FN=FNPAPH

H L L L L X X X Hold: QN =QHPAPH

Z = high impedance

D = data on serial input

F = flip-flop (see Logic Diagram)

When one or both output controls are high the eight input/output terminals are disabled to the high-impedance

state; however, sequential operation or clearing of the register is not affected.

IN74AC323

407

Figure 1. Switching Waveform Figure 2. Switching Waveform

Figure 3. Switching Waveform Figure 4. Switching Waveform

IN74AC323

408

EXPANDED LOGIC DIAGRAM