DS096 (v3.2) March 8, 2007 www.xilinx.com 1
Product Specification
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Features
• Optimized for 1.8V systems
- As fast as 7.1 ns pin-to-pin delays
- As low as 14 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 208-pin PQFP with 173 user I/O
- 256-ball FT (1.0mm) BGA with 212 user I/O
- 324-ball FG (1.0mm) BGA with 270 user I/O
- Pb-free available for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable signal control
- Four separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Advanced design security
- PLA architecture
· Superior pinout retention
· 100% product term routability across function
block
- Open-drain output option for Wired-OR and LED
drive
- Optional bus-hold, 3-state or weak pullup on
selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
- Hot Pluggable
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
Description
The CoolRunner-II 512-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
This device consists of thirty two Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.
DataGATE is a method to selectively disable inputs of the
CPLD that are not of interest during certain points in time.
0
XC2C512 CoolRunner-II CPLD
DS096 (v3.2) March 8, 2007 00Product Specification
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Product Specification
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By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Four I/O banks are available on the CoolRunner-II 512
macrocell device that permits easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
The CoolRunner-II 512 macrocell CPLD is I/O compatible
with various JEDEC I/O standards (see Table 1). This
device is also 1.5V I/O compatible with the use of
Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital, a design technique that makes use of CMOS
technology in both the fabrication and design methodology.
RealDigital design technology employs a cascade of CMOS
gates to implement sum of products instead of traditional
sense amplifier methodology. Due to this technology, Xilinx
CoolRunner-II CPLDs achieve both high-performance and
low power operation.
Supported I/O Standards
The CoolRunner-II 512 macrocell features LVCMOS,
LVTTL, SSTL, and HSTL I/O implementations. See Table 1
for I/O standard voltages. The LVTTL I/O standard is a gen-
eral purpose EIA/JEDEC standard for 3.3V applications that
use an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
Both HSTL and SSTL I/O standards make use of a VREF pin
for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V
I/O compatible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C512(1)
IOSTANDARD
Attribute
Output
VCCIO
Input
VCCIO
Input
VREF
Board
Termination
Voltage VTT
LVTTL 3.3 3.3 N/A N/A
LVCMOS33 3.3 3.3 N/A N/A
LVCMOS25 2.5 2.5 N/A N/A
LVCMOS18 1.8 1.8 N/A N/A
LVCMOS15(2) 1.5 1.5 N/A N/A
HSTL_1 1.5 1.5 0.75 0.75
SSTL2_1 2.5 2.5 1.25 1.25
SSTL3_1 3.3 3.3 1.5 1.5
(1) For information on Vref pins, see XAPP399.
(2) LVCMOS15 requires Schmitt-trigger inputs.
Figure 1: ICC vs Frequency
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1)
Frequency (MHz)
0 20 40 60 80 100 120 140 160 180
Typical ICC (mA) 0.025 17.22 34.37 52.04 69.44 86.85 105.13 122.68 140.23 157.78
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
Frequency (MHz)
DS096_01_030705
I
CC
(mA)
00
50
100
150
200
1801601208020 14060 10040
250
XC2C512 CoolRunner-II CPLD
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Product Specification
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Recommended Operating Conditions
DC Electrical Characteristics (Over Recommended Operating Conditions)
Absolute Maximum Ratings
Symbol Description Value Units
VCC Supply voltage relative to ground –0.5 to 2.0 V
VCCIO Supply voltage for output drivers –0.5 to 4.0 V
VJTAG(2) JTAG input voltage limits -0.5 to 4.0 V
VCCAUX JTAG input supply voltage -0.5 to 4.0 V
VIN(1) Input voltage relative to ground(1) –0.5 to 4.0 V
VTS(1) Voltage applied to 3-state output(1) –0.5 to 4.0 V
TSTG(3) Storage Temperature (ambient) –65 to +150 °C
TJJunction Temperature +150 °C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Valid over commercial temperature range.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free
packages, see XAPP427.
Symbol Parameter Min Max Units
VCC Supply voltage for internal logic and
input buffers
Commercial TA = 0°C to +70°C 1.7 1.9 V
Industrial TA = –40°C to +85°C 1.7 1.9 V
VCCIO Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V
Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V
Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V
Supply voltage for output drivers @ 1.5V operation 1.4 1.6 V
VCCAUX JTAG programming 1.7 3.6 V
Symbol Parameter Test Conditions Typical Max. Units
ICCSB Standby current Commercial VCC = 1.9V, VCCIO = 3.6V 50 240 μA
ICCSB Standby current Industrial VCC = 1.9V, VCCIO = 3.6V 150 400 μA
ICC (1) Dynamic current f = 1 MHz - 1 mA
f = 50 MHz - 55 mA
CJTAG JTAG input capacitance f = 1 MHz - 10 pF
CCLK Global clock input capacitance f = 1 MHz - 12 pF
CIO I/O capacitance f = 1 MHz - 10 pF
IIL(2) Input leakage current VIN = 0V or VCCIO to 3.9V - +/–1 μA
IIH(2) I/O High-Z leakage VIN = 0V or VCCIO to 3.9V - +/–1 μA
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block) tested at VCC= VCCIO = 1.9V.
2. See Quality and Reliability section of the CoolRunner-II family data sheet.
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Product Specification
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LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications
LVCMOS 2.5V DC Voltage Specifications
(1) The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up to 3.9V without
physical damage.
LVCMOS 1.8V DC Voltage Specifications
(1) The VIH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up to 3.9V without
physical damage.
LVCMOS 1.5V DC Voltage Specifications(1)
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage - 3.0 3.6 V
VIH High level input voltage - 2 3.9 V
VIL Low level input voltage - –0.3 0.8 V
VOH High level output voltage IOH = –8 mA, VCCIO = 3V VCCIO – 0.4V - V
IOH = –0.1 mA, VCCIO = 3V VCCIO – 0.2V - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 3V - 0.4 V
IOL = 0.1 mA, VCCIO = 3V - 0.2 V
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage - 2.3 2.7 V
VIH High level input voltage - 1.7 VCCIO + 0.3(1)) V
VIL Low level input voltage - –0.3 0.7 V
VOH High level output voltage IOH = –8 mA, VCCIO = 2.3V VCCIO – 0.4V - V
IOH = –0.1 mA, VCCIO = 2.3V VCCIO – 0.2V - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 2.3V - 0.4 V
IOL = 0.1mA, VCCIO = 2.3V - 0.2 V
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage - 1.7 1.9 V
VIH High level input voltage - 0.65 x VCCIO VCCIO + 0.3(1) V
VIL Low level input voltage - –0.3 0.35 x VCCIO V
VOH High level output voltage IOH = –8 mA, VCCIO = 1.7V VCCIO – 0.45 - V
IOH = –0.1 mA, VCCIO = 1.7V VCCIO – 0.2 - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 1.7V - 0.45 V
IOL = 0.1 mA, VCCIO = 1.7V - 0.2 V
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage - 1.4 1.6 V
VIH High level input voltage - 0.5 x VCCIO 0.8 x VCCIO V
VIL Low level input voltage - 0.2 x VCCIO 0.5 x VCCIO V
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Product Specification
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Schmitt Trigger Input DC Voltage Specifications
SSTL2-1 DC Voltage Specifications
SSTL3-1 DC Voltage Specifications
VOH High level output voltage IOH = –8 mA, VCCIO = 1.4V VCCIO – 0.45 - V
IOH = –0.1 mA, VCCIO = 1.4V VCCIO – 0.2 - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 1.4V - 0.4 V
IOL = 0.1 mA, VCCIO = 1.4V - 0.2 V
Notes:
1. Hysteresis used on 1.5V inputs.
Symbol Parameter Test Conditions Min. Max. Units
VCCIO Input source voltage 1.4 3.9 V
VT+ Input hysteresis threshold voltage 0.5 x VCCIO 0.8 x VCCIO V
VT- 0.2 x VCCIO 0.5 x VCCIO V
Symbol Parameter Test Conditions Min. Typ Max. Units
VCCIO Input source voltage 2.3 2.5 2.7 V
VREF(1) Input reference voltage 1.15 1.25 1.35 V
VTT(2) Termination voltage VREF – 0.04 1.25 VREF + 0.04 V
VIH High level input voltage VREF + 0.18 - 3.9 V
VIL Low level input voltage –0.3 - VREF – 0.18 V
VOH High level output voltage IOH = –8 mA, VCCIO = 2.3V VCCIO – 0.62 - - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 2.3V - - 0.54 V
Notes:
1. VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed ±2% VREF
2. VTT of transmitting device must track VREF of receiving devices
Symbol Parameter Test Conditions Min. Typ Max. Units
VCCIO Input source voltage 3.0 3.3 3.6 V
VREF(1) Input reference voltage 1.3 1.5 1.7 V
VTT(2) Termination voltage VREF – 0.05 1.5 VREF + 0.05 V
VIH High level input voltage VREF + 0.2 - VCCIO + 0.3 V
VIL Low level input voltage –0.3 - VREF – 0.2 V
VOH High level output voltage IOH = –8 mA, VCCIO = 3V VCCIO – 1.1 - - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 3V - - 0.7 V
Notes:
1. VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed ±2% VREF
2. VTT of transmitting device must track VREF of receiving devices
Symbol Parameter Test Conditions Min. Max. Units
XC2C512 CoolRunner-II CPLD
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Product Specification
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HSTL1 DC Voltage Specifications
Symbol Parameter Test Conditions Min. Typ Max. Units
VCCIO Input source voltage 1.4 1.5 1.6 V
VREF(1) Input reference voltage 0.68 0.75 0.90 V
VTT(2) Termination voltage - VCCIO x 0.5 - V
VIH High level input voltage VREF + 0.1 - 1.9 V
VIL Low level input voltage –0.3 - VREF – 0.1 V
VOH High level output voltage IOH = –8 mA, VCCIO = 1.7V VCCIO – 0.4 - - V
VOL Low level output voltage IOL = 8 mA, VCCIO = 1.7V - - 0.4 V
Notes:
1. VREF should track the variations in VCCIO, also peak-to-peak AC noise on VREF may not exceed ±2% VREF
2. VTT of transmitting device must track VREF of receiving devices
XC2C512 CoolRunner-II CPLD
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Product Specification
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AC Electrical Characteristics Over Recommended Operating Conditions
Symbol Parameter
-7 -10
UnitsMin. Max. Min. Max.
TPD1 Propagation delay (single p-term) - 7.1 - 9.2 ns
TPD2 Propagation delay (OR array) - 7.5 - 10.0 ns
TSUD Direct input register set-up time 3.4 - 4.0 - ns
TSU1 Setup time fast (single p-term) 2.6 - 3.1 - ns
TSU2 Setup time (OR array) 3.0 - 3.9 - ns
THDirect input register hold time 0 - 0 - ns
THP-term hold time 0 - 0 - ns
TCO Clock to output - 5.8 - 7.9 ns
FTOGGLE(1) Internal toggle rate - 250 - 166 MHz
FSYSTEM1(2) Maximum system frequency - 179 - 128 MHz
FSYSTEM2(2) Maximum system frequency - 167 - 116 MHz
FEXT1(3) Maximum external frequency - 119 - 91 MHz
FEXT2(3) Maximum external frequency - 114 - 85 MHz
TPSUD Direct input register p-term clock setup time 2.1 - 2.8 - ns
TPSU1 P-term clock setup time (single p-term) 1.1 - 1.7 - ns
TPSU2 P-term clock setup time (OR array) 1.5 - 2.5 - ns
TPHD Direct input register p-term clock hold time 0.1 - 0.4 - ns
TPH P-term clock hold 1.3 - 1.7 - ns
TPCO P-term clock to output - 7.3 - 9.3 ns
TOE/TOD Global OE to output enable/disable - 6.5 - 9.2 ns
TPOE/TPOD P-term OE to output enable/disable - 7.5 - 10.2 ns
TMOE/TMOD Macrocell driven OE to output enable/disable - 8.6 - 12.5 ns
TPAO P-term set/reset to output valid - 7.6 - 11.6 ns
TAO Global set/reset to output valid - 7.5 - 11.5 ns
TSUEC Register clock enable setup time 2.8 - 3.2 - ns
THEC Register clock enable hold time 0 - 0 - ns
TCW Global clock pulse width High or Low 2.0 - 3.0 - ns
TPCW P-term pulse width High or Low 7.5 - 10.0 - ns
TAPRPW Asynchronous preset/reset pulse width (High or Low) 7.5 - 10.0 - ns
TDGSU Set-up before DataGATE latch assertion 0.0 - 0.0 - ns
TDGH Hold to DataGATE latch assertion 4.0 - 6.0 - ns
TDGR DataGATE recovery to new data - 9.3 - 11.0 ns
TDGW DataGATE low pulse width 3.0 - 5.0 - ns
TCDRSU CDRST setup time before falling edge GCLK2 1.7 - 2.5 - ns
TCDRH Hold time CDRST after falling edge GCLK2 0 - 0 - ns
TCONFIG(4) Configuration time - 400 - 400 μs
Notes:
1. FTOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet for more
information).
2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with 16-bit Resetable binary counter through
one p-term per macrocell while FSYSTEM2 is through the OR array.
3. FEXT1(1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array
4. Typical configuration current during TCONFIG is approximately 15mA
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Product Specification
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Internal Timing Parameters(1)
Symbol Parameter(1)
-7 -10
UnitsMin. Max. Min. Max.
Buffer Delays
TIN Input buffer delay - 3.1 - 3.8 ns
TDIN Direct data register input delay - 4.4 - 5.5 ns
TGCK Global Clock buffer delay - 2.4 - 3.3 ns
TGSR Global set/reset buffer delay - 3.8 - 4.6 ns
TGTS Global 3-state buffer delay - 2.9 - 3.7 ns
TOUT Output buffer delay - 3.0 - 3.9 ns
TEN Output buffer enable/disable delay - 3.6 - 5.5 ns
P-term Delays
TCT Control term delay - 0.8 - 0.9 ns
TLOGI1 Single P-term delay adder - 0.5 - 0.8 ns
TLOGI2 Multiple P-term delay adder - 0.4 - 0.8 ns
Macrocell Delay
TPDI Input to output valid - 0.5 - 0.7 ns
TSUI Setup before clock 1.4 - 1.8 - ns
THI Hold after clock 0 - 0 - ns
TECSU Enable clock setup time 1.3 - 1.8 - ns
TECHO Enable clock hold time 0 - 0 - ns
TCOI Clock to output valid - 0.4 - 0.7 ns
TAOI Set/reset to output valid - 0.7 - 3.0 ns
TCDBL Clock doubler delay - 0 - 0 ns
Feedback Delays
TFFeedback delay - 3.3 - 4.5 ns
TOEM Macrocell to global OE delay - 2.2 - 3.0 ns
I/O Standard Time Adder Delays 1.5V CMOS
THYS15 Hysteresis input adder - 3.0 - 4.0 ns
TOUT15 Output adder - 0.8 - 1.0 ns
TSLEW15 Output slew rate adder - 3.0 - 4.0 ns
I/O Standard Time Adder Delays 1.8V CMOS
THYS18 Hysteresis input adder - 2.0 - 3.0 ns
TOUT18 Output adder - 0 - 0 ns
TSLEW18 Output slew rate adder - 2.5 - 4.0 ns
XC2C512 CoolRunner-II CPLD
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Product Specification
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Switching Characteristics AC Test Circuit
I/O Standard Time Adder Delays 2.5V CMOS
TIN25 Standard input adder - 0.6 - 1.0 ns
THYS25 Hysteresis input adder - 1.5 - 3.0 ns
TOUT25 Output adder - 0.8 - 2.0 ns
TSLEW25 Output slew rate adder - 3.0 - 4.0 ns
I/O Standard Time Adder Delays 3.3V CMOS/TTL
TIN33 Standard input adder - 0.5 - 2.0 ns
THYS33 Hysteresis input adder - 1.2 - 3.0 ns
TOUT33 Output adder - 1.2 - 3.0 ns
TSLEW33 Output slew rate adder - 3.0 - 4.0 ns
I/O Standard Time Adder Delays HSTL, SSTL
SSTL2-1 Input adder to TIN, TDIN, TGCK, TGSR,TGTS - 0.4 - 1.0 ns
Output adder to TOUT --0.5-0.0ns
SSTL3-1 Input adder to TIN, TDIN, TGCK, TGSR,TGTS - 0.6 - 1.0 ns
Output adder to TOUT - 0.0 - 0.0 ns
HSTL-1 Input adder to TIN, TDIN, TGCK, TGSR,TGTS - 0.8 - 1.0 ns
Output adder to TOUT - 0.0 - 0.0 ns
Notes:
1. 1.5 ns input pin signal rise/fall.
Internal Timing Parameters(1) (Continued)
Symbol Parameter(1)
-7 -10
UnitsMin. Max. Min. Max.
Figure 2: Derating Curve for TPD
Number of Outputs Switching
124816
6.0
6.4
6.8
VCC = VCCIO = 1.8V @ 25
o
C
TPD2 (ns)
7.0
6.6
6.2
DS096_02_022003
Figure 3: Load Circuit
R1
VCC
CL
R2
Device
Under Test
Output Type
LVTTL33
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
CL includes test fixtures and probe capacitance.
1.5 nsec maximum rise/fall times on inputs.
R1
268Ω
275Ω
188Ω
112.5Ω
150Ω
R2
235Ω
275Ω
188Ω
112.5Ω
150Ω
CL
35 pF
35 pF
35pF
35pF
35pF
DS_ACT_08_14_0
2
Test Point
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Product Specification
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Typical I/O Output Curves
The I/V curve illustrates the nominal amount of current that an I/O can source/sink at different voltage levels.
Figure 4: Typical I/V Curves for XC2C512
VO (Output Volts) XC512VoIo_all02200
3
IO (Output Current mA)
00
80
20
40
60
3.02.52.01.51.0.5 3
.5
3.3V
1.5V
1.8V
2.5V
IOL
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Product Specification
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11
Pin Descriptions
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
1(GTS0) 1 7 D4 C1 2
126B2C22
1(GTS3) 3 5 E3 B1 2
144C3B22
15----
16----
17----
18----
19----
110----
111----
112----
1(GTS2) 13 3 D3 D3 2
1142B3C32
1 15 208 B4 A1 2
1(GSR) 16 206 C4 A2 2
21-A1D22
228-D12
23-D2F42
24--F32
25----
26----
27----
28----
29----
210----
211----
212----
213-C2E22
2(GTS1) 14 9 E5 E1 2
2 15 10B1F2 2
21612E4G42
31205-B32
32-A2C42
33203-B42
34-C5C52
35202A3B52
36----
37----
38----
39----
310----
311----
312----
3 13 201 E7 A3 2
3 14 - A4 A4 2
3 15 200 C6 D6 2
3 16 199 B5 A5 2
41-C1G32
4214E2G22
43-F2G12
4415E6H42
45----
46----
47----
48----
49----
410----
411----
412----
413-F3H32
41416D1H22
41517G4H12
41618E1J42
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
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Product Specification
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5 1 198 D6 C6 2
5 2 197 A5 B6 2
5 3 196 E8 A6 2
5 4 195 B6 D7 2
5 5 194 C7 C7 2
56----
57----
58----
59----
510----
511----
512----
5 13 193 - B7 2
5 14 - A6 A7 2
5 15 192 D7 D8 2
516-B7C82
6119G3J32
6 2 20 G2 J2 2
6321-J12
64-F5K42
65----
66----
67----
68----
69----
610----
611----
612----
613--K32
614-F1K22
615--K12
616-G5L12
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
71191-B82
72-E9A82
73189A7D92
74188D8C92
75187B8B92
76----
77----
78----
79----
710----
711----
712----
713186C8A92
714185A8D102
7 15 184 E11 C10 2
7 16 183 E10 B10 2
81-H2L42
8222-L32
8 3 23 H4 L2 2
84--M12
85----
86----
87----
88----
89----
810----
811----
812----
813-G1M22
81425H3M32
815-H1M42
8 16 - H5 N1 2
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
XC2C512 CoolRunner-II CPLD
DS096 (v3.2) March 8, 2007 www.xilinx.com 13
Product Specification
R
9 1 - - AA2 1
9 2 50 N3 AB1 1
9 3 49 - AA1 1
9448-W41
95----
96----
97----
98----
99----
910----
911----
912----
913-R1Y31
91447N4Y21
915-N2W31
9(GCK1) 16 46 M3 Y1 1
10(CDRST) 1 51 P2 AB2 1
10 2 54 P4 Y4 1
10(GCK2) 3 55 P5 AB3 1
10 4 56 R2 AA4 1
10 5 - - - -
10 6 - - - -
10 7 - - - -
10 8 - - - -
10 9 - - - -
10 10 - - - -
10 11 - - - -
10 12 - - - -
10 13 57 T1 Y5 1
10(DGE) 14 58 T2 AA5 1
10 15 - - AB4 1
10 16 - N5 W6 1
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
11 1 45 P1 W2 1
11 2 - M4 W1 1
11(GCK0) 3 44 M2 V3 1
11 4 43 L3 U4 1
11 5 - - - -
11 6 - - - -
11 7 - - - -
11 8 - - - -
11 9 - - - -
11 10 - - - -
11 11 - - - -
11 12 - - - -
11 13 41 N1 V2 1
11 14 40 L4 V1 1
11 15 39 M1 U3 1
11 16 38 L5 U2 1
12 1 60 R4 AB5 1
12 2 61 M5 Y6 1
12 3 62 R5 AA6 1
12 4 63 R6 AB6 1
12 5 64 - W7 1
12 6 - - - -
12 7 - - - -
12 8 - - - -
12 9 - - - -
12 10 - - - -
12 11 - - - -
12 12 - - - -
12 13 65 N6 Y7 1
12 14 66 - AA7 1
12 15 67 R3 AB7 1
12 16 - - W8 1
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
XC2C512 CoolRunner-II CPLD
14 www.xilinx.com DS096 (v3.2) March 8, 2007
Product Specification
R
13 1 37 - U1 1
13 2 - K4 T4 1
13 3 36L2T3 1
13 4 35 - T2 1
13 5 - - - -
13 6 - - - -
13 7 - - - -
13 8 - - - -
13 9 - - - -
13 10 - - - -
13 11 - - - -
13 12 - - - -
13 13 - K3 T1 1
13 14 34 L1 R4 1
13 15 32 K5 R3 1
13 16 - K2 R2 1
14 1 - M6 Y8 1
14 2 - - AA8 1
14 3 69 T3 AB8 1
14 4 70 P6 W9 1
14 5 71 T4 Y9 1
14 6 - - - -
14 7 - - - -
14 8 - - - -
14 9 - - - -
14 10 - - - -
14 11 - - - -
14 12 - - - -
14 13 72 P7 AA9 1
14 14 - - AB9 1
14 15 73 T5 W10 1
14 16 - - Y10 1
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
15 1 31 J4 R1 1
15 2 - K1 P4 1
15 3 30 J3 P3 1
15 4 29 J2 P2 1
15 5 - - - -
15 6 - - - -
15 7 - - - -
15 8 - - - -
15 9 - - - -
15 10 - - - -
15 11 - - - -
15 12 - - - -
15 13 28 J5 P1 1
15 14 27 J1 N4 1
15 15 - - N3 1
15 16 - - N2 1
16 1 74 N7 AA10 1
16 2 - - AB10 1
16 3 75 R7 AB11 1
16 4 76 M7 W11 1
16 5 77 T6 AA11 1
16 6 - - - -
16 7 - - - -
16 8 - - - -
16 9 - - - -
16 10 - - - -
16 11 - - - -
16 12 - - - -
16 13 - - Y11 1
16 14 78 - AB12 1
16 15 - - AA12 1
16 16 - - Y12 1
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
XC2C512 CoolRunner-II CPLD
DS096 (v3.2) March 8, 2007 www.xilinx.com 15
Product Specification
R
17 1 161 A16 A21 4
17 2 162 B13 B20 4
17 3 163 - C19 4
17 4 164 - B19 4
17 5 165 B14 C18 4
17 6 - - - -
17 7 - - - -
17 8 - - - -
17 9 - - - -
17 10 - - - -
17 11 - - - -
17 12 - - - -
17 13 166 C13 B18 4
17 14 167 A15 A19 4
17 15 168 C12 D17 4
17 16 169 B12 A18 4
18 1 160 B15 A22 4
18 2 - C14 B21 4
18 3 - G11 B22 4
18 4 159 B16 C20 4
18 5 - - - -
18 6 - - - -
18 7 - - - -
18 8 - - - -
18 9 - - - -
18 10 - - - -
18 11 - - - -
18 12 - - - -
18 13 - - C21 4
18 14 - D14 D19 4
18 15 158 - D20 4
18 16 - C15 C22 4
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
19 1 170 D13 C17 4
19 2 171 A14 B17 4
19 3 173 E13 A17 4
19 4 - A13 D16 4
19 5 - C11 C16 4
19 6 - - - -
19 7 - - - -
19 8 - - - -
19 9 - - - -
19 10 - - - -
19 11 - - - -
19 12 - - - -
19 13 - A12 B16 4
19 14 - B11 A16 4
19 15 - D11 D15 4
19 16 - A11 C15 4
20 1 - G12 D21 4
20 2 - D15 D22 4
20 3 155 E14 E20 4
20 4 154 C16 F19 4
20 5 - - - -
20 6 - - - -
20 7 - - - -
20 8 - - - -
20 9 - - - -
20 10 - - - -
20 11 - - - -
20 12 - - - -
20 13 153 F14 E21 4
20 14 152 D16 E22 4
20 15 151 F13 F20 4
20 16 150 E15 F21 4
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
XC2C512 CoolRunner-II CPLD
16 www.xilinx.com DS096 (v3.2) March 8, 2007
Product Specification
R
21 1 - D10 B15 4
21 2 174 B10 A15 4
21 3 175 E12 D14 4
21 4 - F12 B14 4
21 5 178 - A14 4
21 6 - - - -
21 7 - - - -
21 8 - - - -
21 9 - - - -
21 10 - - - -
21 11 - - - -
21 12 - - - -
21 13 - - D13 4
21 14 - - C13 4
21 15 - - B13 4
21 16 - - A13 4
22 1 149 G13 F22 4
22 2 148 F15 G19 4
22 3 147 G14 G20 4
22 4 146 E16 G21 4
22 5 - - - -
22 6 - - - -
22 7 - - - -
22 8 - - - -
22 9 - - - -
22 10 - - - -
22 11 - - - -
22 12 - - - -
22 13 145 H12 G22 4
22 14 144 F16 H19 4
22 15 143 H16 H20 4
22 16 142 - H21 4
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
23 1 179 B9 A12 4
23 2 180 - D12 4
23 3 - C9 B12 4
23 4 182 - C12 4
23 5 - C10 A11 4
23 6 - - - -
23 7 - - - -
23 8 - - - -
23 9 - - - -
23 10 - - - -
23 11 - - - -
23 12 - - - -
23 13 - - B11 4
23 14 - A9 C11 4
23 15 - - D11 4
23 16 - D9 A10 4
24 1 140 G15 H22 4
24 2 139 H13 J19 4
24 3 138 G16 J20 4
24 4 137 H14 J21 4
24 5 - - - -
24 6 - - - -
24 7 - - - -
24 8 - - - -
24 9 - - - -
24 10 - - - -
24 11 - - - -
24 12 - - - -
24 13 136 H15 J22 4
24 14 135 J12 K19 4
24 15 134 K12 K20 4
24 16 - J16 K21 4
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
XC2C512 CoolRunner-II CPLD
DS096 (v3.2) March 8, 2007 www.xilinx.com 17
Product Specification
R
25 1 110 R16 W22 3
25 2 111 N15 V20 3
25 3 112 M15 V21 3
25 4 113 M13 U19 3
25 5 - - - -
25 6 - - - -
25 7 - - - -
25 8 - - - -
25 9 - - - -
25 10 - - - -
25 11 - - - -
25 12 - - - -
25 13 114 P16 V22 3
25 14 115 N16 U20 3
25 15 116 L14 U21 3
25 16 117 M14 U22 3
26 1 109 N14 Y22 3
26 2 108 T16 W21 3
26 3 107 R15 W20 3
26 4 106 P15 Y21 3
26 5 - P14 Y20 3
26 6 - - - -
26 7 - - - -
26 8 - - - -
26 9 - - - -
26 10 - - - -
26 11 - - - -
26 12 - - - -
26 13 103 P13 AA22 3
26 14 102 R13 AB22 3
26 15 101 N13 AA21 3
26 16 100 R14 AB21 3
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
27 1 118 L15 T19 3
27 2 - L13 T20 3
27 3 119 M12 T21 3
27 4 120 M16 T22 3
27 5 - - - -
27 6 - - - -
27 7 - - - -
27 8 - - - -
27 9 - - - -
27 10 - - - -
27 11 - - - -
27 12 - - - -
27 13 - K14 R19 3
27 14 - - R20 3
27 15 121 - R21 3
27 16 - - R22 3
28 1 99 T15 W19 3
28 2 97 R12 AA20 3
28 3 95 T14 Y18 3
28 4 - N11 AA19 3
28 5 - P11 W17 3
28 6 - - - -
28 7 - - - -
28 8 - - - -
28 9 - - - -
28 10 - - - -
28 11 - - - -
28 12 - - - -
28 13 - M11 Y17 3
28 14 - T13 AA18 3
28 15 - N10 AB18 3
28 16 - - AA17 3
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
XC2C512 CoolRunner-II CPLD
18 www.xilinx.com DS096 (v3.2) March 8, 2007
Product Specification
R
29 1 - L16 P19 3
29 2 - - P20 3
29 3 122 - P21 3
29 4 123 - P22 3
29 5 - - - -
29 6 - - - -
29 7 - - - -
29 8 - - - -
29 9 - - - -
29 10 - - - -
29 11 - - - -
29 12 - - - -
29 13 - - N19 3
29 14 125 K15 N21 3
29 15 - L12 N22 3
29 16 - - M22 3
30 1 - - AB17 3
30 2 91 T12 W16 3
30 3 90 P10 Y16 3
30 4 89 T11 AA16 3
30 5 - R10 AB16 3
30 6 - - - -
30 7 - - - -
30 8 - - - -
30 9 - - - -
30 10 - - - -
30 11 - - - -
30 12 - - - -
30 13 88 M10 W15 3
30 14 87 T10 Y15 3
30 15 - M9 AA15 3
30 16 86 R9 AB15 3
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
31 1 126 K16 M19 3
31 2 - - M20 3
31 3 127 - M21 3
31 4 128 J14 L22 3
31 5 - - - -
31 6 - - - -
31 7 - - - -
31 8 - - - -
31 9 - - - -
31 10 - - - -
31 11 - - - -
31 12 - - - -
31 13 - - L21 3
31 14 - J15 L20 3
31 15 - - L19 3
31 16 131 J13 K22 3
32 1 85 P9 W14 3
32 2 84 N9 Y14 3
32 3 - T9 AA14 3
32 4 83 M8 AB14 3
32 5 - T8 W13 3
32 6 - - - -
32 7 - - - -
32 8 - - - -
32 9 - - - -
32 10 - - - -
32 11 - - - -
32 12 - - - -
32 13 82 P8 Y13 3
32 14 80 R8 AA13 3
32 15 - T7 AB13 3
32 16 - N8 W12 3
Notes:
1. GTS = global output enable, GSR = global reset/set, GCK =
global clock, CDRST = clock divide reset, DGE = DataGATE
enable.
2. GCK, GSR, and GTS pins can also be used for general
purpose I/O.
Pin Descriptions (Continued)
Function
Block
Macro-
cell PQ208 FT256 FG324
I/O
Bank
XC2C512 CoolRunner-II CPLD
DS096 (v3.2) March 8, 2007 www.xilinx.com 19
Product Specification
R
XC2C512 JTAG, Power/Ground, No Connect Pins and Total User I/O
Device Part Marking
Figure 5: Sample Package with Part Marking
Pin Type PQ208 FT256 FG324
TCK 98 P12 Y19
TDI 94 R11 AB19
TDO 176 A10 C14
TMS 96 N12 AB20
VCCAUX (JTAG supply
voltage)
11 F4 F1
Power internal (VCC) 1, 53, 124 P3, K13, D12, D5 E3, AA3, N20, A20, D4
Power Bank 1 I/O (VCCIO1) 33,59,79 J6, K6, L7, L8 M9, N9, P10, P11
Power Bank 2 I/O (VCCIO2) 26, 204 F7, F8, G6, H6 J10,J11, K9, L9
Power Bank 3 I/O (VCCIO3) 92, 105, 132 J11, K11, L9, L10 M14, N14, P12, P13
Power Bank 4 I/O (VCCIO4) 133, 157, 172, 181 F9, F10, H11 J12, J13, K14, L14
Ground 13, 24, 42, 52, 68, 81,
93, 104, 129, 130, 141,
156, 177, 190, 207
F6, F11, G7, G8, G9, G10,
H7, H8, H9, H10, J7, J8, J9,
J10, K7, K8, K9, K10, L6, L11
D5, D18, E4, E19, J9, J14, K10,
K11, K12, K13, L10, L11, L12,
L13, M10, M11, M12, M13, N10,
N11, N12, N13, P9, P14, V4,
V19, W5, W18
No connects - - -
Total user I/O (includes dual
function pins)
173 212 270
XC2Cxxx
TQ144
7C
Device Type
Package
Speed
Operating Range
This line not
related to device
part number
R
XC2C512 CoolRunner-II CPLD
20 www.xilinx.com DS096 (v3.2) March 8, 2007
Product Specification
R
Ordering Information
Part Number
Pin/Ball
Spacing
θJA
(C/Watt)
θJC
(C/Watt) Package Type
Package Body
Dimensions I/O
Commercial
(C)
Industrial
(I)(1)
XC2C512-7PQ208C 0.5mm 35.1 7.2 Plastic Quad Flat
Pack
28mm x 28mm 173 C
XC2C512-10PQ208C 0.5mm 35.1 7.2 Plastic Quad Flat
Pack
28mm x 28mm 173 C
XC2C512-7FT256C 1.0mm 32.2 4.9 Fine Pitch Thin BGA 17mm x 17mm 212 C
XC2C512-7FT256I 1.0mm 32.2 4.9 Fine Pitch Thin BGA 17mm x 17mm 212 I
XC2C512-10FT256C 1.0mm 32.2 4.9 Fine Pitch Thin BGA 17mm x 17mm 212 C
XC2C512-7FG324C 1.0mm 39.1 5.0 Fine Pitch BGA 23mm x 23mm 270 C
XC2C512-10FG324C 1.0mm 39.1 5.0 Fine Pitch BGA 23mm x 23mm 270 C
XC2C512-7PQG208C 0.5mm 35.1 7.2 Plastic Quad Flat
Pack; Pb-free
28mm x 28mm 173 C
XC2C512-10PQG208C 0.5mm 35.1 7.2 Plastic Quad Flat
Pack; Pb-free
28mm x 28mm 173 C
XC2C512-7FTG256C 1.0mm 32.2 4.9 Fine Pitch Thin BGA;
Pb-free
17mm x 17mm 212 C
XC2C512-7FTG256I 1.0mm 32.2 4.9 Fine Pitch Thin BGA;
Pb-free
17mm x 17mm 212 I
XC2C512-10FTG256C 1.0mm 32.2 4.9 Fine Pitch Thin BGA;
Pb-free
17mm x 17mm 212 C
XC2C512-7FGG324C 1.0mm 39.1 5.0 Fine Pitch BGA;
Pb-free
23mm x 23mm 270 C
XC2C512-10FGG324C 1.0mm 39.1 5.0 Fine Pitch BGA;
Pb-free
23mm x 23mm 270 C
XC2C512-10PQ208I 0.5mm 35.1 7.2 Plastic Quad Flat
Pack
28mm x 28mm 173 I
XC2C512-10FT256I 1.0mm 32.2 4.9 Fine Pitch Thin BGA 17mm x 17mm 212 I
XC2C512-10FG324I 1.0mm 39.1 5.0 Fine Pitch BGA 23mm x 23mm 270 I
XC2C512-10PQG208I 0.5mm 35.1 7.2 Plastic Quad Flat
Pack; Pb-free
28mm x 28mm 173 I
XC2C512-10FTG256I 1.0mm 32.2 4.9 Fine Pitch Thin BGA;
Pb-free
17mm x 17mm 212 I
XC2C512-10FGG324I 1.0mm 39.1 5.0 Fine Pitch BGA;
Pb-free
23mm x 23mm 270 I
Notes:
1. C = Commercial (TA = 0°C to +70° C); I = Industrial (TA = –40°C to +85°C)..
Standard Example: XC2C128
Device
Speed Grade
Package Type
Number of Pins
Temperature Range
-7 TQ C144 Pb-Free Example:
XC2C128 TQ G 144 C
Device
Speed Grade
Package Type
Pb-Free
Number of Pins
-7
Temperature Range
XC2C512 CoolRunner-II CPLD
DS096 (v3.2) March 8, 2007 www.xilinx.com 21
Product Specification
R
Figure 6: PQ208 Plastic Quad Flat Pack
VCC
I/O
I/O(1)
I/O
I/O(1)
I/O
I/O(1)
I/O
I/O(1)
I/O
VAUX
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
V
CCIO2
I/O
I/O
I/O
I/O
I/O
I/O
V
CCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O(2)
I/O
I/O(2)
I/O
I/O
I/O
I/O
I/O(4)
GND
PQ208
Top View
VCC
I/O
I/O(2)
I/O
I/O
I/O(5)
VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO1
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO3
GND
TDI
I/O
TMS
I/O
TCK
I/O
I/O
I/O
I/O
I/O
GND
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(4) - Clock Divide Reset
(5) - DataGATE Enable
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
4
VCCIO
3
I/O
GND
GND
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
3
I/O
GND
I/O(3)
I/O
VCCIO
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
4
I/O
I/O
I/O
GND
TDO
I/O
I/O
I/O
VCCIO
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
XC2C512 CoolRunner-II CPLD
22 www.xilinx.com DS096 (v3.2) March 8, 2007
Product Specification
R
Figure 7: FT256 Fine Pitch Thin BGA
FT256 Bottom View
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
I/O TDO I/O
I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O
I/O I/O I/O
I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O
I/O I/O I/O(3)
I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O
I/O I/O I/O(1)
I/OI/O VCC I/O I/O I/O I/O I/O VCC I/O(1) I/O I/O
I/O
I/O I/O I/O
I/OI/O I/O I/O I/O I/O I/O I/O I/O(1) I/O(1) I/O I/O
I/O
I/O VCCIO4 VAUX
I/OI/O I/O GND VCCIO4 VCCIO2 VCCIO2 GND I/O I/O I/O I/O
I/O
I/O GND I/O
I/OI/O I/O I/O GND GND GND VCCIO2 I/O I/O I/O I/O
I/O
I/O GND I/O
I/OI/O I/O VCCIO4 GND GND GND VCCIO2 I/O I/O I/O I/O
I/O
I/O GND I/O
I/OI/O I/O VCCIO3 GND GND GND VCCIO1 I/O I/O I/O I/O
I/O
I/O GND I/O
VCCI/O I/O VCCIO3 GND GND GND VCCIO1 I/O I/O I/O I/O
I/O
I/O VCCIO3 I/O
I/OI/O I/O GND VCCIO3 VCCIO1 VCCIO1 GND I/O I/O I/O I/O
I/O
I/O I/O I/O
I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O(2) I/O(2) I/O
I/O
I/O I/O I/O
I/OI/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O
I/O I/O I/O
I/OI/O TCK I/O I/O I/O I/O I/O I/O(2) VCC I/O(4) I/O
I/O
I/O I/O I/O
I/OI/O I/O TDI I/O I/O I/O I/O I/O I/O I/O I/O
I/O
I/O I/O I/O
I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(5) I/O
I/O
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(4) - Clock Divide Reset
(5) - DataGATE Enable
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
XC2C512 CoolRunner-II CPLD
DS096 (v3.2) March 8, 2007 www.xilinx.com 23
Product Specification
R
Figure 8: FG324 Fine Pitch BGA
FG324 Bottom View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
A
A
A
B
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
I/O I/O I/O
I/OVCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O
I/O I/O I/O
I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O
I/O I/O I/O
I/OI/O I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O
I/O
I/O I/O I/O
I/OI/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O
I/O GNDI/O
I/O
I/O I/OI/O
I/O
I/O I/OI/O
I/O
I/O I/OI/O
I/O
I/O VCCIO2
I/OI/O GND VCCIO4 VCCIO4 VCCIO2 GND
I/O
I/O GND
I/OI/O VCCIO4 GND GND GND VCCIO2
I/O
I/O GND
I/OI/O VCCIO4 GND GND GND VCCIO2
I/O
I/O GND
I/OI/O VCCIO3 GND GND GND VCCIO1
I/O
I/O GND
I/OVCC VCCIO3 GND GND GND VCCIO1
I/O
I/O VCCIO1
I/OI/O GND VCCIO3 VCCIO3 VCCIO1 GND
I/O
I/O I/OI/O
I/O
I/O I/OI/O
I/O
(1) - Global Output Enable
(2) - Global Clock
(3) - Global Set/Reset
(4) - Clock Divide Reset
(5) - DataGATE Enable
GND VCC I/O I/O(1)
I/O I/O I/O VAUX
I/O I/O I/O I/O
I/O I/O I/O I/O
I/O I/O I/O I/O
I/O I/O I/O I/O
I/O I/O I/O I/O
I/O I/O I/O I/O
I/O I/O I/O I/O
I/O I/O I/O I/O
I/O I/O I/O I/O
I/O I/O I/O I/O
I/O I/OI/O
I/O I/O I/O I/O I/O
I/O GNDI/O
I/O GND I/O(2) I/O I/O
I/O I/O I/O
I/OI/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O
I/O GND I/O I/O I/O
I/O I/O I/O
TCKI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O
I/O I/O I/O I/O I/O(2)
I/O I/O I/O
I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O
I/O I/O(5) VCC I/O I/O
I/O I/O I/O
TDITMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O
I/O I/O I/O(2) I/O(4) I/O
VCC
I/O GND I/O(1) I/O I/O
I/O
I/O I/O I/O I/O I/O(1)
I/O
I/O I/O I/O I/O I/O(1)
I/O
I/O I/O I/O I/O(3) I/O
XC2C512 CoolRunner-II CPLD
24 www.xilinx.com DS096 (v3.2) March 8, 2007
Product Specification
R
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Additional Information
Additional information is available for the following CoolRunner-II topics:
• XAPP784: Bulletproof CPLD Design Practices
• XAPP375: Timing Model
• XAPP376: Logic Engine
• XAPP378: Advanced Features
• XAPP382: I/O Characteristics
• XAPP389: Powering CoolRunner-II
• XAPP399: Assigning VREF Pins
To access these and all application notes with their associ-
ated reference designs, click the following link and scroll
down the page until you find the document you want:
CoolRunner-II Data Sheets and Application Notes
Device Packages
Revision History
The following table shows the revision history for this document.
Date Version Revision
7/19/02 1.0 Initial Xilinx release.
3/15/03 2.0 Added characterization data.
11/25/03 2.1 Fixed two typos.
1/26/04 2.2 Updated Tsol; added links to Data Sheets and Application Notes.
8/03/04 2.3 Pb-free documentation
10/01/04 2.4 Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.
01/30/05 2.5 Change to ICCSB MAX for Commercial and Industrial.
03/07/05 2.6 Removed -6 speed grade. Modified Table 1, IOSTANDARDs.
03/20/06 3.0 Change to Product Specification. Add warranty Disclaimer. Add note to Pin Descriptions
that GCK, GSR, and GTS pins can also be used for general purpose I/O.
02/15/07 3.1 Corrections to timing parameters tDIN, tSUD, tPSUD, tPHD, tPH, tSLEW18, tIN (HSTL),
tOUT(SSTL3), and tTin (SSTL3) for -6 speed grade. Corrections to tDIN, tSUD, tCO, tPSUD,
tPHD, and tPH for the -7 speed grade. Values now match the software. There were no
changes to silicon or characterization. Added XC2C512-7FT256I and XC2C512-7FTG236I
packages. Change to VIH specification for 2.5V and 1.8V LVCMOS.
03/08/07 3.2 Fixed typo in note for VIL for LVCMOS18; removed note for VIL for LVCMOS33.
