General Description
The MAX1214 is a monolithic, 12-bit, 210Msps analog-
to-digital converter (ADC) optimized for outstanding
dynamic performance at high-IF frequencies up to
300MHz. The product operates with conversion rates
up to 210Msps while consuming only 820mW.
At 210Msps and an input frequency up to 250MHz, the
MAX1214 achieves a spurious-free dynamic range
(SFDR) of 77.2dBc. Its excellent signal-to-noise ratio
(SNR) of 66dB at 10MHz remains flat (within 2dB) for
input tones up to 300MHz. This ADC yields an excellent
low noise floor of -67.6dBFS, which makes it ideal for
wideband applications such as cable-head end
receivers and power-amplifier predistortion in cellular
base-station transceivers.
The MAX1214 requires a single 1.8V supply. The analog
input is designed for either differential or single-ended
operation and can be AC- or DC-coupled. The ADC also
features a selectable on-chip divide-by-2 clock circuit,
which allows the user to apply clock frequencies as high
as 340MHz. This helps to reduce the phase noise of the
input clock source. A low-voltage differential signal
(LVDS) sampling clock is recommended for best perfor-
mance. The converter’s digital outputs are LVDS com-
patible and the data format can be selected to be either
two’s complement or offset binary.
The MAX1214 is available in a 68-pin QFN package
with exposed paddle (EP) and is specified over the
industrial (-40°C to +85°C) temperature range.
See the Pin-Compatible Versions table for a complete
selection of 8-bit, 10-bit, and 12-bit high-speed DACs in
this family (with and without input buffers).
Applications
Base-Station Power-Amplifier Linearization
Cable-Head End Receivers
Wireless and Wired Broadband Communication
Communications Test Equipment
Radar and Satellite Subsystems
Features
♦210Msps Conversion Rate
♦Low Noise Floor of -67.6dBFS
♦Excellent Low-Noise Characteristics
SNR = 65.6dB at fIN = 100MHz
SNR = 65dB at fIN = 250MHz
♦Excellent Dynamic Range
SFDR = 74.2dBc at fIN = 100MHz
SFDR = 77.2dBc at fIN = 250MHz
♦59.5dB NPR for fNOTCH = 28.8MHz and a Noise
Bandwidth of 50MHz
♦Single 1.8V Supply
♦820mW Power Dissipation at fSAMPLE = 210MHz
and fIN = 100MHz
♦On-Chip Track-and-Hold Amplifier
♦Internal 1.23V-Bandgap Reference
♦On-Chip Selectable Divide-by-2 Clock Input
♦LVDS Digital Outputs with Data Clock Output
♦MAX1214 EV Kit Available
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
________________________________________________________________ Maxim Integrated Products 1
PART TEMP RANGE PIN-PACKAGE
MAX1214EGK-D -40°C to +85°C 68 QFN-EP*
MAX1214EGK+D -40°C to +85°C 68 QFN-EP*
Ordering Information
19-3652; Rev 1; 9/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*EP = Exposed paddle.
+Denotes lead-free package.
D= Dry pack.
EVALUATION KIT
AVAILABLE
Pin-Compatible Versions
PART RESOLUTION
(BITS)
SPEED GRADE
(Msps)
ON-CHIP
BUFFER
MAX1121 8 250 Yes
MAX1122 10 170 Yes
MAX1123 10 210 Yes
MAX1124 10 250 Yes
MAX1213 12 170 Yes
MAX1215 12 250 Yes
MAX1213N 12 170 No
MAX1214N 12 210 No
MAX1215N 12 250 No
Pin Configuration appears at end of data sheet.
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL = 100Ω±1%, TA= TMIN to TMAX, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCC to AGND ......................................................-0.3V to +2.1V
OVCC to OGND .....................................................-0.3V to +2.1V
AVCC to OVCC .......................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
INP, INN to AGND....................................-0.3V to (AVCC + 0.3V)
All Digital Inputs to AGND........................-0.3V to (AVCC + 0.3V)
REFIO, REFADJ to AGND ........................-0.3V to (AVCC + 0.3V)
All Digital Outputs to OGND ....................-0.3V to (OVCC + 0.3V)
Continuous Power Dissipation (TA= +70°C, multi-layer board)
68-Pin QFN-EP (derate 41.7mW/°C
above +70°C)........................................................3333mW/°C
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Maximum Current into Any Pin .........................................±50mA
Lead Temperature (soldering,10s) ..................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity (Note 2) INL fIN = 10MHz, TA = +25°C -1.75 ±0.75 +1.75 LSB
Differential Nonlinearity (Note 2) DNL TA = +25°C, no missing codes -1 ±0.4 +1 LSB
Transfer Curve Offset VOS TA = +25°C (Note 2) -3.5 +3.5 mV
Offset Temperature Drift 40 µV/°C
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range VFS TA = +25°C (Note 2) 1320 1454 1590 mVP-P
Full-Scale Range Temperature
Drift 130 ppm/°C
Common-Mode Input Range VCM Internally self-biased 1.365 ±0.15 V
Input Capacitance CIN 2.5 pF
Differential Input Resistance RIN 3.0 4.2 6.3 kΩ
Full-Power Analog Bandwidth FPBW 700 MHz
REFERENCE (REFIO, REFADJ)
Reference Output Voltage VREFIO TA = +25°C, REFADJ = AGND 1.18 1.23 1.30 V
Reference Temperature Drift 90 ppm/°C
REFADJ Input High Voltage VREFADJ Used to disable the internal reference AVCC - 0.3 V
SAMPLING CHARACTERISTICS
Maximum Sampling Rate fSAMPLE 210 MHz
Minimum Sampling Rate fSAMPLE 20 MHz
Clock Duty Cycle Set by clock-management circuit 40 to 60 %
Aperture Delay tAD Figures 4, 11 620 ps
Aperture Jitter tAJ Figure 11 0.2 psRMS
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL = 100Ω±1%, TA= TMIN to TMAX, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude (Note 3) 200 500 mVP-P
Clock Input Common-Mode
Voltage Range Internally self-biased 1.15 ±0.25 V
Clock Differential Input
Resistance RCLK 11
±25% kΩ
Clock Differential Input
Capacitance CCLK 5pF
DYNAMIC CHARACTERISTICS (at -1dBFS)
fIN = 10MHz, TA ≥ +25°C6466
fIN = 100MHz, TA ≥ +25°C 64 65.6
fIN = 200MHz 65.3
Signal-to-Noise
Ratio SNR
fIN = 250MHz 65
dB
fIN = 10MHz, TA ≥ +25°C 64 65.8
fIN = 100MHz, TA ≥ +25°C 63.3 65
fIN = 200MHz 63.7
Signal-to-Noise
and Distortion SINAD
fIN = 250MHz 64.4
dB
fIN = 10MHz, TA ≥ +25°C 73 80.7
fIN = 100MHz, TA ≥ +25°C 68 74.2
fIN = 200MHz 69.1
Spurious-Free
Dynamic Range SFDR
fIN = 250MHz 77.2
dBc
fIN = 10MHz, TA ≥ +25°C -82 -73
fIN = 100MHz, TA ≥ +25°C -74.2 -68
fIN = 200MHz -73.5
Worst Harmonics
(HD2 or HD3)
fIN = 250MHz -72.5
dBc
Two-Tone Intermodulation
Distortion TTIMD fIN1 = 99MHz at -7dBFS,
fIN2 = 101MHz at -7dBFS -74 dBc
Noise-Power Ratio NPR fNOTCH = 28.8MHz ±1MHz,
noise BW = 50MHz, AIN = -9.1dBFS 59.5 dB
LVDS DIGITAL OUTPUTS (D0P/N–D11P/N, ORP/N)
Differential Output Voltage |VOD|R
L = 100Ω ±1% 250 400 mV
Output Offset Voltage OVOS RL = 100Ω ±1% 1.125 1.310 V
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
internal reference, digital output pins differential RL = 100Ω±1%, TA= TMIN to TMAX, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input-Voltage Low VIL 0.2 x AVCC V
Digital Input-Voltage High VIH 0.8 x AVCC V
TIMING CHARACTERISTICS
CLK-to-Data Propagation Delay tPDL Figure 4 1.77 ns
CLK-to-DCLK Propagation Delay tCPDL Figure 4 4.31 ns
DCLK-to-Data Propagation Delay tPDL - tCPDL Figure 4 (Note 3) 2.09 2.54 2.91 ns
LVDS Output Rise Time tRISE 20% to 80%, CL = 5pF 460 ps
LVDS Output Fall Time tFALL 20% to 80%, CL = 5pF 460 ps
Output Data Pipeline Delay tLATENCY Figure 4 11 Clock
cycles
POWER REQUIREMENTS
Analog Supply Voltage Range AVCC 1.70 1.80 1.90 V
Digital Supply Voltage Range OVCC 1.70 1.80 1.90 V
Analog Supply Current IAVCC fIN = 100MHz 390 460 mA
Digital Supply Current IOVCC fIN = 100MHz 64 75 mA
Analog Power Dissipation PDISS fIN = 100MHz 820 963 mW
Offset 1.8 mV/V
Power-Supply Rejection Ratio
(Note 4) PSRR Gain 1.5 %FS/V
Note 1: ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: Static linearity and offset parameters are based on the end-point fit method. The full-scale range (FSR) is defined as 4095 x
slope of the line.
Note 3: Parameter guaranteed by design and characterization: TA= TMIN to TMAX.
Note 4: PSRR is measured with both analog and digital supplies connected to the same potential.
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
_______________________________________________________________________________________ 5
FFT PLOT
(8192-POINT DATA RECORD)
MAX1214 toc01
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
fSAMPLE = 209.99946MHz
fIN = 12.79172MHz
AIN = -1.083dBFS
SNR = 66.6dB
SINAD = 66.4dB
THD = -79.3dBc
SFDR = 82.3dB
HD2 = -90.8dBc
HD3 = -82.3dBc
HD3
HD2
0 102030405060708090100
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(8192-POINT DATA RECORD)
MAX1214 toc02
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
fSAMPLE = 209.99946MHz
fIN = 65.08650MHz
AIN = -1.119dBFS
SNR = 66.5dB
SINAD = 66.5dB
THD = -75.2dBc
SFDR = 73.1dBc
HD2 = -87.9dBc
HD3 = -73.1dBc
HD2
HD3
0 102030405060708090100
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(8192-POINT DATA RECORD)
MAX1214 toc03
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
fSAMPLE = 209.99946MHz
fIN = 199.77122MHz
AIN = -1.030dBFS
SNR = 65.3dB
SINAD = 63.7dB
THD = -68.7dBc
SFDR = 69.1dBc
HD2 = -83.7dBc
HD3 = -69.1dBc
HD3
HD2
0 102030405060708090100
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(8192-POINT DATA RECORD)
MAX1214 toc04
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
fSAMPLE = 209.99946MHz
fIN = 249.91269MHz
AIN = -1.080dBFS
SNR = 65dB
SINAD = 64.4dB
THD = -73.4dBc
SFDR = 77.2dBc
HD2 = -77.2dBc
HD3 = -78.3dBc HD3 HD2
0 102030405060708090100
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT
(8192-POINT DATA RECORD)
MAX1214 toc05
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
fSAMPLE = 209.99946MHz
fIN1 = 99.02686MHz
fIN2 = 101.0776221MHz
AIN1 = AIN2 = -7dBFS
IMD = -74dBc
fIN1
fIN2
2fIN2 -fIN2
2fIN1 +fIN2
2fIN2 +fIN1
0 102030405060708090100
ANALOG INPUT FREQUENCY (MHz)
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 209.99946MHz, AIN = -1dBFS)
MAX1214 toc06
fIN (MHz)
SNR/SINAD (dB)
25020015010050
50
55
60
65
70
45
0300
SNR
SINAD
SFDR vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 209.99946MHz, AIN = -1dBFS)
MAX1214 toc07
fIN (MHz)
SFDR (dBc)
25020015010050
45
50
55
60
65
70
75
80
85
90
95
40
0300
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 209.99946MHz, AIN = -1dBFS)
MAX1214 toc08
fIN (MHz)
HD2/HD3 (dBc)
25020015010050
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-100
0300
HD3
HD2
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 209.99964MHz, fIN = 65.0865033MHz)
MAX1214 toc9
ANALOG INPUT AMPLITUDE (dBFS)
SNR/SINAD (dB)
5-10-15-20-25-30-35-40-45-50
20
30
40
50
60
70
10
-55 0
SNR
SINAD
Typical Operating Characteristics
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, AIN = -1dBFS; see each TOC for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA= +25°C.)
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
6 ______________________________________________________________________________________
SFDR vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 209.99946MHz, fIN = 65.08650MHz)
MAX1214 toc10
ANALOG INPUT AMPLITUDE (dBFS)
SFDR (dBc)
-5-10-15-20-25-35-35-40-45-50
40
50
60
70
80
90
30
-55 0
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 209.99946MHz, fIN = 65.08650MHz)
MAX1214 toc11
ANALOG INPUT AMPLITUDE (dBFS)
HD2/HD3 (dBc)
-5-10-15-20-25-30-35-40-45-50
-90
-80
-70
-60
-50
-40
-30
-100
-55 0
HD3
HD2
SNR/SINAD vs. SAMPLE FREQUENCY
(fIN = 65MHz, AIN = -1dBFS)
MAX1214 toc12
fSAMPLE (MHz)
SNR/SINAD (dB)
180150120906030
54
58
62
66
70
50
0210
SNR
SINAD
SFDR vs. SAMPLE FREQUENCY
(fIN = 65MHz, AIN = -1dBFS)
MAX1214 toc13
fSAMPLE (MHz)
SFDR (dBc)
180150120906030
60
65
70
75
80
85
55
0210
HD2/HD3 vs. SAMPLE FREQUENCY
(fIN = 65MHz, AIN = -1dBFS)
MAX1214 toc14
fSAMPLE (MHz)
HD2/HD3 (dBc)
180150120906030
-100
-105
-95
-90
-85
-80
-75
-70
-60
-65
-110
0210
HD3
HD2
TOTAL POWER DISSIPATION vs. SAMPLE
FREQUENCY (fIN = 65MHz, AIN = -1dBFS)
MAX1214 toc15
fSAMPLE (MHz)
PDISS (mW)
180150120906030
730
750
770
790
810
830
710
0210
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1214 toc16
DIGITAL OUTPUT CODE
INL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
04096
fIN = 13MHz
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1214 toc17
DIGITAL OUTPUT CODE
DNL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
04096
fIN = 13MHz
GAIN BANDWIDTH PLOT
(fSAMPLE = 209.99946MHz, AIN = -1dBFS)
MAX1214 toc18
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
100
-6
-5
-4
-3
-2
-1
0
1
-7
10 1000
DIFFERENTIAL TRANSFORMER COUPLING
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, AIN = -1dBFS; see each TOC for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA= +25°C.)
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
_______________________________________________________________________________________ 7
SNR/SINAD vs. TEMPERATURE
(fIN = 100MHz, AIN = -1dBFS)
MAX1214 toc19
TEMPERATURE (°C)
SNR/SINAD (dB)
603510-15
61
62
63
64
65
66
67
68
69
70
60
-40 85
SNR
SINAD
SFDR vs. TEMPERATURE
(fIN = 100MHz, AIN = -1dBFS)
MAX1214 toc20
TEMPERATURE (°C)
SFDR (dBc)
303510-15
62
64
66
68
70
72
74
76
78
80
60
-40 85
HD2/HD3 vs. TEMPERATURE
(fIN = 100MHz, AIN = -1dBFS)
MAX1214 toc21
TEMPERATURE (°C)
HD2/HD3 (dBc)
303510-15
-96
-92
-88
-84
-80
-76
-72
-68
-64
-60
-100
-40 85
HD3
HD2
SNR/SINAD, SFDR vs. SUPPLY VOLTAGE
(fIN = 65.06850MHz, AIN = -1dBFS)
MAX1214 toc22
SUPPLY VOLTAGE (V)
SNR/SINAD, SFDR (dB, dBc)
1.851.801.75
65
67
69
71
73
75
63
1.70 1.90
SNR
SINAD
SFDR
AVCC = OVCC
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, AIN = -1dBFS; see each TOC for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA= +25°C.)
INTERNAL REFERENCE
vs. SUPPLY VOLTAGE
MAX1214 toc23
SUPPLY VOLTAGE (V)
VREFIO (V)
1.851.801.75
1.2410
1.2420
1.2430
1.2440
1.2450
1.2400
1.70 1.90
MEASURED AT THE REFIO PIN
REFADJ = AVCC = OVCC
PROPAGATION DELAY TIMES
vs. TEMPERATURE
MAX1214 toc24
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
603510-15
1
2
3
4
5
6
0
-40 85
tCPDL
tPDL
NOISE-POWER RATIO vs. ANALOG INPUT
POWER (fNOTCH = 28.8MHz 1MHz)
MAX1214 toc25
ANALOG INPUT POWER (dBFS)
NPR (dB)
-5-10-20 -15-30 -25-35
25
30
35
40
45
50
55
60
65
70
20
-40 0
WIDE NOISE BANDWIDTH = 50MHz
NOISE-POWER RATIO PLOT
(WIDE NOISE BANDWIDTH: 50MHz)
MAX1214 toc26
ANALOG INPUT FREQUENCY (MHz)
NPR (dB)
454030 3510 15 20 255
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
050
fNOTCH = 28.8MHz
NPR = 59.5dB
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 6, 11–14, 20,
25, 62, 63, 65 AVCC Analog Supply Voltage. Bypass each pin with a parallel combination of 0.1µF and 0.22µF
capacitors for best decoupling results.
2, 5, 7, 10, 15, 16,
18, 19, 21, 24,
64, 66, 67
AGND Analog Converter Ground
3 REFIO
Reference Input/Output. With REFADJ pulled high, this I/O port allows an external reference
source to be connected to the MAX1214. With REFADJ pulled low, the internal 1.23V bandgap
reference is active.
4 REFADJ
Reference Adjust Input. REFADJ allows for FSR adjustments by placing a resistor or trim
potentiometer between REFADJ and AGND (decreases FSR) or REFADJ and REFIO (increases
FSR). If REFADJ is connected to AVCC, the internal reference can be overdriven with an
external source connected to REFIO. If REFADJ is connected to AGND, the internal reference is
used to determine the FSR of the data converter.
8 INP Positive Analog Input Terminal. Internally self-biased to 1.365V.
9 INN Negative Analog Input Terminal. Internally self-biased to 1.365V.
17 CLKDIV
Clock Divider Input. This LVCMOS-compatible input controls with which speed the converter’s
digital outputs are updated. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.
CLKDIV = 1: ADC updates digital outputs at input clock rate.
22 CLKP True Clock Input. This input ideally requires an LVPECL-compatible input level to maintain the
converter’s excellent performance. Internally self-biased to 1.15V.
23 CLKN Complementary Clock Input. This input ideally requires an LVPECL-compatible input level to
maintain the converter’s excellent performance. Internally self-biased to 1.15V.
26, 45, 61 OGND Digital Converter Ground. Ground connection for digital circuitry and output drivers.
27, 28, 41, 44, 60 OVCC Digital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results.
29 D0N Complementary Output Bit 0 (LSB)
30 D0P True Output Bit 0 (LSB)
31 D1N Complementary Output Bit 1
32 D1P True Output Bit 1
33 D2N Complementary Output Bit 2
34 D2P True Output Bit 2
35 D3N Complementary Output Bit 3
36 D3P True Output Bit 3
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN NAME FUNCTION
37 D4N Complementary Output Bit 4
38 D4P True Output Bit 4
39 D5N Complementary Output Bit 5
40 D5P True Output Bit 5
42 DCLKN Complementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock.
43 DCLKP True Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock.
46 D6N Complementary Output Bit 6
47 D6P True Output Bit 6
48 D7N Complementary Output Bit 7
49 D7P True Output Bit 7
50 D8N Complementary Output Bit 8
51 D8P True Output Bit 8
52 D9N Complementary Output Bit 9
53 D9P True Output Bit 9
54 D10N Complementary Output Bit 10
55 D10P True Output Bit 10
56 D11N Complementary Output Bit 11 (MSB)
57 D11P True Output Bit 11 (MSB)
58 ORN Complementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.
59 ORP True Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP flags
this condition by transitioning high.
68 T/B
Two’s Complement or Binary Output Format Selection. This LVCMOS-compatible input controls
the digital output format of the MAX1214. T/B has an internal pulldown resistor.
T/B = 0: Two’s complement output format.
T/B = 1: Binary output format.
—EP
Exposed Paddle. The exposed paddle is located on the backside of the chip and must be
connected to analog ground for optimum performance.
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
10 ______________________________________________________________________________________
Detailed Description—
Theory of Operation
The MAX1214 uses a fully differential pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy, and linearity while minimizing power
consumption and die size.
Both positive (INP) and negative/complementary ana-
log input terminals (INN) are centered around a 1.365V
common-mode voltage, and accept a differential ana-
log input voltage swing of ±VFS / 4 each, resulting in a
typical 1.454VP-P differential full-scale signal swing.
Inputs INP and INN are buffered prior to entering each
T/H stage and are sampled when the differential sam-
pling clock signal transitions high.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. The result is a 12-bit parallel
digital output word in user-selectable two’s-complement
or offset binary output formats with LVDS-compatible
output levels. See Figure 1 for a more detailed view of
the MAX1214 architecture.
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1214. Differential inputs usually feature good rejec-
tion of even-order harmonics, which allows for
enhanced AC performance as the signals are progress-
ing through the analog stages. The MAX1214 analog
inputs are self-biased at a 1.365V common-mode volt-
age and allow a 1.454VP-P differential input voltage
swing (Figure 2). Both inputs are self-biased through
2kΩresistors, resulting in a typical differential input
resistance of 4kΩ. It is recommended to drive the ana-
log inputs of the MAX1214 in AC-coupled configuration
to achieve best dynamic performance. See the
Transformer-Coupled, Differential Analog Input Drive
section for a detailed discussion of this configuration.
MAX1214
CLOCK-
DIVIDER
CONTROL
CLKDIV
CLOCK
MANAGEMENT
INPUT
BUFFER
DCLKP
D0P/N–D11P/N
DCLKN
12
ORP
ORN
2.2kΩ2.2kΩ
CLKP
CLKN
INP
INN
COMMON-MODE
BUFFER
REFIO REFADJ
LVDS
DATA PORT
REFERENCE
T/H 12-BIT PIPELINE
QUANTIZER
CORE
2.2kΩ
INP
2.2kΩ
AGND
COMMON-MODE
VOLTAGE (1.365V)
COMMON-MODE
VOLTAGE (1.365V)
INN
TO COMMON MODE
TO COMMON MODE
1.454VP-P
DIFFERENTIAL FSR
INP
-VFS / 4
-VFS / 4
+VFS / 4
VFS / 2VFS / 2
+VFS / 4
INN
AVCC
Figure 1. MAX1214 Block Diagram
Figure 2. Simplified Analog Input Architecture and Allowable
Input Voltage Range
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
______________________________________________________________________________________ 11
On-Chip Reference Circuit
The MAX1214 features an internal 1.23V bandgap refer-
ence circuit (Figure 3), which in combination with an inter-
nal reference-scaling amplifier determines the FSR of the
MAX1214. Bypass REFIO with a 0.1µF capacitor to
AGND. To compensate for gain errors or increase the
ADC’s FSR, the voltage of this bandgap reference can be
indirectly adjusted by adding an external resistor (e.g.,
100kΩtrim potentiometer) between REFADJ and AGND
or REFADJ and REFIO. See the Applications Information
section for a detailed description of this process.
To disable the internal reference, connect REFADJ to
AVCC. In this configuration, an external, stable refer-
ence must be applied to REFIO to set the converter’s
full scale. To enable the internal reference, connect
REFADJ to AGND.
Clock Inputs (CLKP, CLKN)
Designed for a differential LVDS clock input drive, it is
recommended to drive the clock inputs of the MAX1214
with an LVDS- or PECL-compatible clock to achieve the
best dynamic performance. The clock signal source
must be a high-quality, low phase noise with fast edge
rates to avoid any degradation in the noise performance
of the ADC. The clock inputs (CLKP, CLKN) are internally
biased to 1.15V, accept a typical 0.5VP-P differential sig-
nal swing, and are usually driven in AC-coupled configu-
ration. See the Differential, AC-Coupled PECL-
Compatible Clock Input section for more circuit details
on how to drive CLKP and CLKN appropriately. Although
not recommended, the clock inputs also accept a single-
ended input signal.
The MAX1214 also features an internal clock-manage-
ment circuit (duty-cycle equalizer) that ensures the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty-cycle clock signal
that desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum clock fre-
quency of >20MHz to work appropriately and accord-
ing to data sheet specifications.
Data Clock Outputs (DCLKP, DCLKN)
The MAX1214 features a differential clock output, which
can be used to latch the digital output data with an
external latch or receiver. Additionally, the clock output
can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
4.31ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 4 for timing details.
Divide-by-2 Clock Control (CLKDIV)
The MAX1214 offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at one-
half the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that require this divide-by-2 mode. Connecting CLKDIV
to OVCC disables the divide-by-2 mode.
MAX1214
REFERENCE
BUFFER
ADC FULL SCALE = REFT - REFB
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
1V
AVCC AVCC/2
G
CONTROL LINE TO
DISABLE REFERENCE BUFFER
REFERENCE
SCALING AMPLIFIER
REFIO
REFADJ
0.1μF
100Ω*
*REFADJ MAY
BE SHORTED TO
AGND DIRECTLY
REFT
REFB
Figure 3. Simplified Reference Architecture
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
12 ______________________________________________________________________________________
System Timing Requirements
Figure 4 depicts the relationship between the clock
input and output, analog input, sampling event, and
data output. The MAX1214 samples on the rising
(falling) edge of CLKP (CLKN). Output data is valid on
the next rising (falling) edge of the DCLKP (DCLKN)
clock, but has an internal latency of 11 clock cycles.
Digital Outputs (D0P/N–D11P/N, DCLKP/N,
ORP/N) and Control Input
T
/B
Digital outputs D0P/N–D11P/N, DCLKP/N, and ORP/N
are LVDS compatible, and data on D0P/N–D11P/N is
presented in either binary or two’s-complement format
(Table 1). The T/B control line is an LVCMOS-compati-
ble input, which allows the user to select the desired
output format. Pulling T/B low outputs data in two’s
complement and pulling it high presents data in offset
binary format on the 12-bit parallel bus. T/B has an
internal pulldown resistor and may be left unconnected
in applications using only two’s-complement output
format. All LVDS outputs provide a typical voltage
swing of 0.325V around a common-mode voltage of
1.15V, and must be terminated at the far end of each
transmission line pair (true and complementary) with
100Ω. The LVDS outputs are powered from a separate
power supply, which can be operated between 1.7V
and 1.9V.
The MAX1214 offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out-of-range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Note: Although a differential LVDS output architecture
reduces single-ended transients to the supply and
ground planes, capacitive loading on the digital out-
puts should still be kept as low as possible. Using
LVDS buffers on the digital outputs of the ADC when
driving larger loads may improve overall performance
and reduce system-timing constraints.
SAMPLING EVENT
INN
INP
CLKN
CLKP
DCLKP
DCLKN
D0P/N–
D11P/N
ORP/N
SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT
tCL
tCH
tAD
tPDL
tCPDL - tPDL~ 0.4 x tSAMPLE WITH tSAMPLE = 1/fSAMPLE
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
tCPDL
tLATENCY
tCPDL - tPDL
NN + 1 N + 8 N + 9
N - 8
N - 8 N - 7 N - 1 N + 1
N
N - 7 NN + 1
Figure 4. System and Output Timing Diagram
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
______________________________________________________________________________________ 13
Applications Information
FSR Adjustments Using the Internal
Bandgap Reference
The MAX1214 supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale signal range, an
external resistor value ranging from 13kΩto 1MΩmay
be added between REFADJ and AGND. A similar
approach can be taken to increase the ADC’s full-scale
range FSR. Adding a variable resistor, potentiometer,
or predetermined resistor value between REFADJ and
REFIO increases the FSR of the data converter. Figure
6a shows the two possible configurations and their
impact on the overall full-scale range adjustment of the
MAX1214. Do not use resistor values of less than 13kΩ
to avoid instability of the internal gain regulation loop
for the bandgap reference. See Figure 6b for the
results of the adjustment range for a selection of resis-
tors used to trim the full-scale range of the MAX1214.
Table 1. MAX1214 Digital Output Coding
INP ANALOG
INPUT VOLTAGE
LEVEL
INN ANALOG
INPUT VOLTAGE
LEVEL
OUT-OF-RANGE
ORP (ORN)
BINARY DIGITAL OUTPUT
CODE (D11P/N–D0P/N)
TWO’S COMPLEMENT DIGITAL
OUTPUT CODE (D11P/N–D0P/N)
> VCM + VFS / 4 < VCM - VFS / 4 1 (0) 1111 1111 1111
(exceeds +FS, OR set)
0111 1111 1111
(exceeds +FS, OR set)
VCM + VFS / 4 VCM - VFS / 4 0 (1) 1111 1111 1111 (+FS) 0111 1111 1111 (+FS)
VCM VCM 0 (1) 1000 0000 0000 or
0111 1111 1111 (FS/2)
0000 0000 0000 or
1111 1111 1111 (FS/2)
VCM - VFS / 4 VCM + VFS / 4 0 (1) 0000 0000 0000 (-FS) 1000 0000 0000 (-FS)
< VCM + VFS / 4 > VCM - VFS / 4 1 (0) 00 0000 0000
(exceeds -FS, OR set)
10 0000 0000
(exceeds -FS, OR set)
VON
OGND
OVCC
VOP
2.2kΩ2.2kΩ
Figure 5. Simplified LVDS Output Architecture
MAX1214
REFERENCE
BUFFER
ADC FULL SCALE = REFT - REFB
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
1V
AVCC AVCC/2
G
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
REFERENCE-
SCALING
AMPLIFIER
REFIO
REFADJ
13kΩ TO
1MΩ
0.1μF
REFT
REFB
13kΩ TO
1MΩ
Figure 6a. Circuit Suggestions to Adjust the ADC’s Full-Scale
Range
FS VOLTAGE vs. FS ADJUST RESISTOR
MAX1213 fig06b
FS ADJUST RESISTOR (kΩ)
VFS (V)
875750500 625250 375125
1.39
1.41
1.43
1.45
1.47
1.49
1.51
1.53
1.55
1.57
1.37
0 1000
RESISTOR VALUE APPLIED BETWEEN
REFADJ AND REFIO INCREASES VFS
RESISTOR VALUE APPLIED BETWEEN
REFADJ AND AGND DECREASES VFS
Figure 6b. FS Adjustment Range vs. FS Adjustment Resistor
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
14 ______________________________________________________________________________________
Differential, AC-Coupled,
LVPECL-Compatible Clock Input
The MAX1214 dynamic performance depends on the
use of a very clean clock source. The phase noise floor
of the clock source has a negative impact on the SNR
performance. Spurious signals on the clock signal
source also affect the ADC’s dynamic range. The pre-
ferred method of clocking the MAX1214 is differentially
with LVDS- or LVPECL-compatible input levels. The fast
data transition rates of these logic families minimize the
clock-input circuitry’s transition uncertainty, thereby
improving the SNR performance. To accomplish this, a
50Ωreverse-terminated clock signal source with low
phase noise is AC-coupled into a fast differential
receiver such as the MC100LVEL16D (Figure 7). The
receiver produces the necessary LVPECL output levels
to drive the clock inputs of the data converter.
Transformer-Coupled,
Differential Analog Input Drive
In general, the MAX1214 provides the best SFDR and
THD with fully differential input signals and it is not
recommended to drive the ADC inputs in single-ended
configuration. In differential input mode, even-order
harmonics are usually lower since INP and INN are bal-
anced, and each of the ADC inputs only requires half
the signal swing compared to a single-ended configu-
ration. Wideband RF transformers provide an excellent
solution to convert a single-ended signal to a fully dif-
ferential signal, required by the MAX1214 to reach its
optimum dynamic performance.
A secondary-side termination of a 1:1 transformer (e.g.,
Mini-Circuit’s ADT1-1WT) into two separate 24.9Ω±1%
resistors (use tight resistor tolerances to minimize
effects of imbalance; 0.5% would be an ideal choice)
placed between top/bottom and center tap of the trans-
former is recommended to maximize the ADC’s dynam-
ic range. This configuration optimizes THD and SFDR
performance of the ADC by reducing the effects of
transformer parasitics. However, the source imped-
ance combined with the shunt capacitance provided
by a PCB and the ADC’s parasitic capacitance limit the
ADC’s full-power input bandwidth to approximately
600MHz.
MC100LVEL16D
AGND OGND
D0P/N–D11P/N
AVCC
VCLK
0.1μF
0.1μF
0.1μF
0.1μF
0.01μF
SINGLE-ENDED
INPUT TERMINAL
150Ω
150Ω
CLKP
CLKN
INP
INN
OVCC
12
2
8
45
7
6
3
50Ω
510Ω510Ω
MAX1214
Figure 7. Differential, AC-Coupled, LVPECL-Compatible Clock Input Configuration
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
______________________________________________________________________________________ 15
To further enhance THD and SFDR performance at high
input frequencies (>100MHz), a second transformer
(Figure 8) should be placed in series with the single-
ended-to-differential conversion transformer. This trans-
former reduces the increase of even-order harmonics
at high frequencies.
Single-Ended, AC-Coupled Analog Inputs
Although not recommended, the MAX1214 can be used
in single-ended mode (Figure 9). Analog signals can be
AC-coupled to the positive input INP through a 0.1µF
capacitor and terminated with a 49.9Ωresistor to AGND.
The negative input should be reverse terminated with
49.9Ωresistors and AC-grounded with a 0.1µF capacitor.
Grounding, Bypassing, and
Board Layout Considerations
The MAX1214 requires board layout design techniques
suitable for high-speed data converters. This ADC pro-
vides separate analog and digital power supplies. The
analog and digital supply voltage pins accept 1.7V to
1.9V input voltage ranges. Although both supply types
can be combined and supplied from one source, it is
recommended to use separate sources to cut down on
performance degradation caused by digital switching
currents, which can couple into the analog supply net-
work. Isolate analog and digital supplies (AVCC and
OVCC) where they enter the PCB with separate net-
works of ferrite beads and capacitors to their corre-
sponding grounds (AGND, OGND).
AGND OGND
D0P/N–D11P/N
AVCC
INP
INN
OVCC
12
MAX1214
0.1μF
25Ω
25Ω
0.1μFADT1-1WT ADT1-1WT
10Ω
10Ω
SINGLE-ENDED
INPUT TERMINAL
AGND OGND
D0P/N–D11P/N
AVCC
INP
49.9Ω
1%
49.9Ω
1%
INN
OVCC
12
MAX1214
0.1μF
SINGLE-ENDED
INPUT TERMINAL
0.1μF
Figure 8. Analog Input Configuration with Back-to-Back Transformers and Secondary-Side Termination
Figure 9. Single-Ended AC-Coupled Analog Input Configuration
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
16 ______________________________________________________________________________________
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor
and parallel combinations of 10µF and 1µF ceramic
capacitors. Additionally, the ADC requires each supply
pin to be bypassed with separate 0.1µF ceramic
capacitors (Figure 10). Locate these capacitors directly
at the ADC supply pins or as close as possible to the
MAX1214. Choose surface-mount capacitors, whose
preferred location should be on the same side as the
converter to save space and minimize the inductance.
If close placement on the same side is not possible,
these bypassing capacitors may be routed through
vias to the bottom side of the PCB.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. The dynamic currents that may need to travel
long distances before they are recombined at a com-
mon-source ground, resulting in large and undesirable
ground loops, are a major concern with this approach.
Ground loops can degrade the input noise by coupling
back to the analog front-end of the converter, resulting
in increased spurious activity, leading to decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
coupling of the digital output signals from the analog
input, segregate the digital output bus carefully from the
analog input circuitry. To further minimize the effects of
digital noise coupling, ground return vias can be posi-
tioned throughout the layout to divert digital switching
currents away from the sensitive analog sections of the
ADC. This approach does not require split ground
planes, but can be accomplished by placing substantial
ground connections between the analog front-end and
the digital outputs.
The MAX1214 is packaged in a 68-pin QFN-EP pack-
age (package code: G6800-4), providing greater
design flexibility, increased thermal dissipation, and
optimized AC performance of the ADC. The exposed
paddle (EP) must be soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PCB side of
the package. This allows a solid attachment of the
package to the board with standard infrared (IR) flow
soldering techniques.
Thermal efficiency is one of the factors for selecting a
package with an exposed pad for the MAX1214. The
exposed pad improves thermal and ensures a solid
ground connection between the DAC and the PCB’s
analog ground layer.
Considerable care must be taken when routing the digi-
tal output traces for a high-speed, high-resolution data
converter. It is recommended running the LVDS output
traces as differential lines with 100Ωmatched imped-
ance from the ADC to the LVDS load device.
AGND
NOTE: EACH POWER-SUPPLY PIN (ANALOG
AND DIGITAL) SHOULD BE DECOUPLED WITH
AN INDIVIDUAL 0.1μF CAPACITOR AS CLOSE
AS POSSIBLE TO THE ADC.
BYPASSING—ADC LEVEL BYPASSING—BOARD LEVEL
ANALOG POWER-
SUPPLY SOURCE
OGND
AGND OGND
D0P/N–D11P/N
1μF10μF
0.1μF0.1μF
47μF
AVCC OVCC
12
MAX1214
AVCC
DIGITAL/OUTPUT
DRIVER POWER-
SUPPLY SOURCE
1μF10μF47μF
OVCC
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1214
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
______________________________________________________________________________________ 17
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. However, the
static linearity parameters for the MAX1214 are mea-
sured using the histogram method with a 10MHz input
frequency.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function. The
MAX1214’s DNL specification is measured with the his-
togram method based on a 10MHz input tone.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
SNR[max] = 6.02 x N + 1.76
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities are also contributing to the SNR calcula-
tion and should be considered when determining the
signal-to-noise ratio in ADC.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components excluding the fundamen-
tal and the DC offset. In the case of the MAX1214,
SINAD is computed from a curve fit.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal component) to the RMS value
of the next-largest noise or harmonic distortion compo-
nent. SFDR is usually measured in dBc with respect to
the carrier frequency amplitude or in dBFS with respect
to the ADC’s full-scale range.
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
The fundamental input tone amplitudes (V1and V2) are at
-7dBFS. The intermodulation products are the amplitudes
of the output spectrum at the following frequencies:
• Second-order intermodulation products: fIN1 + fIN2,
fIN2 - fIN1
• Third-order intermodulation products: 2 x fIN1 - fIN2,
2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1
• Fourth-order intermodulation products: 3 x fIN1 - fIN2,
3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1
• Fifth-order intermodulation products: 3 x fIN1 - 2 x fIN2,
3 x fIN2-2 x fIN1, 3 x fIN1+2 x fIN2, 3 x fIN2 + 2 x fIN1
Full-Power Bandwidth
A large -1dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. The -3dB point is defined as
the full-power input bandwidth frequency of the ADC.
IMD VV V V
VV
IM IM IM IMn
log ......
=× ++++
+
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
20 1
222322
1
222
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
tAD
tAJ
TRACK TRACK
CLKN
CLKP
Figure 11. Aperture Jitter/Delay Specifications
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
18 ______________________________________________________________________________________
Noise-Power Ratio (NPR)
NPR is commonly used to characterize the return path of
cable systems where the signals are typically individual
quadrature amplitude-modulated (QAM) carriers with a
frequency spectrum similar to noise. Numerous such
carriers are operated in a continuous spectrum, generat-
ing a noise-like signal, which covers a relatively broad
bandwidth. To test the MAX1214 for NPR, a “noise-like”
signal is passed through a high-order bandpass filter to
produce an approximately square spectral pedestal of
noise with about the same bandwidth as the signals
being simulated. Following the bandpass filter, the signal
is passed through a narrow band-reject filter to produce
a deep notch at the center of the noise pedestal. Finally,
this signal is applied to the MAX1214 and its digitized
results analyzed. The RMS noise power of the signal
inside the notch is compared with the RMS noise level
outside the notch using an FFT. Note that the NPR test
requires sufficiently long data records to guarantee a
suitable number of samples inside the notch. NPR for the
MAX1214 was determined for 50MHz noise bandwidth
signals, simulating a typical cable signal environment
(see the Typical Operating Characteristics for test details
and results), and with a notch frequency of 28.8MHz.
Pin-Compatible, Lower-
Speed/Resolution Versions
Applications that require lower resolution, a choice of
buffered or non-buffered outputs, and/or higher speed
can refer to other family members of the MAX1214.
Adjusting an application to a lower resolution has been
simplified by maintaining an identical pinout for all mem-
bers of this high-speed family. See the Pin-Compatible
Versions table on the first page of this data sheet for a
selection of different resolution and speed grades.
Pin Configuration
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
AVCC
AGND
AVCC
TOP VIEW
AVCC
OGND
OVCC
ORP
ORN
D11P
D11N
D10P
D10N
5253
D9P
D9N
AGND
AGND
AVCC
CLKN
CLKP
AVCC
AGND
OVCC
OGND
D0N
OVCC
D1N
D0P
D1P
D6P
D6N
OGND
OVCC
DCLKP
DCLKN
OVCC
D5P
D5N
D4P
35
36
37 D4N
D3P
D3N
AGND
INN
INP
AGND
AVCC
AGND
AGND
AVCC
AVCC
AVCC
AGND
REFADJ
REFIO
AGND
48 D7N
AVCC
64
AGND
656667
AGND
AGND
AVCC
68
T/B
2322212019 2726252418 2928 323130
D2N
D2P
3433
49
50 D8N
D7P
EP
51 D8P
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
CLKDIV 17
MAX1214
QFN
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
______________________________________________________________________________________ 19
68L QFN.EPS
C12
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
For the MAX1214, the package code is G6800-4.
MAX1214
1.8V, 12-Bit, 210Msps ADC for
Broadband Applications
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
C
12
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Revision History
Pages changed at Rev 1: 1, 2, 12–16, 18, 20
