HEXFET® Power MOSFET
VDSS = 55V
RDS(on) = 5.3m
ID = 95A
12/22/03
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AUTOMOTIVE MOSFET
PD - 95810
Specifically designed for Automotive applications, this HEXFET®
Power MOSFET utilizes the latest processing techniques to
achieve extremely low on-resistance per silicon area. Additional
features of this design are a 175°C junction operating tempera-
ture, fast switching speed and improved repetitive avalanche
rating . These features combine to make this design an extremely
efficient and reliable device for use in Automotive applications and
a wide variety of other applications.
S
D
G
Description
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Features
HEXFET® is a registered trademark of International Rectifier.
* Rθ is measured at TJ approximately 90°C
IRFP1405
TO-247AC
S
D
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Absolute Maximum Ratin
g
s
Parameter Units
ID @ TC = 2 5 °C C ont inuous D r a i n C u r r ent, VGS @ 10V (Silicon Limited)
ID @ TC = 10C C ont inuous D r a i n C u r r ent, VGS @ 10V A
ID @ TC = 2 5 °C C ont inuous D r a i n C u r r ent, VGS @ 10V (Package Limited
)
IDM
P
u
l
se
d
D
ra
i
n
C
urren
t
c
PD @TC = 25° C Powe r Dissipation W
Linear Derating Factor W/°C
VGS Gate-to- Sou r c e Volta
g
e V
EAS (Thermally limited)
Si
n
gl
e
P
u
l
se
A
va
l
anc
h
e
E
ner
gy
d
mJ
EAS (Tes te d )
Si
n
gl
e
P
u
l
se
A
va
l
anc
h
e
E
ner
gy
T
es
t
e
d
V
a
l
ue
h
IAR
A
va
l
anc
h
e
C
urren
t
A
EAR
R
epe
titi
ve
A
va
l
anc
h
e
E
ner
gy
g
mJ
TJ Operatin
g
Junction and
TSTG Stora
g
e Temperature Ran
g
C
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
Th ermal Resistance Parameter Typ. Max. Units
RθJC Junc t ion-to-C as e * ––– 0.4 9
Rθcs Case-to-Sink, Flat, Greased Surface 0.24 ––– °C/W
RθJA Junc t ion-to-A m bient * ––– 40
1060
530
Se e Fig. 12 a, 12b, 15, 16
310
2.0
± 20
Max.
160
110
640
95
-55 to + 175
300 (1.6mm from case )
10 lbf
y
in (1.1N
y
m)
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Electrical Characterist ics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
V(BR)DSS D r ai n- to- Sour c e B reakd ow n V oltage 55 ––– ––– V
V(BR)DSS
/
TJ Br eakdown Volt age Temp. Coefficient ––– 0.058 ––– V/°C
RDS(on) Stati c Dr ain- to- Sour c e O n- Res i s tanc e ––– 4. 2 5.3 m
VGS(th) Gate Threshold Voltage 2.0 –– 4.0 V
gfs For ward Tr ansconduct ance 77 –– ––– S
IDSS Dr ai n- to- Sour c e Leak age Cu rr ent ––– ––– 20 µA
––– –– 250
IGSS Gate-t o- Sour c e Fo r w ard Lea kag e ––– ––– 200 nA
Gate- to- Sour c e R ev e r s e Leak age ––– ––– -20 0
QgTotal Gate Charge ––– 120 180
Qgs Gate- to- Sou r c e C har ge ––– 30 ––– nC
Qgd Gate-to - Drain ( " Mille r") Charge ––– 53 –––
td(on) Turn-On Delay Time ––– 12 –––
trRise Ti m e ––– 16 0 –––
td(off) Turn-Off Delay Ti me ––– 140 ––– n s
tfFall Time –– 150 –––
LDInternal Drain Inductance ––– 5.0 ––– Between lead,
nH 6mm (0.25in.)
LSInt er nal Source Inducta nce ––– 13 ––– fr om package
and center of die contact
Ciss Input Capacitance ––– 5600 ––
Coss Output Capacitance ––– 1310 ––
Crss Reve rse Tr a ns fer Cap acit a nc e ––– 350 ––– pF
Coss Output Capacitance ––– 6550 ––
Coss Output Capacitance ––– 920 –––
Coss ef f. Effective Output Capacitance ––– 1750 ––
Source-Drain Ratin
g
s and Characteristics
Par a me t e r Min. Ty p. M a x . Units
ISContinuous So ur ce Cu rrent –– ––– 9 5
(Body Diode) A
ISM Pulsed Source Current ––– ––– 640
(Body Diode)
c
VSD Diod e Forward Volta ge –– ––– 1.3 V
trr Reverse Recovery Time ––– 70 1 10 ns
Qrr Reverse Recovery Charge ––– 170 260 nC
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
VGS = 0 V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0 V, VDS = 44V, ƒ = 1. 0M Hz
VGS = 0V, VDS = 0V to 44V
f
VGS = 10V
e
VDD = 28V
ID = 95A
RG = 2.6
TJ = 25°C, IS = 95A, VGS = 0V
e
TJ = 25°C, IF = 95 A, V DD = 28V
di /dt = 100A/µs
e
Conditions
VGS = 0V, ID = 25 A
Refere nce to 25 °C, ID = 1m A
VGS = 10V, ID = 95A
e
VDS = VGS, ID = 250µ A
VDS = 55V , V GS = 0V
VDS = 55V , V GS = 0V , TJ = 12 C
MOSFET symbol
showing the
integra l revers e
p-n junction diode.
VDS = 25V , I D = 95A
ID = 95A
VDS = 44V
Conditions
VGS = 10V
e
VGS = 0V
VDS = 25V
ƒ = 1. 0M H z
VGS = 20V
VGS = -20V
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.12mH
RG = 25 , IAS = 95A, V GS =10V. Part not
recommended for use above this value.
Pulse width 1.0ms; duty cycle 2%.
Notes:
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance
Vs. Drain Current
0 1 10 100
0.1 110 100
VDS, Dr ain-to- Source Voltage (V )
10
100
1000
ID, Drain-to-Source Current (A)
60µs PU LSE WIDTH
Tj = 175° C
4.5V
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.0 5.0 6.0 7.0 8.0 9.0 10.0
VGS, Gate-to-S ource Voltage (V)
10
100
1000
ID, Drain-to-Source Current (Α)
VDS = 25V
60µs PU LSE WIDTH
TJ = 25°C
TJ = 175°C
0.1 110 100
VDS, Dr ain-to- Source Voltage (V )
1
10
100
1000
ID, Drain-to-Source Current (A)
60µs PU LSE WIDTH
Tj = 25° C
4.5V
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
0 20406080100
ID, Drain-to-Source Current (A )
0
20
40
60
80
100
120
140
Gfs, Forward Transconductance (S)
TJ = 25°C
TJ = 175°C
VDS = 10V
380µs PU LSE WIDTH
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Dr ain-to- Source Vol tage (V)
0
2000
4000
6000
8000
10000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 40 80 120 160 200
QG Total G ate Charge (nC)
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
VDS= 44V
VDS= 28V
ID= 95A
FOR TEST CIRCUIT
SEE FIGURE 13
0.2 0.6 1.0 1.4 1.8 2.2
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
1 10 100 1000
VDS , Dr ain-toSource Vol tage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175° C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
DC
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature Fig 10. Normalized On-Resistance
Vs. Temperature
25 50 75 100 125 150 175
TC , C ase Temperatur e (°C)
0
50
100
150
200
ID , Drain Current (A)
LIMITED BY PACKAGE
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 95A
VGS = 10V
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangul ar Pulse D uration ( sec)
0.0001
0.001
0.01
0.1
1
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) τi (sec)
0.2529 0.00080
0.2368 0.014283
τJ
τJ
τ1
τ1τ2
τ2
R1
R1R2
R2
τ
τC
Ci i/Ri
Ci= τi/Ri
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Q
G
Q
GS
Q
GD
V
G
Charge
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage Vs. Temperature
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
25 50 75 100 125 150 175
Starti ng TJ, Junction Temperature (°C)
0
500
1000
1500
2000
EAS, Single Pulse Avalanche Energy (mJ)
ID
TOP 16A
20A
BOTTOM 95A
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
1.5
2.0
2.5
3.0
3.5
4.0
VGS(th) Gate threshold Voltage (V)
ID = 250µA
1K
VCC
DUT
0
L
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Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
10000
Avalanche Current (A)
0.05
Dut y Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
25 50 75 100 125 150 175
Starti ng TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1% Duty Cy cle
ID = 95A
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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
VDS
90%
10%
VGS t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
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Data and specifications subject to change without notice.
This product has been designed and qualified for Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
TO-247AC packages are not recommended for Surface Mount Application.
TO-247AC Package Outline
TO-247AC Part Marking Information
Dimensions are shown in millimeters
LOT CODE
WW = WE EK
YY = YE AR
Notes: T his part marking information applies to devices produced before 02/26/2001 or for
E XAMP L E: T HI S I S AN IR F P E 30
WIT H AS S E MB L Y
LOT CODE 3A1Q
ASSEMBLY
LOGO
RECTIFIER
INTERNATIONAL
3A1Q
IR F PE3 0
PART NUMBER
(YYWW)
DATE CODE
9302
parts manufactur ed i n GB .
Notes: T his part marking information applies to devices produced after 02/26/2001
EXAMPLE:
AS S E MBL ED ON WW 35, 2000
LOT CODE 5657
WIT H AS S E MBL Y
THIS IS AN IRFPE30
IN T HE ASSEMBLY LINE "H" 035H
LOGO
INT ERNAT IONAL
RECTIFIER IRFPE30
LOT CODE
AS S E MB L Y
56 57
PART NUMBER
DATE CODE
YEAR 0 = 2000
WE EK 35
LINE H
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
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'5* 1
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Note: For the most current drawings please refer to the IR website at:
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