1 of 76 REV: 011206
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
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FEATURES
Complete E1, T1, or J1 Line Interface Unit
(LIU)
Supports Both Long-Haul And Short-Haul
Trunks
Internal Software-Selectable Receive-Side
Termination for 75Ω/100Ω/120Ω
3.3V Power Supply
32-Bit or 128-Bit Crystal-Less Jitter
Attenuator Requires Only a 2.048MHz
Master Clock for Both E1 and T1 with
Option to Use 1.544MHz for T1
Generates the Appropriate Line Build-Outs,
with and without Return loss, for E1 and
DSX-1 and CSU Line Build-Outs for T1
AMI, HDB3, and B8ZS, Encoding/Decoding
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Clock
Programmable Monitor Mode for Receiver
Loopbacks and PRBS Pattern Generation/
Detection with Output for Received Errors
Generates/Detects In-Band Loop Codes,
1 to 16 Bits Including CSU Loop Codes
8-Bit Parallel or Serial Interface with
Optional Hardware Mode
Muxed and Nonmuxed Parallel Bus Supports
Intel or Motorola
Detects/Generates Blue (AIS) Alarms
NRZ/Bipolar Interface for Tx/Rx Data I/O
Transmit Open-Circuit Detection
Receive Carrier Loss (RCL) Indication
(G.775)
High-Impedance State for TTIP and TRING
50mA (RMS) Current Limiter
PIN CONFIGURATIONS
ORDERING INFORMATION
+ Denotes lead-free/RoHS-compliant package.
PART CHANNEL TEMP
RANGE PIN-PACKAGE
DS21348TN Single -40°C to +85°C 44 TQFP
DS21348TN+ Single -40°C to +85°C 44 TQFP
DS21348T Single 0°C to +70°C 44 TQFP
DS21348T+ Single 0°C to +70°C 44 TQFP
DS21348GN Single -40°C to +85°C 49 CSBGA
DS21348GN+ Single -40°C to +85°C 49 CSBGA
DS21348G Single 0°C to +70°C 49 CSBGA
DS21348G+ Single 0°C to +70°C 49 CSBGA
DS21Q348N Four -40°C to +85°C 144 CSBGA
DS21Q348 Four 0°C to +70°C 144 CSBGA
111
PRELMINARY
DS21348/DS21Q348
3.3V E1/T1/J1 Line Interface
www.maxim-ic.com
44 TQFP
1
44
DS21348
49 CSBGA
(7mm x 7mm)
DS21Q348
TOP VIEW
See Section 8 for 144-pin CSBGA pinout.
DS21348/DS21Q348
2 of 76
DETAILED DESCRIPTION
The DS21348 is a complete selectable E1 or T1 line interface unit (LIU) for short-haul and long-haul
applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts
automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1
applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary
G.703 E1 waveshapes in 75Ω or 120Ω applications and DSX-1 line build-outs or CSU line build-outs of
0dB, -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less on-board jitter attenuator requires
only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK
in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can
be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK
is available for use as a backplane system clock (where n = 1, 2, 4, or 8).
The DS21348 has diagnostic capabilities such as loopbacks and PRBS pattern generation/detection. 16-
bit loop-up and loop-down codes can be generated and detected. The device can be controlled through an
8-bit parallel muxed or nonmuxed port, serial port, or used in hardware mode. The device fully meets all
of the latest E1 and T1 specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411,
ITU G.703, G.704, G.706, G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703,
JTI.431, JJ-20.1, TBR12, TBR13, and CTR4.
DS21348/DS21Q348
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TABLE OF CONTENTS
1. INTRODUCTION.................................................................................................................. 6
1.1 DOCUMENT REVISION HISTORY...............................................................................................6
2. PIN DESCRIPTION............................................................................................................ 10
2.1 PIN DESCRIPTIONS ........................................................................................................................14
3. HARDWARE MODE .......................................................................................................... 25
3.1 REGISTER MAP .............................................................................................................................25
3.2 PARALLEL PORT OPERATION .........................................................................................................26
3.3 SERIAL PORT OPERATION..............................................................................................................26
4. CONTROL REGISTERS.................................................................................................... 29
4.1 DEVICE POWER-UP AND RESET .....................................................................................................32
5. STATUS REGISTERS ....................................................................................................... 36
6. DIAGNOSTICS .................................................................................................................. 41
6.1 IN-BAND LOOP CODE GENERATION AND DETECTION ......................................................................41
6.2 LOOPBACKS ..................................................................................................................................46
6.2.1 Remote Loopback (RLB) ..................................................................................................................... 46
6.2.2 Local Loopback (LLB) .......................................................................................................................... 46
6.2.3 Analog Loopback (ALB) ....................................................................................................................... 46
6.2.4 Dual Loopback (DLB)........................................................................................................................... 46
6.3 PRBS GENERATION AND DETECTION ............................................................................................47
6.4 ERROR COUNTER..........................................................................................................................47
6.4.1 Error Counter Update........................................................................................................................... 48
6.5 ERROR INSERTION ........................................................................................................................48
7. ANALOG INTERFACE ...................................................................................................... 49
7.1 RECEIVER .....................................................................................................................................49
7.2 TRANSMITTER ...............................................................................................................................50
7.3 JITTER ATTENUATOR .....................................................................................................................50
7.4 G.703 SYNCHRONIZATION SIGNAL .................................................................................................51
8. DS21Q348 QUAD LIU ....................................................................................................... 58
9. DC CHARACTERISTICS................................................................................................... 62
10. THERMAL CHARACTERISTICS....................................................................................... 63
11. AC CHARACTERISTICS................................................................................................... 64
12. PACKAGE INFORMATION ............................................................................................... 73
12.1 44-PIN TQFP (56-G4012-001) .....................................................................................................73
12.2 49-BALL CSGBA (7MM X 7MM) (56-G6006-001) ...........................................................................74
12.3 144-BALL CSBGA (17MM X 17MM) (56-G6011-001) .....................................................................75
DS21348/DS21Q348
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LIST OF FIGURES
Figure 1-1. DS21348 Block Diagram..........................................................................................................7
Figure 1-2. Receive Logic...........................................................................................................................8
Figure 1-3. Transmit Logic..........................................................................................................................9
Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP Package) ..................................22
Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package) ............................................23
Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package) .............................................24
Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1 .........................................................27
Figure 3-2. Serial Port Operation for Read Access Mode 2 .....................................................................27
Figure 3-3. Serial Port Operation for Read Access Mode 3 .....................................................................27
Figure 3-4. Serial Port Operation for Read Access Mode 4 .....................................................................28
Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2..............................................28
Figure 3-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4..............................................28
Figure 7-1. Basic Interface .......................................................................................................................52
Figure 7-2. Protected Interface Using Internal Receive Termination........................................................53
Figure 7-3. Protected Interface Using External Receive Termination.......................................................54
Figure 7-4. E1 Transmit Pulse Template..................................................................................................55
Figure 7-5. T1 Transmit Pulse Template ..................................................................................................56
Figure 7-6. Jitter Tolerance ......................................................................................................................57
Figure 7-7. Jitter Attenuation ....................................................................................................................57
Figure 8-1. 144-CSBGA (17mm x 17mm) Pinout .....................................................................................61
Figure 11-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) .......................................................65
Figure 11-2. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) .......................................................65
Figure 11-3. Motorola Bus Timing (PBTS = 1, BIS1 = 0, BIS0 = 0)..........................................................66
Figure 11-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) .......................................................68
Figure 11-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) .......................................................68
Figure 11-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................................69
Figure 11-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................................69
Figure 11-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0)................................................................................70
Figure 11-9. Receive Side Timing ............................................................................................................71
Figure 11-10. Transmit Side Timing .........................................................................................................72
DS21348/DS21Q348
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LIST OF TABLES
Table 2-1. Bus Interface Selection ...........................................................................................................10
Table 2-2. Pin Assignment in Parallel Port Mode .....................................................................................10
Table 2-3. Pin Assignment in Serial Port Mode........................................................................................11
Table 2-4. Pin Assignment in Hardware Mode .........................................................................................12
Table 2-5. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name, DS21348T Pin Numbering).....14
Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name, DS21348T Pin Numbering) .......16
Table 2-7. Pin Descriptions in Hardware Mode (Sorted By Pin Name, DS21348T Pin Numbering) ........18
Table 2-8. Loopback Control in Hardware Mode......................................................................................21
Table 2-9. Transmit Data Control in Hardware Mode...............................................................................21
Table 2-10. Receive Sensitivity Settings ..................................................................................................21
Table 2-11. Monitor Gain Settings............................................................................................................21
Table 2-12. Internal Rx Termination Select ..............................................................................................21
Table 2-13. MCLK Selection.....................................................................................................................22
Table 3-1. Register Map ...........................................................................................................................25
Table 4-1. MCLK Selection.......................................................................................................................30
Table 4-2. Receive Equalizer Sensitivity Settings ....................................................................................32
Table 4-3. Backplane Clock Select...........................................................................................................34
Table 4-4. Monitor Gain Settings..............................................................................................................34
Table 4-5. Internal Rx Termination Select ................................................................................................34
Table 5-1. Received Alarm Criteria ..........................................................................................................36
Table 5-2. Receive Level Indication .........................................................................................................40
Table 6-1. Transmit Code Length.............................................................................................................41
Table 6-2. Receive Code Length..............................................................................................................42
Table 6-3. Definition of Received Errors...................................................................................................47
Table 6-4. Function of ECRS Bits and RNEG Pin ....................................................................................48
Table 7-1. Line Build-Out Select for E1 in Register CCR4 (ETS = 0).......................................................51
Table 7-2. Line Build-Out Select for T1 in Register CCR4 (ETS = 1).......................................................51
Table 7-3. Transformer Specifications for 3.3V Operation .......................................................................51
Table 8-1. DS21Q348 Pin Assignment.....................................................................................................58
Table 9-1. Recommended DC Operating Conditions ...............................................................................62
Table 9-2. Capacitance ............................................................................................................................62
Table 9-3. DC Characteristics ..................................................................................................................62
Table 10-1. Thermal Characteristics—DS21Q348 CSBGA Package.......................................................63
Table 10-2. Theta-JA (θJA) vs. Airflow.......................................................................................................63
Table 11-1. AC Characteristics—Multiplexed Parallel Port (BIS1 = 0, BIS0 = 0) .....................................64
Table 11-2. AC Characteristics—Nonmultiplexed Parallel Port (BIS1 = 0, BIS0 = 1)...............................67
Table 11-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0) ...........................................................70
Table 11-4. AC Characteristics—Receive Side........................................................................................71
Table 11-5. AC Characteristics—Transmit Side.......................................................................................72
DS21348/DS21Q348
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1. INTRODUCTION
The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is
transformer coupled into the RTIP and RRING pins of the DS21348. The user has the option to use
internal termination, software selectable for 75Ω/100Ω/120Ω applications, or external termination. The
device recovers clock and data from the analog signal and passes it through the jitter attenuation MUX
outputting the received line clock at RCLK and bipolar or NRZ data at RPOS and RNEG. The DS21348
contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in
transmission. The receive circuitry is also configurable for various monitor applications. The device has a
usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allows the device to
operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input at TPOS and
TNEG is sent via the jitter attenuation mux to the waveshaping circuitry and line driver. The DS21348
will drive the E1 or T1 line from the TTIP and TRING pins via a coupling transformer. The line driver
can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for
T1.
1.1 Document Revision History
REVISION DESCRIPTION
011801 Data sheet revised for 3.3V only.
092101 Added supply current measurements
Added thermal characteristics of quad package
101104 Corrected typos and removed all instances of 5V operation.
113004 Updated the storage and soldering temperature specs in the Absolute
Maximum Ratings section.
011206 Added lead-free packages to Ordering Information table on page 1.
DS21348/DS21Q348
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Figure 1-1. DS21348 Block Diagram
VDD
VSS
Power Connections
2
2
VCO / PLL
MCLK
2.048MHz to
1.544MHz PLL
Jitter
A
ttenuato
r
MUX
VSM
A
nalog Loopback
Line Drivers
CSU Filters
Wave Shaping
Local Loopback
TRING
TTIP
Jitter Attenuation
(can be placed in either transmit or receive path)
Filte
r
Peak Detect
Clock / Data
Recovery
RRING
RTIP
Optional
Termination
Remote Loopback (Dual Mode)
Unframed
A
ll Ones
Insertion
D0 to D7 /
A
D0 to AD7
PBTS
W
R(R/W)
R
D(DS)
A
LE(AS)
A
0 to A4
8
5
SDO
SDI
SCLK
I
NT
C
S
21
BIS0
BIS1 Control and Test Port
(routed to all blocks)
MUX (the Serial, Parallel, and Hardware Interfaces share device pins)
H
RST
TEST
16.384MHz or
8.192MHz or
4.096MHz or
2.048MHz
Synthesizer BPCLK
RPOS
RCLK
RNEG
TPOS
TCLK
TNEG
JACLK
M
U
X
See Figure 3-2
See Figure 1-3
PBEO
Hardware
Interface
Control and
Interrupt
Parallel Interface
Serial Interface
Remote Loopback
MUX RCL/LOTC
DS21348
DS21348/DS21Q348
8 of 76
Figure 1-2. Receive Logic
RPOS
RNEG
From
Remote
Loopback
Clock
Invert RCLK
CCR2.0
CCR1.6
Routed to
All Blocks
rx bd
mux
4 or 8 Zero Detect
16 Zero Detect
RIR1.7 RIR1.6
B8ZS/HDB3
Decoder
All Ones
Detector
Loop Code
Detector
PRBS
Detector
SR.6 SR.7SR.4 RIR1.3
CCR2.3
RIR1.5
16-Bit Error
Counter (ECR)
mux CCR6.0
SR.0
CCR6.2/
CCR6.0/
CCR6.1
NRZ Data
BPV/CV/EXZ
PBEO
CCR1.4
DS21348/DS21Q348
9 of 76
Figure 1-3. Transmit Logic
BPV
Insert
mux
B8ZS/
HDB3
Coder
Logic
Error
Insert
mux
OR
Gate
OR
Gate
CCR3.1
CCR1.6
CCR2.2
CCR3.0
CCR3.4
CCR3.3
TPOS
TNEG
To
Remote
Loopback
PRBS Generator
Loop Code Generator
Clock
Invert
Loss Of Transmit
Clock Detect
TCLK
CCR2.1
RCLK
JACLK
(derived
from
MCLK)
CCR1.0
CCR1.1
CCR1.2
1
0
mux
mux
OR
Gate
To LOTC Output Pin
0
1
0
1
AND
Gate
Routed to
All Blocks
tx bd
SR.5
DS21348/DS21Q348
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2. PIN DESCRIPTION
The DS21348 can be controlled in a parallel port mode, serial port mode, or hardware mode (Table 2-2,
Table 2-3, and Table 2-4).
Table 2-1. Bus Interface Selection
BIS1 BIS0 PBTS MODE
0 0 0 Muxed Intel
0 0 1 Muxed Motorola
0 1 0 Nonmuxed Intel
0 1 1 Nonmuxed Motorola
1 0 — Serial Port
1 1 — Hardware
Table 2-2. Pin Assignment in Parallel Port Mode
PIN
DS21348T DS21348G I/O PARALLEL
PORT MODE
1 C3 I CS
2 C2 I
RD (DS)
3 B1 I
WR (R/W)
4 D2 I ALE (AS)
5 C1 I NA
6 D3 I NA
7 D1 I/O A4
8 E1 I A3
9 F2 I A2
10 F1 I A1
11 G1 I A0
12 E3 I/O D7/AD7
13 F3 I/O D6/AD6
14 G2 I/O D5/AD5
15 F4 I/O D4/AD4
16 G3 I/O D3/AD3
17 E4 I/O D2/AD2
18 G4 I/O D1/AD1
19 F5 I/O D0/AD0
20 G5 I VSM
21 F6 — VDD
22 G6 — VSS
23 E5 I/O
INT
24 E6 O PBEO
25 F7 O RCL/LOTC
26 D6 I TEST
27 D5 I RTIP
DS21348/DS21Q348
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PIN
DS21348T DS21348G I/O PARALLEL
PORT MODE
28 D7 I RRING
29 C6 I HRST
30 C7 I MCLK
31 B6 O BPCLK
32 B7 I BIS0
33 A7 I BIS1
34 C5 O TTIP
35 B5 — VSS
36 A6 — VDD
37 B4 O TRING
38 C4 O RPOS
39 A4 O RNEG
40 B3 O RCLK
41 A3 I TPOS
42 B2 I TNEG
43 A2 I TCLK
44 A1 I PBTS
Table 2-3. Pin Assignment in Serial Port Mode
PIN
DS21348T DS21348G I/O SERIAL
PORT MODE
1 C3 I CS
2 C2 I NA
3 B1 I NA
4 D2 I NA
5 C1 I SCLK
6 D3 I SDI
7 D1 I/O SDO
8 E1 I ICES
9 F2 I OCES
10 F1 I NA
11 G1 I NA
12 E3 I/O NA
13 F3 I/O NA
14 G2 I/O NA
15 F4 I/O NA
16 G3 I/O NA
17 E4 I/O NA
18 G4 I/O NA
19 F5 I/O NA
20 G5 I VSM
21 F6 — VDD
22 G6 — VSS
DS21348/DS21Q348
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PIN
DS21348T DS21348G I/O SERIAL
PORT MODE
23 E5 I/O
INT
24 E6 O PBEO
25 F7 O RCL/LOTC
26 D6 I TEST
27 D5 I RTIP
28 D7 I RRING
29 C6 I HRST
30 C7 I MCLK
31 B6 O BPCLK
32 B7 I BIS0
33 A7 I BIS1
34 C5 O TTIP
35 B5 — VSS
36 A6 — VDD
37 B4 O TRING
38 C4 O RPOS
39 A4 O RNEG
40 B3 O RCLK
41 A3 I TPOS
42 B2 I TNEG
43 A2 I TCLK
44 A1 I NA
Table 2-4. Pin Assignment in Hardware Mode
PIN
DS21348T DS21348G I/O HARDWARE
MODE
1 C3 I EGL
2 C2 I ETS
3 B1 I NRZE
4 D2 I SCLKE
5 C1 I L2
6 D3 I L1
7 D1 I/O L0
8 E1 I DJA
9 F2 I JAMUX
10 F1 I JAS
11 G1 I HBE
12 E3 I/O CES
13 F3 I/O TPD
14 G2 I/O TX0
15 F4 I/O TX1
16 G3 I/O LOOP0
DS21348/DS21Q348
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PIN
DS21348T DS21348G I/O HARDWARE
MODE
17 E4 I/O LOOP1
18 G4 I/O MM0
19 F5 I/O MM1
20 G5 I VSM
21 F6 — VDD
22 G6 — VSS
23 E5 I/O RT1
24 E6 O PBEO
25 F7 O RCL
26 D6 I TEST
27 D5 I RTIP
28 D7 I RRING
29 C6 I HRST
30 C7 I MCLK
31 B6 O BPCLK
32 B7 I BIS0
33 A7 I BIS1
34 C5 O TTIP
35 B5 — VSS
36 A6 — VDD
37 B4 O TRING
38 C4 O RPOS
39 A4 O RNEG
40 B3 O RCLK
41 A3 I TPOS
42 B2 I TNEG
43 A2 I TCLK
44 A1 I RT0
DS21348/DS21Q348
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2.1 Pin Descriptions
Table 2-5. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name,
DS21348T Pin Numbering)
NAME PIN I/O FUNCTION
A0 to A4 11 to 7 I
Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 =
1), serves as the address bus. In multiplexed bus operation (BIS1 =
0, BIS0 = 0), these pins are not used and should be tied low.
ALE (AS) 4 I
Address Latch Enable (Address Strobe). When using the parallel
port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to
demultiplex the bus on a positive-going edge. In nonmultiplexed bus
mode (BIS0 = 1), should be tied low.
BIS0/BIS1 32/33 I Bus Interface Select Bits 0 and 1. Used to select bus interface
option. See Table 2-1 for details.
BPCLK 31 O
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
CS 1 I
Chip Select, Active Low. This active-low signal must be low to
read or write to the device.
D0/AD0 to
D7/AD7 19 to 12 I/O
Data Bus/Address/Data Bus. In nonmultiplexed bus operation
(BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus
operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed
address/data bus.
HRST 29 I
Hardware Reset, Active Low. Bringing HRST low resets the
DS21348, setting all control bits to their default state of all zeros.
INT 23 O
Interrupt, Active Low. Flags host controller during conditions and
change of conditions defined in the Status Register. Active low,
open drain output.
MCLK 30 I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
N/A — I Not Assigned. Should be tied low.
PBEO 24 O
PRBS Bit Error Output. The receiver will constantly search for a
215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
DS21348/DS21Q348
15 of 76
NAME PIN I/O FUNCTION
PBTS 44 I
Parallel Bus Type Select. When using the parallel port (BIS1 = 0),
set high to select Motorola bus timing, set low to select Intel bus
timing. This pin controls the function of the RD (DS), ALE (AS),
and WR (R/W) pins. If PBTS = 1 and BIS1 = 0, then these pins
assume the Motorola function listed in parentheses (). In serial port
mode, this pin should be tied low.
RCLK 40 O
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
RD (DS) 2 I
Read Input (Data Strobe), Active Low. DS is active low when in
nonmultiplexed, Motorola mode. See the bus timing diagrams in
Section 11.
RCL/
LOTC 25 O
Receive Carrier Loss/Loss of Transmit Clock. An output which
will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5 µsec ± 2
µsec (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware
mode.
RNEG 39 O
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0)
or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out
of the line interface. Set NRZE (CCR1.6) to a one for NRZ
applications. In NRZ mode, data will be output on RPOS while a
received error will cause a positive-going pulse synchronous with
RCLK at RNEG. See Section 6.4 for details.
RPOS 38 O
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or
the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the
line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In
NRZ mode, data will be output on RPOS while a received error will
cause a positive-going pulse synchronous with RCLK at RNEG. See
Section 6.4 for details.
RTIP/
RRING 27/28 I
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 5
for details.
TCLK 43 I
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter. Can be sourced
internally by MCLK or RCLK. See Common Control Register 1 and
Figure 1-3.
TEST 26 I
Tri-State Control. Set high to tri-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board level testing.
TNEG 42 I
Transmit Negative Data. Sampled on the falling edge (CCR2.1 =
0) or the rising edge (CCR2.1 = 1) of TCLK for data to be
transmitted out onto the line.
TPOS 41 I
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)
or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted
out onto the line.
DS21348/DS21Q348
16 of 76
NAME PIN I/O FUNCTION
TTIP/
TRING 34/37 O
Transmit Tip and Ring [TTIP AND TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line. See
Section 5 for details.
VDD 21/36 — Positive Supply. 3.3V ±5%
VSM 20 I Voltage Supply Mode. Should be low for 3.3V operation.
VSS 22/35 —
Signal Ground
WR (R/W) 3 I
Write Input (Read/Write), Active Low. See the bus timing
diagrams in Section 11.
Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name,
DS21348T Pin Numbering)
NAME PIN I/O FUNCTION
BIS0/BIS1 32/33 I Bus Interface Select Bits 0 and 1. Used to select bus interface
option. See Table 2-1 for details.
BPCLK 31 O
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
CS 1 I
Chip Select, Active Low. Active-low signal must be low to read or
write to the device.
HRST 29 I
Hardware Reset, Active Low. Bringing HRST low will reset the
DS21348 setting all control bits to their default state of all zeros.
ICES 8 I
Input Clock Edge Select. Selects whether the serial port data input
(SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of
SCLK.
INT 23 O
Interrupt, Active Low. Flags host controller during conditions and
change of conditions defined in the Status Register. Active-low,
open-drain output.
MCLK 30 I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
NA — I Not Assigned. Should be tied low.
OCES 9 I
Output Clock Edge Select. Selects whether the serial port data
output (SDO) is valid on the rising (OCES = 1) or falling edge
(OCES = 0) of SCLK.
PBEO 24 O
PRBS Bit Error Output. The receiver will constantly search for a
215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern. Goes
low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to a logic 1.
DS21348/DS21Q348
17 of 76
NAME PIN I/O FUNCTION
RCLK 40 O
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
RCL/LOTC 25 O
Receive Carrier Loss/Loss of Transmit Clock. An output which
will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5µs ± 2µs
(CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware mode.
RNEG 39 O
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0)
or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out
of the line interface. Set NRZE (CCR1.6) to a one for NRZ
applications. In NRZ mode, data will be output on RPOS while a
received error will cause a positive-going pulse synchronous with
RCLK at RNEG. See Section 6.4 for details.
RPOS 38 O
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or
the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the
line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In
NRZ mode, data will be output on RPOS while a received error will
cause a positive-going pulse synchronous with RCLK at RNEG. See
Section 6.4 for details.
RTIP/
RRING 27/28 I
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 5
for details.
SCLK 5 I Serial Clock. Serial bus clock input.
SDI 6 I
Serial Data Input. Sampled on rising edge (ICES = 0) or the falling
edge (ICES = 1) of SCLK.
SDO 7 O
Serial Data Output. Valid on the falling edge (OCES = 0) or the
rising edge (OCES = 1) of SCLK.
TCLK 43 I
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter. Can be sourced
internally by MCLK or RCLK. See Common Control Register 1 and
Figure 1-3.
TEST 26 I
Tri-State Control. Set high to tri-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board-level testing.
TNEG 42 I
Transmit Negative Data. Sampled on the falling edge (CCR2.1 =
0) or the rising edge (CCR2.1 = 1) of TCLK for data to be
transmitted out onto the line.
TPOS 41 I
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)
or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted
out onto the line.
TTIP/TRIN
G 34/37 O
Transmit Tip and Ring [TTIP and TRING]. Analog line-driver
outputs. These pins connect via a step-up transformer to the line.
See Section 5 for details.
VDD 21/36 — Positive Supply. 3.3V ±5%
VSM 20 I Voltage Supply Mode. Should be tied low for 3.3V operation.
VSS 22/35 —
Signal Ground
DS21348/DS21Q348
18 of 76
Table 2-7. Pin Descriptions in Hardware Mode (Sorted By Pin Name,
DS21348T Pin Numbering)
NAME PIN I/O FUNCTION
BIS0/BIS1 32/33 I Bus Interface Select Bits 0 and 1. Used to select bus interface
option. BIS0 = 1 and BIS1 = 1 selects hardware mode.
BPCLK 31 O Backplane Clock. 16.384MHz output.
CES 12 I
Receive and Transmit Clock Edge Select. Selects which RCLK
edge to update RPOS and RNEG and which TCLK edge to sample
TPOS and TNEG.
0 = update RNEG/RPOS on rising edge of RCLK; sample
TPOS/TNEG on falling edge of TCLK
1 = update RNEG/RPOS on falling edge of RCLK; sample
TPOS/TNEG on rising edge of TCLK
DJA 8 I
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
EGL 1 I
Receive Equalizer Gain Limit. This pin controls the sensitivity of
the receive equalizer.
EGL E1 (ETS = 0)
0 = -12dB (short haul)
1 = -43dB (long haul)
EGL T1 (ETS = 1)
0 = -36dB (long haul)
1 = -30dB (limited long haul)
ETS 2 I
E1/T1 Select.
0 = E1
1 = T1
HBE 11 I
Receive and Transmit HDB3/B8ZS Enable
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
HRST 29 I
Hardware Reset. Bringing HRST low will reset the DS21348.
JAMUX 9 I
Jitter Attenuator Mux. Controls the source for JACLK.
See Figure 1-1 and Table 2-13.
E1 (ETS = 0) JAMUX
MCLK = 2.048MHz 0
T1 (ETS = 1)
MCLK = 2.048MHz 1
MCLK = 1.544MHz 0
JAS 10 I
Jitter Attenuator Select
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
L0/L1/L2 7/6/5 I
Transmit LIU Waveshape Select Bits 0 and 1 [H/W Mode].
These inputs determine the waveshape of the transmitter (Table 7-1
and Table 7-2.
LOOP0/
LOOP1 16/17 I
Loopback Select Bits 0 and 1 [H/W Mode]. These inputs
determine the active loopback mode (if any). See Table 2-8.
DS21348/DS21Q348
19 of 76
NAME PIN I/O FUNCTION
MCLK 30 I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional. G.703 requires an accuracy of ±50ppm for
both T1 and E1. TR62411 and ANSI specs require an accuracy of
±32ppm for T1 interfaces.
MM0/MM1 18/19 I Monitor Mode Select Bits 0 and 1 [H/W Mode]. These inputs
determine if the receive equalizer is in a monitor mode (Table 2-11).
NA — I Not Assigned. Should be tied low.
NRZE 3 I
NRZ Enable [H/W Mode]
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
PBEO 24 O
PRBS Bit Error Output. The receiver will constantly search for a
QRSS (T1) or a 215-1 (E1) PRBS depending whether T1 or E1
mode is selected. Remains high if out of synchronization with the
PRBS pattern. Goes low when synchronized to the PRBS pattern.
Any errors in the received pattern after synchronization will cause a
positive going pulse (with same period as E1 or T1 clock)
synchronous with RCLK.
RCLK 40 O
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
RCL 25 O
Receive Carrier Loss. An output which will toggle high during a
receive carrier loss.
RNEG 39 O
Receive Negative Data. Updated on the rising edge (CES = 0) or
the falling edge (CES = 1) of RCLK with the bipolar data out of the
line interface. Set NRZE to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
Section 6.4 for details.
RPOS 38 O
Receive Positive Data. Updated on the rising edge (CES = 0) or the
falling edge (CES = 1) of RCLK with bipolar data out of the line
interface. Set NRZE pin to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
section 6.4 for details.
RT0/RT1 44/23 I Receive LIU Termination Select Bits 0 and 1 [H/W Mode]. These
inputs determine the receive termination. See Table 2-12.
RTIP/
RRING 27/28 I
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 5
for details.
SCLKE 4 I
Receive and Transmit Synchronization Clock Enable
0 = disable 2.048MHz synchronization transmit and receive mode
1 = enable 2.048 Hz synchronization transmit and receive mode
TCLK 43 I
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter.
DS21348/DS21Q348
20 of 76
NAME PIN I/O FUNCTION
TEST 26 I
Tri-State Control. Set high to tri-state all outputs and I/O pins
(including the parallel control port). Set low for normal operation.
Useful in board-level testing.
TNEG 42 I
Transmit Negative Data. Sampled on the falling edge (CES = 0) or
the rising edge (CES = 1) of TCLK for data to be transmitted out
onto the line.
TPD 13 I
Transmit Power-Down
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP and TRING
pins
TPOS 41 I
Transmit Positive Data. Sampled on the falling edge (CES = 0) or
the rising edge (CES = 1) of TCLK for data to be transmitted out
onto the line.
TTIP/TRING 34/37 O
Transmit Tip and Ring [TTIP and TRING]. Analog line driver
outputs. These pins connect via a step-up transformer to the line.
See Section 5 for details.
TX0/TX1 14/15 I Transmit Data Source Select Bits 0 and 1 [H/W Mode]. These
inputs determine the source of the transmit data. See Table 2-9.
VDD 21/36 — Positive Supply. 3.3V ±5%
VSM 20 I Voltage Supply Mode. Should be tied low for 3.3V operation.
VSS 22/35 —
Signal Ground
Note: G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for
T1 interfaces.
DS21348/DS21Q348
21 of 76
Table 2-8. Loopback Control in Hardware Mode
LOOPBACK SYMBOL
CONTROL
BIT LOOP1 LOOP0
Remote Loopback RLB CCR6.6 1 1
Local Loopback LLB CCR6.7 1 0
Analog Loopback ALB CCR6.4 0 1
No Loopback — — 0 0
Table 2-9. Transmit Data Control in Hardware Mode
TRANSMIT DATA SYMBOL CONTROL
BIT TX1 TX0
Transmit Unframed
All Ones TUA1 CCR3.7 1 1
Transmit Alternating
Ones and Zeros TAOZ CCR3.5 1 0
Transmit PRBS TPRBSE CCR3.4 0 1
TPOS and TNEG — — 0 0
Table 2-10. Receive Sensitivity Settings
EGL
(CCR4.4)
ETS
(CCR1.7) RECEIVE SENSITIVITY
0 0 (E1) -12dB (short haul)
1 0 (E1) -43dB (long haul)
1 1 (T1) -30dB (limited long haul)
0 1 (T1) -36dB (long haul)
Table 2-11. Monitor Gain Settings
MM1
(CCR5.5)
MM0
(CCR5.4)
INTERNAL LINEAR
GAIN BOOST (dB)
0 0 Normal operation (no boost)
0 1 20
1 0 26
1 1 32
Table 2-12. Internal Rx Termination Select
RT1
(CCR5.1)
RT0
(CCR5.0)
INTERNAL RECEIVE
TERMINATION CONFIGURATION
0 0 Internal receive-side termination disabled
0 1
Internal receive-side 120Ω enabled
1 0
Internal receive-side 100Ω enabled
1 1
Internal receive-side 75Ω enabled
DS21348/DS21Q348
22 of 76
Table 2-13. MCLK Selection
MCLK
(MHz)
JAMUX
(CCR1.3)
ETS
(CCR1.7)
2.048 0 0
2.048 1 1
1.544 0 1
Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP
Package)
1
C
S
2 RD (DS)
3
W
R (R/
W
)
4 ALE (AS)
5 NA
6 NA
7 A4
8 A3
9 A2
10 A1
11 A0
BIS1 33
BIS0 32
BPCLK 31
MCLK 30
H
RST 29
RRING 28
RTIP 27
TEST 26
RCL/LOTC 25
PBEO 24
I
NT 23
34 TTIP
35 VSS
36 VDD
37 TRING
38 RPOS
39 RNEG
40 RCLK
41 TPOS
42 TNEG
43 TCLK
44 PBTS
VSS 22
VDD 21
VSM 20
A
D0/D0 19
A
D1/D1 18
A
D2/D2 17
A
D3/D3 16
A
D4/D4 15
A
D5/D5 14
A
D6/D6 13
A
D7/D7 12
DS21348
Parallel Port
Operation
(NOTE: TIE ALL NA PINS LOW)
tie low
TIE LOW (MUX) OR HIGH (NONMUX)
TIE LOW
DS21348/DS21Q348
23 of 76
Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package)
1
C
S
2 NA
3 NA
4 NA
5 SCLK
6 SDI
7 SDO
8 ICES
9 OCES
10 NA
11 NA
BIS1 33
BIS0 32
BPCLK 31
MCLK 30
H
RST 29
RRING 28
RTIP 27
TEST 26
RCL/LOTC 25
PBEO 24
I
NT 23
34
TT
IP
35 VSS
36 VDD
37 TRING
38 RPOS
39 RNEG
40 RCLK
41 TPOS
42 TNEG
43 TCLK
44 PBTS
VSS 22
VDD 21
VSM 20
NA 19
NA 18
NA 17
NA 16
NA 15
NA 14
NA 13
NA 12
DS21348
Serial Port
Operation
(NOTE: TIE ALL NA PINS LOW)
TIE HIGH
TIE LOW
TIE LOW
TIE LOW
DS21348/DS21Q348
24 of 76
Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package)
1 EGL
2 ETS
3 NRZE
4 SCLKE
5 L2
6 L1
7 L0
8 DJ
A
9 JAMUX
10 JAS
11 HBE
BIS1 33
BIS0 32
BPCLK 31
MCLK 30
H
RST 29
RRING 28
RTIP 27
TEST 26
RCL 25
PBEO 24
RT1 23
34 TTIP
35 VSS
36 VDD
37 TRING
38 RPOS
39 RNEG
40 RCL
K
41 TPOS
42 TNEG
43 TCL
K
44 RT0
VSS 22
VDD 21
VSM 20
MM1 19
MM0 18
LOOP1 17
LOOP0 16
TX1 15
TX0 14
TPD 13
CES 12
DS21348
Hardware
Operation
TIE HIGH
TIE HIGH
TIE LOW
DS21348/DS21Q348
25 of 76
3. HARDWARE MODE
In hardware mode (BIS1 = 1, BIS0 = 1), pins 1–19, 23, 25, 31, and 44 are redefined to be used for
initializing the DS21348. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. The
RCL/LOTC (pin 25) is designated to RCL when in hardware mode. JABDS (CCR4.2) defaults to logic 0.
The RHBE (CCR2.3) and THBE (CCR2.2) control bits are combined and controlled by HBE at pin 11
while the RSCLKE (CCR5.3) and TSCLKE (CCR5.2) bits are combined and controlled by SCLKE at
pin 4. TCES (CCR2.1) and RCES (CCR2.0) are combined and controlled by CES at pin 12. The
transmitter functions are combined and controlled by TX1 (pin 15) and TX0 (pin 14). The loopback
functions are controlled by LOOP1 (pin 17) and LOOP0 (pin 16). All other control bits default to the
logic 0 setting.
3.1 Register Map
Table 3-1. Register Map
NAME REGISTER R/W
PARALLEL
PORT MODE
SERIAL PORT
MODE
(Notes 2 to 5)
(msb) (lsb)
CCR1 Common Control Register 1 R/W 00h B000 000A
CCR2 Common Control Register 2 R/W 01h B000 001A
CCR3 Common Control Register 3 R/W 02h B000 010A
CCR4 Common Control Register 4 R/W 03h B000 011A
CCR5 Common Control Register 5 R/W 04h B000 100A
CCR6 Common Control Register 6 R/W 05h B000 101A
SR Status Register R 06h B000 110A
IMR Interrupt Mask Register R/W 07h B000 111A
RIR1 Receive Information Register 1 R 08h B001 000A
RIR2 Receive Information Register 2 R 09h B001 001A
IBCC In-Band Code Control Register R/W 0Ah B001 010A
TCD1 Transmit Code Definition Register 1 R/W 0Bh B001 011A
TCD2 Transmit Code Definition Register 2 R/W 0Ch B001 100A
RUPCD1 Receive Up Code Definition Register 1 R/W 0Dh B001 101A
RUPCD2 Receive Up Code Definition Register 2 R/W 0Eh B001 110A
RDNCD1 Receive Down Code Definition Register 1 R/W 0Fh B001 111A
RDNCD2 Receive Down Code Definition Register 2 R/W 10h B010 000A
ECR1 Error Count Register 1 R 11h B010 001A
ECR2 Error Count Register 2 R 12h B010 010A
TEST1 Test 1 R/W 13h B010 011A
TEST2 Test 2 R/W 14h B010 100A
TEST3 Test 3 R/W 15h B010 101A
— — — (Note 1) —
Note 1: Register addresses 16h to 1Fh do not exist.
Note 2: In the Serial Port Mode, the LSB is on the right hand side.
Note 3: In the Serial Port Mode, data is read and written LSB first.
Note 4: In the Serial Port Mode, the A bit (the LSB) determines whether the access is a read (A = 1) or a write (A = 0).
Note 5: In the Serial Port Mode, the B bit (the MSB) determines whether the access is a burst access (B = 1) or a single register
access (B = 0).
DS21348/DS21Q348
26 of 76
3.2 Parallel Port Operation
When using the parallel interface on the DS21348 (BIS1 = 0) the user has the option for either
multiplexed bus operation (BIS1 = 0, BIS0 = 0) or non-multiplexed bus operation (BIS1 = 0, BIS0 = 1).
The DS21348 can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is tied
low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals
are listed in parentheses (). See the timing diagrams in Section 11 for more details.
3.3 Serial Port Operation
Setting BIS1 = 1 and BIS0 = 0 enables the serial bus interface on the DS21348. Port read/write timing is
unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host.
See Section 11 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 3-1,
Figure 3-2, Figure 3-3, and Figure 3-4 for more details.
Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSB) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next 5 bits identify the register address. Bit 7 is reserved and must
be set to 0 for proper operation.
The last bit (MSB) of the address/command byte is the burst mode bit. When the burst bit is enabled
(B = 1) and a READ operation is performed, addresses 0 through 15h are read sequentially, starting at
address 0h. And when the burst bit is enabled and a WRITE operation is performed, addresses 0 through
16h are written sequentially, starting at address 0h. Burst operation is stopped once address 15h is read.
See Figure 3-5 and Figure 3-6 for more details.
All data transfers are initiated by driving the CS input low. When Input Clock-Edge Select (ICES) is low,
input data is latched on the rising edge of SCLK and when ICES is high, input data is latched on the
falling edge of SCLK. When Output Clock-Edge Select (OCES) is low, data is output on the falling edge
of SCLK and when OCES is high, data is output on the rising edge of SCLK. Data is held until the next
falling or rising edge. All data transfers are terminated if the CS input transitions high. Port control logic
is disabled and SDO is tri-stated when CS is high.
DS21348/DS21Q348
27 of 76
Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1
ICES = 1 (sample SDI on the falling edge of SCLK)
OCES = 1 (update SDO on rising edge of SCLK)
Figure 3-2. Serial Port Operation for Read Access Mode 2
ICES = 1 (sample SDI on the falling edge of SCLK)
OCES = 0 (update SDO on falling edge of SCLK)
Figure 3-3. Serial Port Operation for Read Access Mode 3
ICES = 0 (sample SDI on the rising edge of SCLK)
OCES = 0 (update SDO on falling edge of SCLK)
12345678910111213141516
1
A
0
A
1
A
2
A
32
A
40B
D1 D2 D3 D4 D5 D6
SCL
K
SDI
SDO
C
S
(lsb) (msb)
D0
(lsb)
D7
(msb)
READ ACCESS ENABLED
12345678910111213141516
1
A
0
A
1
A
2
A
3
A
40 B
D1 D2 D3 D4 D5 D6
SCL
K
SDI
SDO
C
S
(lsb) (msb)
D0
(lsb)
D7
(msb)
12345678910111213141516
1
A
0
A
1
A
2
A
3
A
40 B
D1 D2 D3 D4 D5 D6
SCL
K
SDI
SDO
C
S
(lsb) (msb)
D0
(lsb)
D7
(msb)
DS21348/DS21Q348
28 of 76
Figure 3-4. Serial Port Operation for Read Access Mode 4
ICES = 0 (sample SDI on the rising edge of SCLK)
OCES = 1 (update SDO on rising edge of SCLK)
Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2
ICES = 1 (sample SDI on the falling edge of SCLK)
Figure 3-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4
ICES = 0 (sample SDI on the rising edge of SCLK)
12345678910111213141516
D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0D0
1
A
0
A
1
A
2
A
3A5
A
40B
D0D0D0D0 D0
SCL
K
SDI
SDO
C
S
(lsb) (msb)
(lsb) (msb)
D1 D2 D3 D4 D5 D6 D0 D7
12345678910111213141516SCL
K
C
S
0
A
0
A
1
A
2
A
3
A
40B
(msb)
SDI
SDO
D1 D2 D3 D4 D5 D7
(lsb) (msb)
D0 D6
(lsb)
WRITE ACCESS ENABLED
12345678910 111213141516SCL
K
C
S
0
A
0
A
1
A
2
A
3
A
40B
(msb)
SDI
SDO
D1 D2 D3 D4 D5 D7
(lsb) (msb)
D0 D6
(lsb)
WRITE ACCESS ENABLED
DS21348/DS21Q348
29 of 76
4. CONTROL REGISTERS
CCR1 (00H): COMMON CONTROL REGISTER 1
(MSB)
(LSB)
ETS NRZE RCLA ECUE JAMUX TTOJ TTOR LOTCMC
SYMBOL POSITION DESCRIPTION
ETS CCR1.7
E1/T1 Select.
0 = E1
1 = T1
NRZE CCR1.6
NRZ Enable.
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive
going pulse when device receives a BPV, CV, or EXZ. See Figure 1-2
and Figure 1-3.
RCLA CCR1.5
Receive Carrier Loss Alternate Criteria.
0 = RCL declared upon 255 (E1) or 192 (T1) consecutive zeros
1 = RCL declared upon 2048 (E1) or 1544 (T1) consecutive zeros
ECUE CCR1.4 Error Counter Update Enable. A 0 to 1 transition forces the next clock
cycle to load the error counter registers with the latest counts and reset
the counters. The user must wait a minimum of two clocks cycles (976ns
for E1 and 1296ns for T1) before reading the error count registers to
allow for a proper update. See Section 4 and Figure 1-2 for details.
JAMUX CCR1.3 Jitter Attenuator MUX. Controls the source for JACLK (Figure 1-1).
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
TTOJ CCR1.2 TCLK to JACLK. Internally connects TCLK to JACLK (Figure 1-3).
0 = disabled
1 = enabled
TTOR CCR1.1 TCLK to RCLK. Internally connects TCLK to RCLK (Figure 1-3).
0 = disabled
1 = enabled
LOTCMC CCR1.0 Loss Of Transmit Clock Mux Control. Determines whether the
transmit logic should switch to JACLK if the TCLK input should fail to
transition (Figure 1-3).
0 = do not switch to JACLK if TCLK stops
1 = switch to JACLK if TCLK stops
DS21348/DS21Q348
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Table 4-1. MCLK Selection
MCLK
(MHz)
JAMUX
(CCR1.3)
ETS
(CCR1.7)
2.048 0 0
2.048 1 1
1.544 0 1
CCR2 (01H): COMMON CONTROL REGISTER 2
(MSB)
(LSB)
P25S n/a SCLD CLDS RHBE THBE TCES RCES
SYMBOL POSITION DESCRIPTION
P25S CCR2.7 Pin 25 Select. Forced to logic 0 in hardware mode.
0 = toggles high during a Receive Carrier Loss condition
1 = toggles high if TCLK does not transition for at least 5µs
- CCR2.6
Not Assigned. Should be set to zero when written to.
SCLD CCR2.5 Short Circuit Limit Disable (ETS = 0). Controls the 50 mA (rms)
current limiter.
0 = enable 50 mA current limiter
1 = DISABLE 50 MA CURRENT LIMITER
CLDS CCR2.4 Custom Line Driver Select. Setting this bit to a one will redefine the
operation of the transmit line driver. When this bit is set to a one and
CCR4.5 = CCR4.6 = CCR4.7 = 0, then the device will generate a square
wave at the TTIP and TRING outputs instead of a normal waveform.
When this bit is set to a one and CCR4.5 = CCR4.6 = CCR4.7 ≠ 0, then
the device will force TTIP and TRING outputs to become open drain
drivers instead of their normal push-pull operation. This bit should be set
to zero for normal operation of the device. Contact the factory for more
details on how to use this bit.
RHBE CCR2.3 Receive HDB3/B8ZS Enable. See Figure 1-2.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
THBE CCR2.2 Transmit HDB3/B8ZS Enable. See Figure 1-3.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
TCES CCR2.1 Transmit Clock Edge Select. Selects which TCLK edge to sample TPOS
and TNEG. See Figure 1-3.
0 = sample TPOS and TNEG on falling edge of TCLK
1 = sample TPOS and TNEG on rising edge of TCLK
RCES CCR2.0 Receive Clock Edge Select. Selects which RCLK edge to update RPOS
and RNEG. See Figure 1-2.
0 = update RPOS and RNEG on rising edge of RCLK
1 = update RPOS and RNEG on falling edge of RCLK
DS21348/DS21Q348
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CCR3 (02H): COMMON CONTROL REGISTER 3
(MSB)
(LSB)
TUA1 ATUA1 TAOZ TPRBSE TLCE LIRST IBPV IBE
SYMBOL POSITION DESCRIPTION
TUA1 CCR3.7 Transmit Unframed All Ones. The polarity of this bit is set such that the
device will transmit an all ones pattern on power-up or device reset. This
bit must be set to a one to allow the device to transmit data. The
transmission of this data pattern is always timed off of the JACLK (See
Figure 1-1).
0 = transmit all ones at TTIP and TRING
1 = transmit data normally
ATUA1 CCR3.6 Automatic Transmit Unframed All Ones. Automatically transmit an
unframed all ones pattern at TTIP and TRING during a receive carrier loss
(RCL) condition or receive all ones condition.
0 = disabled
1 = enabled
TAOZ CCR3.5 Transmit Alternate Ones and Zeros. Transmit a …101010… pattern at
TTIP and TRING. The transmission of this data pattern is always timed
off of TCLK (Figure 1-1).
0 = disabled
1 = enabled
TPRBSE CCR3.4 Transmit PRBS Enable. Transmit a 215 - 1 (E1) or a 220 - 1 (T1) PRBS at
TTIP and TRING (Figure 1-3).
0 = disabled
1 = enabled
TLCE CCR3.3 Transmit Loop Code Enable. Enables the transmit side to transmit the
loop up code in the Transmit Code Definition registers (TCD1 and
TCD2). See Section 4 and Figure 1-3 for details.
0 = disabled
1 = enabled
LIRST CCR3.2 Line Interface Reset. Setting this bit from a zero to a one will initiate an
internal reset that resets the clock recovery state machine and re-centers
the jitter attenuator. Normally this bit is only toggled on power-up. Must
be cleared and set again for a subsequent reset.
IBPV CCR3.1 Insert BPV. A 0 to 1 transition on this bit will cause a single BiPolar
Violation (BPV) to be inserted into the transmit data stream. Once this bit
has been toggled from a 0 to a 1, the device waits for the next occurrence
of three consecutive ones to insert the BPV. This bit must be cleared and
set again for a subsequent error to be inserted (Figure 1-3).
IBE CCR3.0 Insert Bit Error. A 0 to 1 transition on this bit will cause a single logic
error to be inserted into the transmit data stream. This bit must be cleared
and set again for a subsequent error to be inserted (Figure 1-3).
DS21348/DS21Q348
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4.1 Device Power-Up and Reset
The DS21348 will reset itself upon power-up setting all writeable registers to 00h and clear the status and
information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the
power supplies have settled following power-up, initialize all control registers to the desired settings, then
toggle the LIRST bit (CCR3.2). At anytime, the DS21348 can be reset to the default settings by bringing
HRST (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
(MSB)
(LSB)
L2 L1 L0 EGL JAS JABDS DJA TPD
SYMBOL POSITION DESCRIPTION
L2 CCR4.7 Line Build Out Select Bit 2. Sets the transmitter build out; see Table 7-1
for E1 and Table 7-2 for T1.
L1 CCR4.6 Line Build Out Select Bit 1. Sets the transmitter build out; see Table 7-1
for E1 and Table 7-2 for T1.
L0 CCR4.5 Line Build Out Select Bit 0. Sets the transmitter build out; see Table 7-1
for E1 and Table 7-2 for T1.
EGL CCR4.4 Receive Equalizer Gain Limit. This bit controls the sensitivity of the
receive equalizer. See Table 4-2.
JAS CCR4.3
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
JABDS CCR4.2
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay-sensitive applications)
DJA CCR4.1
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPD CCR4.0
Transmit Power-Down.
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP and TRING pins
Table 4-2. Receive Equalizer Sensitivity Settings
EGL
(CCR4.4)
ETS
(CCR1.7)
RECEIVE
SENSITIVITY
0 0 (E1) -12dB (short haul)
1 0 (E1) -43dB (long haul)
1 1 (T1) -30dB (limited long haul)
0 1 (T1) -36dB (long haul)
DS21348/DS21Q348
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CCR5 (04H): COMMON CONTROL REGISTER 5
(MSB)
(LSB)
BPCS1 BPCS0 MM1 MM0 RSCLKE TSCLKE RT1 RT0
SYMBOL POSITION DESCRIPTION
BPCS1 CCR5.7 Backplane Clock Select 1. See Table 4-3 for details.
BPCS0 CCR5.6 Backplane Clock Select 0. See Table 4-3 for details
MM1 CCR5.5 Monitor Mode 1. See Table 4-4.
MM0 CCR5.4 Monitor Mode 0. See Table 4-4.
RSCLKE CCR5.3
Receive Synchronization Clock Enable.
This control bit determines whether the line receiver should handle normal
T1/E1 signals or a synchronization signal.
E1 mode:
0 = receive normal E1 signal (Section 6 of G.703)
1 = receive 2.048MHz synchronization signal (Section 10 of G.703)
T1 mode:
0 = receive normal T1 signal
1 = receive 1.544MHz synchronization signal
TSCLKE CCR5.2
Transmit Synchronization Clock Enable.
This control bit determines whether the transmitter should transmit normal
T1/E1 signals or a synchronized signal.
E1 mode:
0 = transmit normal E1 signal (Section 6 of G.703)
1 = transmit 2.048MHz synchronization signal (Section 10 of G.703)
T1 mode:
0 = transmit normal T1 signal
1 = transmit 1.544MHz synchronization signal
RT1 CCR5.1 Receive Termination 1. See Table 4-5 for details.
RT0 CCR5.0 Receive Termination 0. See Table 4-5 for details.
DS21348/DS21Q348
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Table 4-3. Backplane Clock Select
BPCS1
(CCR5.7)
BPCS0
(CCR5.6)
BPCLK
FREQUENCY
0 0 16.384MHz
0 1 8.192MHz
1 0 4.096MHz
1 1 2.048MHz
Table 4-4. Monitor Gain Settings
MM1
(CCR5.5)
MM0
(CCR5.4)
INTERNAL LINEAR
GAIN BOOST
0 0
Normal operation
(no boost)
0 1 20dB
1 0 26dB
1 1 32dB
Table 4-5. Internal Rx Termination Select
RT1
(CCR5.1)
RT0
(CCR5.0)
INTERNAL RECEIVE
TERMINATION CONFIGURATION
0 0 Internal receive-side termination disabled
0 1
Internal receive-side 120Ω enabled
1 0
Internal receive-side 100Ω enabled
1 1
Internal receive-side 75Ω enabled
DS21348/DS21Q348
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CCR6 (05H): COMMON CONTROL REGISTER 6
(MSB)
(LSB)
LLB RLB ARLBE ALB RJAB ECRS2 ECRS1 ECRS0
SYMBOL POSITION DESCRIPTION
LLB CCR6.7 Local Loopback. In Local Loopback (LLB), transmit data will be looped back
to the receive path passing through the jitter attenuator if it is enabled. Data in
the transmit path will act as normal. See Figure 1-1 and Section 6.2.2 for
details.
0 = loopback disabled
1 = loopback enabled
RLB CCR6.6 Remote Loopback. In Remote Loopback (RLB), data output from the
clock/data recovery circuitry will be looped back to the transmit path passing
through the jitter attenuator if it is enabled. Data in the receive path will act as
normal while data presented at TPOS and TNEG will be ignored.
See Figure 1-1 and Section 6.2.1 for details.
0 = loopback disabled
1 = loopback enabled
ARLBE CCR6.5 Automatic Remote Loopback Enable and Reset. When this bit is set high,
the device will automatically go into remote loopback when it detects loop up
code programmed into the Receive Loop-Up Code Definition Registers
(RUPCD1 and RUPCD2) for a minimum of 5 seconds and it will also set the
RIR2.1 status bit. Once in a RLB state, it will remain in this state until it has
detected the loop code programmed into the Receive Loop-Down Code
Definition Registers (RDNCD1 and RDNCD2) for a minimum of 5 seconds at
which point it will force the device out of RLB and clear RIR2.1. The
automatic RLB circuitry can be reset by toggling this bit from a 1 to a 0. The
action of the automatic remote loopback circuitry is logically ORed with the
RLB (CCR6.6) control bit (i.e., either one can cause a RLB to occur).
ALB CCR6.4 Analog Loopback. In Analog Loopback (ALB), signals at TTIP and TRING
will be internally connected to RTIP and RRING. The incoming signals, from
the line, at RTIP and RRING will be ignored. The signals at TTIP and TRING
will be transmitted as normal. See Figure 1-1 and Section 6.2.3 for more details.
0 = loopback disabled
1 = loopback enabled
RJAB CCR6.3 RCLK Jitter Attenuator Bypass. This control bit allows the receive recovered
clock and data to bypass the jitter attenuation while still allowing the BPCLK
output to use the jitter attenuator. See Figure 1-1 and Section 7.3 for details.
0 = disabled
1 = enabled
ECRS2 CCR6.2 Error Count Register Select 2. See Section 6.4 for details.
ECRS1 CCR6.1 Error Count Register Select 1. See Section 6.4 for details.
ECRS0 CCR6.0 Error Count Register Select 0. See Section 6.4 for details.
DS21348/DS21Q348
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5. STATUS REGISTERS
There are three registers that contain information on the current real-time status of the device, Status
Register (SR) and Receive Information Registers 1 and 2 (RIR1/RIR2). When a particular event has
occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of
the bits in SR, RIR1, and RIR2 are latched bits and some are real time bits. The register descriptions
below list which status bits are latched and which are real time bits. For latched status bits, when an event
or an alarm occurs the bit is set to a one and will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again. Two of the latched
status bits (RUA1 and RCL) will remain set after reading if the alarm is still present.
The user will always precede a read of any of the three status registers with a write. The byte written to
the register will inform the DS21348 which bits the user wishes to read and have cleared. The user will
write a byte to one of these registers with a one in the bit positions to be read and a zero in the other bit
positions. When a one is written to a bit location, that location will be updated with the latest information.
When a zero is written to a bit position, that bit position will not be updated and the previous value will
be held. A write to the status and information registers will be immediately followed by a read of the
same register. The read result should be logically ANDed with the mask byte that was just written and
this value should be written back into the same register to insure that bit does indeed clear. This second
write step is necessary because the alarms and events in the status registers occur asynchronously with
respect to their access via the parallel port. This write-read-write scheme allows an external
microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the
register. This operation is key in controlling the DS21348 with higher-order software languages.
The bits in the SR register have the unique ability to initiate a hardware interrupt via the INT output pin.
Each of the alarms and events in the SR can be either masked or unmasked from the interrupt pin via the
Interrupt Mask Register (IMR). The interrupts caused by the RCL, RUA1, and LOTC bits in SR act
differently than the interrupts caused by the other status bits in SR. The RCL, RUA1 and LOTC bits will
force the INT pin low whenever they change state (i.e., go active or inactive). The INT pin will be
allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the
interrupt to occur even if the alarm is still present. The other status bits in SR can force the INT pin low
when they are set. The INT pin will be allowed to return high (if no other interrupts are present) when the
user reads the event bit that caused the interrupt to occur.
Table 5-1. Received Alarm Criteria
ALARM E1/T1 SET CRITERIA CLEAR CRITERIA
RUA1 E1 Less than 2 zeros in two frames (512 bits) More than 2 zeros in two frames (512
bits)
RUA1 T1
Over a 3ms window, five or fewer zeros
are received
Over a 3ms window, six or more zeros
are received
RCL1 E1 255 (or 2048)2 consecutive zeros received
(G.775)
In 255 bit times, at least 32 ones are
received
RCL1 T1 192 (or 1544)2 consecutive zeros are
received
14 or more ones out of 112 possible
bit positions are received starting with
the first one received
Note 1: Receive carrier loss (RCL) is also known as loss of signal (LOS) or Red Alarm in T1.
Note 2: See CCR1.5 for details.
DS21348/DS21Q348
37 of 76
SR (06H): STATUS REGISTER
(MSB)
(LSB)
LUP LDN LOTC RUA1 RCL TCLE TOCD PRBSD
SYMBOL POSITION DESCRIPTION
LUP
(latched)
SR.7 Loop-Up Code Detected. Set when the loop-up code defined in registers
RUPCD1 and RUPCD2 is being received. See Section 4 for details.
LDN
(latched)
SR.6 Loop-Down Code Detected. Set when the loop-down code defined in
registers RDNCD1 and RDNCD2 is being received. See Section 4 for
details.
LOTC
(real time)
SR.5 Loss of Transmit Clock. Set when the TCLK pin has not transitioned for
5µsec (±2µs). Will force the LOTC pin high.
RUA1
(latched)
SR.4 Receive Unframed All Ones. Set when an unframed all ones code is
received at RRING and RTIP. See Table 5-1 for details.
RCL
(latched)
SR.3 Receive Carrier Loss. Set when a receive carrier loss condition exists at
RRING and RTIP. See Table 5-1 for details.
TCLE
(real time)
SR.2 Transmit Current Limit Exceeded. Set when the 50mA (RMS) current
limiter is activated whether the current limiter is enabled or not.
TOCD
(real time)
SR.1 Transmit Open Circuit Detect. Set when the device detects that the TTIP
and TRING outputs are open circuited.
PRBSD
(real time)
SR.0 PRBS Detect. Set when the receive-side detects a 215 - 1 (E1) or a 220 - 1
(T1) Pseudo-Random Bit Sequence (PRBS).
DS21348/DS21Q348
38 of 76
IMR (07H): INTERRUPT MASK REGISTER
(MSB)
(LSB)
LUP LDN LOTC RUA1 RCL TCLE TOCD PRBSD
SYMBOL POSITION DESCRIPTION
LUP IMR.7
Loop-Up Code Detected.
0 = interrupt masked
1 = interrupt enabled
LDN IMR.6
Loop-Down Code Detected.
0 = interrupt masked
1 = interrupt enabled
LOTC IMR.5
Loss of Transmit Clock.
0 = interrupt masked
1 = interrupt enabled
RUA1 IMR.4
Receive Unframed All Ones.
0 = interrupt masked
1 = interrupt enabled
RCL IMR.3
Receive Carrier Loss.
0 = interrupt masked
1 = interrupt enabled
TCLE IMR.2
Transmit Current Limiter Exceeded.
0 = interrupt masked
1 = interrupt enabled
TOCD IMR.1
Transmit Open Circuit Detect.
0 = interrupt masked
1 = interrupt enabled
PRBSD IMR.0
PRBS Detection.
0 = interrupt masked
1 = interrupt enabled
DS21348/DS21Q348
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RIR1 (08H): RECEIVE INFORMATION REGISTER 1
(MSB)
(LSB)
ZD 16ZD HBD RCLC RUA1C JALT n/a n/a
SYMBOL POSITION DESCRIPTION
ZD
(latched)
RIR1.7 Zero Detect. Set when a string of at least four (ETS = 0) or eight
(ETS = 1) consecutive zeros (regardless of the length of the string)
have been received. Will be cleared when read.
16ZD
(latched)
RIR1.6 Sixteen Zero Detect. Set when at least 16 consecutive zeros
(regardless of the length of the string) have been received. Will be
cleared when read.
HBD
(latched)
RIR1.5 HDB3/B8ZS Word Detect. Set when an HDB3 (ETS = 0) or B8ZS
(ETS = 1) code word is detected independent of whether the receive
HDB3/B8ZS mode (CCR4.6) is enabled. Will be cleared when read.
Useful for automatically setting the line coding.
RCLC
(latched)
RIR1.4 Receive Carrier Loss Clear. Set when the RCL alarm has met the
clear criteria defined in Table 5-1. Will be cleared when read.
RUA1C
(latched)
RIR1.3 Receive Unframed All Ones Clear. Set when the unframed all ones
signal is no longer detected. Will be cleared when read (Table 5-1).
JALT
(latched)
RIR1.2 Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO
reaches to within 4 bits of its useful limit. Will be cleared when read.
Useful for debugging jitter attenuation operation.
N/A RIR1.1 Not Assigned. Could be any value when read.
N/A RIR1.0 Not Assigned. Could be any value when read.
DS21348/DS21Q348
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RIR2 (09H): RECEIVE INFORMAION REGISTER 2
(MSB)
(LSB)
RL3 RL2 RL1 RL0 N/A N/A ARLB SEC
SYMBOL POSITION DESCRIPTION
RL3
(real time)
RIR2.7 Receive Level Bit 3. See Table 5-2.
RL2
(real time)
RIR2.6 Receive Level Bit 2. See Table 5-2.
RL1
(real time)
RIR2.5 Receive Level Bit 1. See Table 5-2.
RL0
(real time)
RIR2.4 Receive Level Bit 0. See Table 5-2.
N/A RIR2.3 Not Assigned. Could be any value when read.
N/A RIR2.2 Not Assigned. Could be any value when read.
ARLB
(real time)
RIR2.1 Automatic Remote Loopback Detected. This bit will be set to a one
when the automatic Remote Loopback (RLB) circuitry has detected
the presence of a loop up code for 5 seconds. It will remain set until
the automatic RLB circuitry has detected the loop down code for 5
seconds. See Section 4 for more details. This bit will be forced low
when the automatic RLB circuitry is disabled (CCR6.5 = 0).
SEC
(latched)
RIR2.0 One-Second Timer. This bit will be set to a one on one-second
boundaries as timed by the device based on the RCLK. It will be
cleared when read.
Table 5-2. Receive Level Indication
RL3 RL2 RL1 RL0 RECEIVE LEVEL (dB)
0 0 0 0 < -2.5
0 0 0 1 -2.5 to -5.0
0 0 1 0 -5.0 to -7.5
0 0 1 1 -7.5 to -10.0
0 1 0 0 -10.0 to -12.5
0 1 0 1 -12.5 to -15.0
0 1 1 0 -15.0 to -17.5
0 1 1 1 -17.5 to -20.0
1 0 0 0 -20.0 to -22.5
1 0 0 1 -22.5 to -25.0
1 0 1 0 -25.0 to -27.5
1 0 1 1 -27.5 to -30.0
1 1 0 0 -30.0 to -32.5
1 1 0 1 -32.5 to -35.0
1 1 1 0 -35.0 to -37.5
1 1 1 1 > -37.5
DS21348/DS21Q348
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6. DIAGNOSTICS
6.1 In-Band Loop Code Generation and Detection
The DS21348 can generate and detect a repeating bit pattern that is from one to eight or sixteen bits in
length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition
(TCD1 and TCD2) registers and select the proper length of the pattern by setting the TC0 and TC1 bits in
the In-Band Code Control (IBCC) register. When generating a 1, 2, 4, 8, or 16 bit pattern both the
transmit code registers (TCD1 and TCD2) must be filled with the proper code. Generation of a 1, 3, 5, or
7-bit pattern only requires TCD1 to be filled. Once this is accomplished, the pattern will be transmitted as
long as the TLCE control bit (CCR3.3) is enabled. As an example, if the user wished to transmit the
standard “loop up” code for Channel Service Units which is a repeating pattern of ...10000100001... then
80h would be loaded into TCD1 and the length would set using TC1 and TC0 in the IBCC register to 5
bits.
The DS21348 can detect two separate repeating patterns to allow for both a “loop up” code and a “loop
down” code to be detected. The user will program the codes to be detected in the Receive Up Code
Definition (RUPCD1 and RUPCD2) registers and the Receive Down Code Definition (RDNCD1 and
RDNCD2) registers and the length of each pattern will be selected via the IBCC register. The DS21348
will detect repeating pattern codes with bit error rates as high as 1x10-2. The code detector has a nominal
integration period of 48ms, hence, after about 48ms of receiving either code, the proper status bit (LUP at
SR.7 and LDN at SR.6) will be set to a one. Normally codes are sent for a period of 5 seconds. It is
recommended that the software poll the DS21348 every 100ms to 1000ms until 5 seconds has elapsed to
insure that the code is continuously present.
IBCC (0AH): IN-BAND CODE CONTROL REGISTER
(MSB)
(LSB)
TC1 TC0 RUP2 RUP1 RUP0 RDN2 RDN1 RDN0
SYMBOL POSITION DESCRIPTION
TC1 IBCC.7 Transmit Code Length Definition Bit 1. See Table 6-1.
TC0 IBCC.6 Transmit Code Length Definition Bit 0. See Table 6-1.
RUP2 IBCC.5 Receive Up Code Length Definition Bit 2. See Table 6-2.
RUP1 IBCC.4 Receive Up Code Length Definition Bit 1. See Table 6-2.
RUP0 IBCC.3 Receive Up Code Length Definition Bit 0. See Table 6-2.
RDN2 IBCC.2 Receive Down Code Length Definition Bit 2. See Table 6-2.
RDN1 IBCC.1 Receive Down Code Length Definition Bit 1. See Table 6-2.
RDN0 IBCC.0 Receive Down Code Length Definition Bit 0. See Table 6-2.
Table 6-1. Transmit Code Length
DS21348/DS21Q348
42 of 76
TC1 TC0
LENGTH SELECTED
(BITS)
0 0 5
0 1 6/3
1 0 7
1 1 16/8/4/2/1
Table 6-2. Receive Code Length
RUP2/RDN2 RUP1/ RDN1 RUP0/RDN0 LENGTH
SELECTED (BITS)
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 16/8
TCD1 (0BH): TRANSMIT CODE DEFINITION REGISTER 1
(MSB)
(LSB)
C7 C6 C5 C4 C3 C2 C1 C0
SYMBOL POSITION DESCRIPTION
C7 TCD1.7 Transmit Code Definition Bit 7. First bit of the repeating
pattern.
C6 TCD1.6
Transmit Code Definition Bit 6.
C5 TCD1.5
Transmit Code Definition Bit 5.
C4 TCD1.4
Transmit Code Definition Bit 4.
C3 TCD1.3
Transmit Code Definition Bit 3.
C2 TCD1.2 Transmit Code Definition Bit 2. A Don’t Care if a 5-bit
length is selected.
C1 TCD1.1 Transmit Code Definition Bit 1. A Don’t Care if a 5-bit or 6-
bit length is selected.
C0 TCD1.0 Transmit Code Definition Bit 0. A Don’t Care if a 5-bit, 6-
bit, or 7-bit length is selected.
DS21348/DS21Q348
43 of 76
TCD2 (0CH): TRANSMIT CODE DEFINITION REGISTER 2
(MSB)
(LSB)
C15 C14 C13 C12 C11 C10 C9 C8
SYMBOL POSITION DESCRIPTION
C15 TCD2.7
Transmit Code Definition Bit 15
C14 TCD2.6
Transmit Code Definition Bit 14
C13 TCD2.5
Transmit Code Definition Bit 13
C12 TCD2.4
Transmit Code Definition Bit 12
C11 TCD2.3
Transmit Code Definition Bit 11
C10 TCD2.2
Transmit Code Definition Bit 10
C9 TCD2.1
Transmit Code Definition Bit 9
C8 TCD2.0
Transmit Code Definition Bit 8
RUPCD1 (0DH): RECEIVE UP CODE DEFINITION REGISTER 1
(MSB)
(LSB)
C7 C6 C5 C4 C3 C2 C1 C0
SYMBOL POSITION DESCRIPTION
C7 RUPCD1.7 Receive Up Code Definition Bit 7. First bit of the repeating
pattern.
C6 RUPCD1.6 Receive Up Code Definition Bit 6. A Don’t Care if a 1-bit
length is selected.
C5 RUPCD1.5 Receive Up Code Definition Bit 5. A Don’t Care if a 1-bit or
2-bit length is selected.
C4 RUPCD1.4 Receive Up Code Definition Bit 4. A Don’t Care if a 1-bit to
3-bit length is selected.
C3 RUPCD1.3 Receive Up Code Definition Bit 3. A Don’t Care if a 1-bit to
4-bit length is selected.
C2 RUPCD1.2 Receive Up Code Definition Bit 2. A Don’t Care if a 1-bit to
5-bit length is selected.
C1 RUPCD1.1 Receive Up Code Definition Bit 1. A Don’t Care if a 1-bit to
6-bit length is selected.
C0 RUPCD1.0 Receive Up Code Definition Bit 0. A Don’t Care if a 1-bit to
7-bit length is selected.
DS21348/DS21Q348
44 of 76
RUPCD2 (0EH): RECEIVE UP CODE DEFINITION REGISTER 2
(MSB)
(LSB)
C15 C14 C13 C12 C11 C10 C9 C8
SYMBOL POSITION DESCRIPTION
C15 RUPCD2.7
Receive Up Code Definition Bit 15
C14 RUPCD2.6
Receive Up Code Definition Bit 14
C13 RUPCD2.5
Receive Up Code Definition Bit 13
C12 RUPCD2.4
Receive Up Code Definition Bit 12
C11 RUPCD2.3
Receive Up Code Definition Bit 11
C10 RUPCD2.2
Receive Up Code Definition Bit 10
C9 RUPCD2.1
Receive Up Code Definition Bit 9
C8 RUPCD2.0
Receive Up Code Definition Bit 8
RDNCD1 (0FH): RECEIVE DOWN CODE DEFINITION REGISTER 1
(MSB)
(LSB)
C7 C6 C5 C4 C3 C2 C1 C0
SYMBOL POSITION DESCRIPTION
C7 RDNCD1.7 Receive Down Code Definition Bit 7. First bit of the
repeating pattern.
C6 RDNCD1.6 Receive Down Code Definition Bit 6. A Don’t Care if a 1-bit
length is selected.
C5 RDNCD1.5 Receive Down Code Definition Bit 5. A Don’t Care if a 1-bit
or 2-bit length is selected.
C4 RDNCD1.4 Receive Down Code Definition Bit 4. A Don’t Care if a 1-bit
to 3-bit length is selected.
C3 RDNCD1.3 Receive Down Code Definition Bit 3. A Don’t Care if a 1-bit
to 4-bit length is selected.
C2 RDNCD1.2 Receive Down Code Definition Bit 2. A Don’t Care if a 1-bit
to 5-bit length is selected.
C1 RDNCD1.1 Receive Down Code Definition Bit 1. A Don’t Care if a 1-bit
to 6-bit length is selected.
C0 RDNCD1.0 Receive Down Code Definition Bit 0. A Don’t Care if a 1-bit
to 7-bit length is selected.
DS21348/DS21Q348
45 of 76
RDNCD2 (10H): RECEIVE DOWN CODE DEFINITION REGISTER 2
(MSB)
(LSB)
C15 C14 C13 C12 C11 C10 C9 C8
SYMBOL POSITION DESCRIPTION
C15 RDNCD2.7
Receive Down Code Definition Bit 15
C14 RDNCD2.6
Receive Down Code Definition Bit 14
C13 RDNCD2.5
Receive Down Code Definition Bit 13
C12 RDNCD2.4
Receive Down Code Definition Bit 12
C11 RDNCD2.3
Receive Down Code Definition Bit 11
C10 RDNCD2.2
Receive Down Code Definition Bit 10
C9 RDNCD2.1
Receive Down Code Definition Bit 9
C8 RDNCD2.0
Receive Down Code Definition Bit 8
DS21348/DS21Q348
46 of 76
6.2 Loopbacks
6.2.1 Remote Loopback (RLB)
When RLB (CCR6.6) is enabled, the DS21348 is placed into remote loopback. In this loopback, data
from the clock/data recovery state machine will be looped back to the transmit path passing through the
jitter attenuator if it is enabled. The data at the RPOS and RNEG pins will be valid while data presented
at TPOS and TNEG will be ignored. See Figure 1-1 for details.
If the Automatic Remote Loop Back Enable (CCR6.5) is set to a one, the DS21348 will automatically go
into remote loop back when it detects the loop-up code programmed in the Receive Up Code Definition
Registers (RUPCD1 and RUPCD2) for a minimum of 5 seconds. When the DS21348 detects the loop
down code programmed in the Receive Loop-Down Code Definition registers (RDNCD1 and RDNCD2)
for a minimum of 5 seconds, the DS21348 will come out of remote loop back. The ARLB can also be
disabled by setting ARLBE to a zero.
6.2.2 Local Loopback (LLB)
When LLB (CCR6.7) is set to a one, the DS21348 is placed into Local Loopback. In this loopback, data
on the transmit-side will continue to be transmitted as normal. TCLK and TPOS/TNEG will pass through
the jitter attenuator (if enabled) and be output at RCLK and RPOS/RNEG. Incoming data from the line at
RTIP and RRING will be ignored. If Transmit Unframed All Ones (CCR3.7) is set to a one while in LLB,
TTIP and TRING will transmit all ones while TCLK and TPOS/TNEG will be looped back to RCLK and
RPOS/RNEG. See Figure 1-1 for more details.
6.2.3 Analog Loopback (ALB)
Setting ALB (CCR6.4) to a one puts the DS21348 in Analog Loopback. Signals at TTIP and TRING will
be internally connected to RTIP and RRING. The incoming signals at RTIP and RRING will be ignored.
The signals at TTIP and TRING will be transmitted as normal. See Figure 1-1 for more details.
6.2.4 Dual Loopback (DLB)
Setting both CCR6.7 and CCR6.6 to a one, LLB and RLB respectively, puts the DS21348 into Dual
Loopback operation. The TCLK and TPOS/TNEG signals will be looped back through the jitter
attenuator (if enabled) and output at RCLK and RPOS/RNEG. Clock and data recovered from RTIP and
RRING will be looped back to the transmit-side and output at TTIP and TRING. This mode of operation
is not available when implementing hardware operation. See Figure 1-1 for more details.
DS21348/DS21Q348
47 of 76
6.3 PRBS Generation and Detection
Setting TPRBSE (CCR3.4) = 1 enables the DS21348 to transmit a 215 - 1 (E1) or a 220 - 1 (T1) Pseudo-
Random Bit Sequence (PRBS) depending on the ETS bit setting in CCR1.7. The receive-side of the
DS21348 will always search for these PRBS patterns independent of CCR3.4. The PRBS Bit Error
Output (PBEO) will remain high until the receiver has synchronized to one of the two patterns (64 bits
received without an error) at which time PBEO will go low and the PRBSD bit in the Status Register
(SR) will be set. Once synchronized, any bit errors received will cause a positive going pulse at PBEO,
synchronous with RCLK. This output can be used with external circuitry to keep track of bit error rates
during the PRBS testing. Setting CCR6.0 (ECRS) = 1 will allow the PRBS errors to be accumulated in
the 16-bit counter in registers ECR1 and ECR2. The PRBS synchronizer will remain in sync until it
experiences 6 bit errors or more within a 64-bit span. Both PRBS patterns comply with the ITU-T O.151
specifications.
6.4 Error Counter
Error Count Register 1 (ECR1) is the most significant word and ECR2 is the least significant word of a
user selectable 16-bit counter that records incoming errors including BiPolar Violations (BPV), Code
Violations (CV), Excessive Zero violations (EXZ) and/or PRBS Errors. See Table 6-3 and Table 6-4 and
Figure 1-2 for details.
Table 6-3. Definition of Received Errors
ERROR E1 OR T1 DEFINITION OF RECEIVED ERRORS
BPV E1/T1
Two consecutive marks with the same polarity. Will ignore BPVs due to
HDB3 and B8ZS zero suppression when CCR2.3 = 0. Typically used with
AMI coding (CCR2.3 = 1). ITU-T O.161.
CV E1
When HDB3 is enabled (CCR2.3 = 0) and the receiver detects two
consecutive BPVs with the same polarity. ITU-T O.161.
EXZ E1 When four or more consecutive zeros are detected.
EXZ T1
When receiving AMI coded signals (CCR2.3 = 1), detection of 16 or more
zeros or a BPV. ANSI T1.403 1999.
When receiving B8ZS coded signals (CCR2.3 = 0), detection of 8 or more
zeros or a BPV. ANSI T1.403 1999.
PRBS E1/T1
A bit error in a received PRBS pattern. See Section 6.3 for details. ITU-T
O.151.
DS21348/DS21Q348
48 of 76
Table 6-4. Function of ECRS Bits and RNEG Pin
E1 or T1
(CCR1.7)
ECRS2
(CCR6.2)
ECRS1
(CCR6.1)
ECRS0
(CCR6.0)
RHBE
(CCR2.3)
FUNCTION OF ECR
COUNTERS/RNEG1
0 0 0 0 X CVs
0 0 0 1 X BPVs (HDB3 code words not counted)
0 0 1 0 X CVs + EXZs
0 0 1 1 X BPVs + EXZs
1 0 X 0 0 BPVs (B8ZS code words not counted)
1 0 X 1 0 BPVs + 8 EXZs
1 0 X 0 1 BPVs
1 0 X 1 1 BPVs + 16 EXZs
X 1 X X X PRBS Errors2
Note 1: RNEG outputs error data only when in NRZ mode (CCR1.6 = 1)
Note 2: PRBS errors will always be output at PBEO independent of ECR control bits and NRZ mode and will not be present at RNEG.
6.4.1 Error Counter Update
A transition of the ECUE (CCR1.4) control bit from 0 to 1 will update the ECR registers with the current
values and reset the counters. ECUE must be set back to zero and another 0 to 1 transition must occur for
subsequent reads/resets of the ECR registers. Note that the DS21348 can report errors at RNEG when in
NRZ mode (CCR1.6 = 1) by outputting a pulse for each error occurrence. The counter saturates at 65,535
and will not rollover.
ECR1 (11H): UPPER ERROR COUNT REGISTER 1;
ECR2 (12H): LOWER ERROR COUNT REGISTER 2
(MSB)
(LSB)
E15 E14 E13 E12 E11 E10 E9 E8 ECR1
E7 E6 E5 E4 E3 E2 E1 E0 ECR2
SYMBOL POSITION DESCRIPTION
E15 ECR1.7
MSB of the 16-bit error count
E0 ECR2.0
LSB of the 16-bit error count
6.5 Error Insertion
When IBPV (CCR3.1) is transitioned from a zero to a one, the device waits for the next occurrence of
three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error
insertion. See Figure 1-3 for details on the insertion of the BPV into the datastream.
When IBE (CCR3.0) is transitioned from a zero to a one, the device will insert a logic error. IBE must be
cleared and set again for another logic error insertion. See Figure 1-3 for details on the insertion of the
logic error into the datasteam.
DS21348/DS21Q348
49 of 76
7. ANALOG INTERFACE
7.1 Receiver
The DS21348 contains a digital clock recovery system. The DS21348 couples to the receive E1 or T1
twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 transformer. See Table 7-3 for transformer
details. Figure 7-1, Figure 7-2, and Figure 7-3 along with Table 7-1 and Table 7-2 show the receive
termination requirements. The DS21348 has the option of using internal termination resistors.
The DS21348 is designed to be fully software-selectable for E1 and T1 without the need to change any
external resistors for the receive-side. The receive-side will allow the user to configure the DS21348 for
75Ω, 100Ω, or 120Ω receive termination by setting the RT1 (CCR5.1) and RT0 (CCR5.0) bits. When
using the internal termination feature, the Rr resistors should be 60Ω each. See Figure 7-1 for details. If
external termination is required, RT1 and RT0 should be set to 0 and both Rr resistors in Figure 7-1 will
need to be 37.5Ω, 50Ω, or 60Ω each depending on the line impedance.
The resultant E1 or T1 clock derived from the 2.048/1.544 PLL (JACLK in Figure 1-1) is internally
multiplied by 16 via another internal PLL and fed to the clock recovery system. The clock recovery
system uses the clock from the PLL circuit to form a 16 times oversampler which is used to recover the
clock and data. This oversampling technique offers outstanding performance to meet jitter tolerance
specifications shown in Figure 7-6.
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1
AMI/B8ZS waveform presented at the RTIP and RRING inputs. When no signal is present at RTIP and
RRING, a Receive Carrier Loss (RCL) condition will occur and the RCLK will be derived from the
JACLK source. See Figure 1-1. If the jitter attenuator is placed in the receive path (as is the case in most
applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If the jitter
attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter
high cycles of the clock. This is due to the highly oversampled digital clock recovery circuitry. See the
Receive AC Timing Characteristics in Section 11 for more details.
The receive-side circuitry also contains a clock synthesizer which outputs a user configurable clock (up to
16.384MHz) synthesized to RCLK at BPCLK (pin 31). See Table 4-3 for details on output clock
frequencies at BPCLK. In hardware mode, BPCLK defaults to a 16.384MHz output.
The DS21348 has a bypass mode for the receive side clock and data. This allows the BPCLK to be
derived from RCLK after the jitter attenuator while the clock and data presented at RCLK, RPOS, and
RNEG go unaltered. This is intended for applications where the receive side jitter attenuation will be
done after the LIU. Setting RJAB (CCR6.3) to a logic 1 will enable the bypass. Be sure that the jitter
attenuator is in the receive path (CCR4.3 = 0). See Figure 1-1 for details.
The DS21348 will report the signal strength at RTIP and RRING in 2.5dB increments via RL3-RL0
located in the Receive Information Register 2. This feature is helpful when trouble shooting line
performance problems. See Table 5-2 for details.
Monitor applications in both E1 and T1 require various flat gain settings for the receive-side circuitry.
The DS21348 can be programmed to support these applications via the Monitor Mode control bits MM1
and MM0. When the monitor modes are enabled, the receiver will tolerate normal line loss up to -6dB.
See Table 4-4 for details.
DS21348/DS21Q348
50 of 76
7.2 Transmitter
The DS21348 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter
(DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the
DS21348 meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user will select which
waveform is to be generated by setting the ETS bit (CCR1.7) for E1 or T1 operation, then programming
the L2/L1/L0 bits in Common Control Register 4 for the appropriate application. See Table 7-1 and
Table 7-2 for the proper L2/L1/L0 settings.
A 2.048MHz or 1.544MHz TTL clock is required at TCLK for transmitting data at TPOS and TNEG.
ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs
require an accuracy of ±32ppm for T1 interfaces. The clock can be sourced internally by RCLK or
JACLK. See CCR1.2, CCR1.1, CCR1.0, and Figure 1-3 for details. Due to the nature of the design of the
transmitter in the DS21348, very little jitter (less than 0.005UIP-P broadband from 10Hz to 100kHz) is
added to the jitter present on TCLK. Also, the waveforms created are independent of the duty cycle of
TCLK. The transmitter in the DS21348 couples to the E1 or T1 transmit twisted pair (or coaxial cable in
some E1 applications) via a 1:2 step-up transformer. In order for the device to create the proper
waveforms, the transformer used must meet the specifications listed in Table 7-3.
The DS21348 has automatic short-circuit limiter which limits the source current to 50mA (RMS) into a
1Ω load. This feature can be disabled by setting the SCLD bit (CCR2.5) = 1. When the current limiter is
activated, TCLE (SR.2) will be set even if short circuit limiter is disabled. The TPD bit (CCR4.0) will
power-down the transmit line driver and tri-state the TTIP and TRING pins. The DS21348 can also detect
when the TTIP or TRING outputs are open circuited. When an open circuit is detected, TOCD (SR.1)
will be set.
7.3 Jitter Attenuator
The DS21348 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit (CCR4.2). In hardware mode the depth is 128 bits and cannot be changed. The 128-bit
mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in
delay sensitive applications. The characteristics of the attenuation are shown in Figure 7-7Figure 7-7. The
jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or
clearing the JAS bit (CCR4.3). Also, the jitter attenuator can be disabled (in effect, removed) by setting
the DJA bit (CCR4.1). For the jitter attenuator to operate properly, a 2.048MHz or 1.544MHz clock must
be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1.
TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. There is an on-board PLL for
the jitter attenuator, which will convert the 2.048MHz clock to a 1.544 MHz rate for T1 applications.
Setting JAMUX (CCR1.3) to a logic 0 bypasses this PLL. On-board circuitry adjusts either the recovered
clock from the clock/data recovery block or the clock applied at the TCLK pin to create a smooth jitter-
free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a
gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming
jitter exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer depth is 32 bits), then the
DS21348 will divide the internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17
instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17,
it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive Information Register 1 (RIR1).
DS21348/DS21Q348
51 of 76
7.4 G.703 Synchronization Signal
The DS21348 can receive a 2.048MHz square-wave synchronization clock as specified in Section 13 of
ITU G.703(10/98). To use the DS21348 in this mode, set the Receive Synchronization Clock Enable
(CCR5.3) = 1. The DS21348 can also transmit the 2.048MHz square-wave synchronization clock as
specified in Section 10 of G.703. To transmit the 2.048MHz clock, set the Transmit Synchronization
Clock Enable (CCR5.2) = 1.
Table 7-1. Line Build-Out Select for E1 in Register CCR4 (ETS = 0)
L2 L1 L0
VDD
(V) APPLICATION N
RETURN LOSS
(dB) Rt (Ω)
0 0 0 3.3
75Ω normal 1:2 N.M. 0
0 0 1 3.3
120Ω normal 1:2 N.M. 0
1 0 0 3.3
75Ω with high return loss 1:2 21 6.2
1 0 1 3.3
120Ω with high return loss 1:2 21 11.6
Note: See Figure 7-1, Figure 7-2, and Figure 7-3. N.M. = Not meaningful.
Table 7-2. Line Build-Out Select for T1 in Register CCR4 (ETS = 1)
L2 L1 L0 VDD
(V) APPLICATION N
RETURN LOSS
(dB) Rt (Ω)
0 0 0 3.3
DSX-1 (0 to 133 feet)/
0dB CSU 1:2 N.M. 0
0 0 1 3.3 DSX-1 (133 to 266 feet) 1:2 N.M. 0
0 1 0 3.3 DSX-1 (266 to 399 feet) 1:2 N.M. 0
0 1 1 3.3 DSX-1 (399 to 533 feet) 1:2 N.M. 0
1 0 0 3.3 DSX-1 (533 to 655 feet) 1:2 N.M. 0
1 0 1 3.3 -7.5dB CSU 1:2 N.M. 0
1 1 0 3.3 -15dB CSU 1:2 N.M. 0
1 1 1 3.3 -22.5dB CSU 1:2 N.M. 0
Note: See Figure 7-1, Figure 7-2, and Figure 7-3. N.M. = Not meaningful.
Table 7-3. Transformer Specifications for 3.3V Operation
SPECIFICATION RECOMMENDED VALUE
Turns Ratio 3.3V Applications 1:1 (receive) and 1:2 (transmit) ±2%
Primary Inductance 600µH minimum
Leakage Inductance 1.0µH maximum
Intertwining Capacitance 40pF maximum
Transmit Transformer DC Resistance
Primary (Device Side)
Secondary
1.0Ω maximum
2.0Ω maximum
Receive Transformer DC Resistance
Primary (Device Side)
Secondary
1.2Ω maximum
1.2Ω maximum
DS21348/DS21Q348
52 of 76
Figure 7-1. Basic Interface
NOTES:
1) All resistor values are ±1%.
2) In E1 applications, the Rt resistors are used to increase the transmitter return loss (Table 7-1). No
return loss is required for T1 applications.
3) The Rr resistors should be set to 60Ω each if the internal receive-side termination feature is enabled.
When this feature is disabled, Rr = 37.5Ω for 75Ω or 60Ω for 120Ω E1 systems, or 50Ω for 100Ω
T1 lines.
4) See Table 7-1 and Table 7-2 for the appropriate transmit transformer turns ratio (N).
RTIP
RRING
TTIP
TRING
Receive
Line
N:1
(larger winding
toward the network)
DS21348
1.0µF
(non-
polarized)
VDD (21)
VSS (22)
0.1µF
VDD (36)
VSS (35)
0.1µF
+VDD
0.01µF
2.048MHz
(this clock can also
be 1.544MHz for T1
only applications)
MCLK
1:1
0.1µF
R
r
R
r
Rt
Rt
Transmit
Line 10µF
10µF
DS21348/DS21Q348
53 of 76
Figure 7-2. Protected Interface Using Internal Receive Termination
NOTES:
1. All resistor values are ±1%.
2. C1 = C2 = 0.1µF.
3. S is a 6V transient suppresser.
4. D1 to D8 are Schottky diodes.
5. The fuses are optional to prevent AC power line crosses from compromising the transformers.
6. Rp resistors exist to keep the Fuses from opening during a surge. If they are used, then the 60Ω
receive termination resistance must be adjusted to match the line impedance.
7. The Rt resistors are used to increase the transmitter return loss (Table 7-1). No return loss is required
for T1 applications.
8. The transmit transformer turns ratio (N) would be 1:2 for 3.3V operation.
9. The 68µF is used to keep the local power plane potential within tolerance during a surge.
RTIP
RRING
TTIP
TRING
Receive
Line
N:1
(larger winding
toward the network)
DS21348
1.0µF
(non-
polarized)
VDD (21)
VSS (22)
0.1µF
VDD (36)
VSS (35)
0.1µF
+VDD
0.01µF
2.048MHz
(this clock can also
be 1.544MHz for T1
only applications)
MCLK
+VDD
S
C1
D1 D2
D3 D4
1:1
Rp
Fuse
Rp
Fuse
+VDD
C2
D5 D6
D7 D8
Rt
Rt
68µF
S
(optional)
Transmit
Line
Rp
Fuse
Rp
Fuse
(optional)
10µF
10µF
0.1µF
60 60
DS21348/DS21Q348
54 of 76
Figure 7-3. Protected Interface Using External Receive Termination
NOTES:
1. All resistor values are ±1%.
2. C1 = 0.1µF.
3. S is a 6V transient suppresser.
4. D1 to D4 are Schottky diodes.
5. The fuses are optional to prevent AC power line crosses from compromising the transformers.
6. Rp resistors exist to keep the Fuses from opening during a surge. If they are used, then Rr must be
adjusted to match the line impedance.
7. Rr = 37.5Ω for 75Ω or 60Ω for 120Ω E1 systems, or 50Ω for 100Ω T1 lines.
8. The Rt resistors are used to increase the transmitter return loss (Table 7-1). No return loss is required
for T1 applications.
9. The transmit transformer turns ratio (N) would be 1:2 for 3.3V operation.
10. The 68µF is used to keep the local power plane potential within tolerance during a surge.
RTIP
RRING
TTIP
TRING
Receive
Line
N:1
(larger winding
toward the network)
DS21348
1.0µF
(non-
polarized)
VDD (21)
VSS (22)
VDD (36)
VSS (35)
2.048MHz
(this clock can also
be 1.544MHz for T1
only applications)
MCLK
+VDD
S
C1
D1 D2
D3 D4
1:1
0.1µF
470
470
Rp
Fuse
Rp
Fuse
R
r
R
r
Rt
Rt
(optional)
Transmit
Line
Rp
Fuse
Rp
Fuse
(optional)
0.1µF
0.1µF
+VDD
0.01µF 68µF
10µF
10µF
DS21348/DS21Q348
55 of 76
Figure 7-4. E1 Transmit Pulse Template
0
-0.1
-0.2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0
TIME (ns)
SCALED AMPLITUDE
50 100 150 200 250-50-100-150-200-250
269ns
194ns
219ns
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak
in 120 ohm systems, 1.0 on the scale = 3.00Vpeak)
G.703
Template
DS21348/DS21Q348
56 of 76
Figure 7-5. T1 Transmit Pulse Template
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
-500 -300 -100 0 300 500 700
-400 -200 200 400 600100
TIME (ns)
NORMALIZED AMPLITUDE
T1.102/87, T1.403,
CB 119 (Oct. 79), &
I.431 Template
-0.77
-0.39
-0.27
-0.27
-0.12
0.00
0.27
0.35
0.93
1.16
-500
-255
-175
-175
-75
0
175
225
600
750
0.05
0.05
0.80
1.15
1.15
1.05
1.05
-0.07
0.05
0.05
-0.77
-0.23
-0.23
-0.15
0.00
0.15
0.23
0.23
0.46
0.66
0.93
1.16
-500
-150
-150
-100
0
100
150
150
300
430
600
750
-0.05
-0.05
0.50
0.95
0.95
0.90
0.50
-0.45
-0.45
-0.20
-0.05
-0.05
UI Time Amp.
MAXIMUM CURVE
UI Time Amp.
MINIMUM CURVE
DS21348/DS21Q348
57 of 76
Figure 7-6. Jitter Tolerance
Figure 7-7. Jitter Attenuation
DS21348
FREQUENCY (Hz)
UNIT INTERVALS (UIP-P)
1k
100
10
1
0.1
10 100 1k 10k 100k
Tolerance
1
TR 62411 (Dec. 90)
ITU-T G.823
FREQUENCY (Hz)
0dB
-20dB
-40dB
-60dB
1 10 100 1K 10K
JITTER ATTENUATION (dB)
100K
TR 62411 (Dec. 90)
Prohibited Area
Curve B
Curve A
ITU G.7XX
Prohibited Area
TBR12
Prohibited
Area
T1E1
DS21348/DS21Q348
58 of 76
8. DS21Q348 QUAD LIU
The DS21Q348 is a quad version of the DS21348G utilizing CSBGA on carrier packaging technology.
The four LIUs are controlled via the parallel port mode. Serial and hardware modes are unavailable in
this package.
Table 8-1. DS21Q348 Pin Assignment
PIN I/O PARALLEL
PORT MODE
J1 I Connect to VSS
K3 I Connect to VSS
J2 I RD (DS)
H1 I WR (R/W)
K2 I ALE (AS)
K1 I/O A4
L1 I A3
H11 I A2
H12 I A1
G12 I A0
J10 I/O D7/AD7
H10 I/O D6/AD6
G11 I/O D5/AD5
J9 I/O D4/AD4
E3 I/O D3/AD3
D4 I/O D2/AD2
F3 I/O D1/AD1
D5 I/O D0/AD0
G4 I VSM
K9 I/O INT
K7 I TEST
L9 I HRST
J6 I MCLK
L7 I BIS0
M8 I BIS1
M12 I PBTS
J3 I CS1
D3 I CS2
D10 I CS3
K10 I CS4
K5 O PBEO1
G3 O PBEO2
E10 O PBEO3
K8 O PBEO4
L6 O RCL/LOTC1
D7 O RCL/LOTC2
DS21348/DS21Q348
59 of 76
PIN I/O PARALLEL
PORT MODE
F9 O RCL/LOTC3
J7 O RCL/LOTC4
A1 I RTIP1
A4 I RTIP2
A7 I RTIP3
A10 I RTIP4
B2 I RRING1
B5 I RRING2
B8 I RRING3
B11 I RRING4
H4 O BPCLK1
D6 O BPCLK2
F10 O BPCLK3
L8 O BPCLK4
A2 O TTIP1
A5 O TTIP2
A8 O TTIP3
A11 O TTIP4
B3 O TRING1
B6 O TRING2
B9 O TRING3
B12 O TRING4
K4 O RPOS1
E1 O RPOS2
D11 O RPOS3
K11 O RPOS4
G2 O RNEG1
E2 O RNEG2
F11 O RNEG3
M10 O RNEG4
H3 O RCLK1
F1 O RCLK2
E11 O RCLK3
L11 O RCLK4
G1 I TPOS1
F2 I TPOS2
E12 I TPOS3
M11 I TPOS4
H2 I TNEG1
M1 I TNEG2
D12 I TNEG3
K12 I TNEG4
M2 I TCLK1
L2 I TCLK2
DS21348/DS21Q348
60 of 76
PIN I/O PARALLEL
PORT MODE
F12 I TCLK3
L12 I TCLK4
J5 — VDD1
D2 — VDD2
G9 — VDD3
M9 — VDD4
L5 — VDD1
E4 — VDD2
D8 — VDD3
J8 — VDD4
J4 — VSS1
D1 — VSS2
E9 — VSS3
L10 — VSS4
M4 — VSS1
F4 — VSS2
D9 — VSS3
H9 — VSS4
DS21348/DS21Q348
61 of 76
Figure 8-1. 144-CSBGA (17mm x 17mm) Pinout
1 2 3 4 5 6 7 8 9 10 11 12
A RTIP1 TTIP1 NC RTIP2 TTIP2 NC RTIP3 TTIP3 NC RTIP4 TTIP4 NC
B NC RRING1 TRING1 NC RRING2 TRING2 NC RRING3 TRING3 NC RRING4 TRING4
C NC NC NC NC NC NC NC NC NC NC NC NC
D VSS2 VDD2 CS2 D2/AD2 D0/AD0 BPCLK2 RCL/
LOTC2 VDD3 VSS3 CS3 RPOS3 TNEG3
E RPOS2 RNEG2 D3/AD3 VDD2 NC NC NC NC VSS3 PEBO3 RCLK3 TPOS3
F RCLK2 TPOS2 D1/AD1 VSS2 NC NC NC NC RCL/
LOTC3 BPCLK3 RNEG3 TCLK3
G TPOS1 RNEG1 PEBO2 VSM NC NC NC NC VDD
3 NC D5/AD5 A0
H WR
(R/W) TNEG1 RCLK1 BPCLK1 NC NC NC NC VSS4 D6/AD6 A2 A1
J (Note 2) RD
(DS) CS1 VSS1 VDD1 MCLK RCL/
LOTC4 VDD4 D4/AD4 D7/AD7 NC NC
K A4 ALE (AS) (Note 2) RPOS1 PEBO1 NC TEST PEBO4 INT CS4 RPOS4 TNEG4
L A3 TCLK2 NC NC VDD1 RCL/
LOTC1 BIS0 BPCLK4 HRST VSS4 RCLK4 TCLK4
M TNEG2 TCLK1 NC VSS1 NC NC NC BIS1 VDD4 RNEG4 TPOS4 PBTS
Note 1: Shaded areas are signals common to all four devices.
Note 2: Connect to VSS.
DS21348/DS21Q348
62 of 76
9. DC CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +6.0V
Operating Temperature Range for DS21348TN……………………………………………-40°C to +85°C
Storage Temperature Range……………………………………………………………….-55°C to +125°C
Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect device
reliability.
Table 9-1. Recommended DC Operating Conditions
(TA = -40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Logic 1 VIH 2.0 5.5 V
Logic 0 VIL –0.3 +0.8 V
Supply for 3.3V Operation VDD 3.135 3.3 3.465 V 1
Table 9-2. Capacitance
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5 pF
Output Capacitance COUT 7 pF
Table 9-3. DC Characteristics
(VDD = 3.3V ± 5%, TA = -40°C to +85°C.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage IIL -1.0 +1.0
µA 3
Output Leakage ILO 1.0
µA 4
Output Current (2.4V) IOH –1.0 mA
Output Current (0.4V) IOL +4.0 mA
Supply Current IDD 66 100 mA 2, 5
NOTES:
1) Applies to VDD.
2) TCLK = MCLK = 2.048MHz.
3) 0.0V < VIN < VDD.
4) Applied to INT when tri-stated.
5) Power dissipation with TTIP and TRING driving a 30Ω load, for an all-ones data density.
DS21348/DS21Q348
63 of 76
10. THERMAL CHARACTERISTICS
Table 10-1. Thermal Characteristics—DS21Q348 CSBGA Package
PARAMETER MIN TYP MAX NOTES
Ambient Temperature -40ºC +85ºC 1
Junction Temperature +125ºC
Theta-JA (θJA) in Still Air +24ºC/W 2
Theta-JC (θJC) in Still Air +4.1ºC/W 3
NOTES:
1) The package is mounted on a four-layer JEDEC-standard test board.
2) Theta-JA (θJA) is the junction to ambient thermal resistance, when the package is mounted on a four-
layer JEDEC-standard test board.
3) While Theta-JC (θJC) is commonly used as the thermal parameter that provides a correlation between the
junction temperature (Tj) and the average temperature on top center of four of the chip-scale BGA
packages (TC), the proper term is Psi-JT. It is defined by:
(TJ - TC) / overall package power
The method of measurement of the thermal parameters is defined in EIA/JEDEC-standard document
EIA-JESD51-2.
Table 10-2. Theta-JA (θJA) vs. Airflow
FORCED AIR (m/s) THETA-JA (θJA)
0 24ºC/W
1 21ºC/W
2.5 19ºC/W
DS21348/DS21Q348
64 of 76
11. AC CHARACTERISTICS
Table 11-1. AC Characteristics—Multiplexed Parallel Port (BIS1 = 0, BIS0 = 0)
(VDD = 3.3V ± 5%, TA = -40°C to +85°C.) (See Figure 11-1, Figure 11-2, and Figure 11-3.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Cycle Time tCYC 200 ns
Pulse Width, DS Low or RD
High PWEL 100 ns
Pulse Width, DS High or RD
Low PWEH 100 ns
Input Rise/Fall Times tR, tF 20 ns
R/W Hold Time tRWH 10 ns
R/W Setup Time Before DS
High tRWS 50 ns
CS Setup Time Before DS,
WR, or RD Active tCS 20 ns
CS Hold Time tCH 0 ns
Read Data Hold Time tDHR 10 50 ns
Write Data Hold Time tDHW 0 ns
Muxed Address Valid to AS
or ALE Fall tASL 15 ns
Muxed Address Hold Time tAHL 10 ns
Delay Time DS, WR, or RD
to AS or ALE Rise tASD 20 ns
Pulse Width AS or ALE
High PWASH 30 ns
Delay Time, AS or ALE to
DS, WR, or RD tASED 10 ns
Output Data Delay Time
from DS or RD tDDR 20 80 ns
Data Setup Time tDSW 50 ns
DS21348/DS21Q348
65 of 76
Figure 11-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0)
Figure 11-2. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 0)
ASH
PW
tCYC
t
ASD
t
ASD PW
PW
EH
EL
t
t
t
t
t
t
t
AHL DSW
DHW
CH
CS
ASL
ASED
C
S
AD0-AD7
R
D
W
R
ALE
ASH
PW
tCYC
t
ASD
t
ASD PW
PW
EH
EL
t
t
t
t
t
t
AHL
CH
CS
ASL
ASED
C
S
AD0-AD7 DHR
tDDR
ALE
R
D
W
R
DS21348/DS21Q348
66 of 76
Figure 11-3. Motorola Bus Timing (PBTS = 1, BIS1 = 0, BIS0 = 0)
t
A
SD
A
SH
PW
t
t
A
SL
A
HL tCS
t
A
SL
t
t
t
DSW
DHW
t
CH
tt
t
DDR DHR
RWH
t
A
SED PW
EH
tRWS
A
HL
PW
EL tCYC
A
S
DS
A
D0-AD7
(write)
A
D0-AD7
(read)
R/
W
C
S
DS21348/DS21Q348
67 of 76
Table 11-2. AC Characteristics—Nonmultiplexed Parallel Port
(BIS1 = 0, BIS0 = 1)
(VDD = 3.3V ± 5%, TA = -40°C to +85°C.) (See Figure 11-4, Figure 11-5, Figure 11-6, and
Figure 11-7.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Setup Time for A0 to A4, Valid to CS
Active t1 0 ns
Setup Time for CS Active to Either RD,
WR, or DS Active t2 0 ns
Delay Time from Either RD or DS Active
to Data Valid t3 75 ns
Hold Time from Either RD, WR, or DS,
Inactive to CS Inactive t4 0 ns
Hold Time from CS Inactive to Data Bus
Tri-State t5 5 20 ns
Wait Time from Either WR or DS Active
to Latch Data t6 75 ns
Data Setup Time to Either WR or DS
Inactive t7 10 ns
Data Hold Time from Either WR or DS
Inactive t8 10 ns
Address Hold from Either WR or DS
Inactive t9 10 ns
DS21348/DS21Q348
68 of 76
Figure 11-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1)
Figure 11-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1)
Address Valid
Data Valid
A0 to A4
D0 to D7
W
R
C
S
R
D
0ns min.
0ns min.
75ns max.
0ns min.
5ns min/20ns max
t1
t2 t3 t4
t5
Address Valid
A0 to A4
D0 to D7
R
D
C
S
W
R
0ns min.
0ns min. 75ns min. 0ns min.
10ns
min.
10ns
min.
t1
t2 t6 t4
t7 t8
DS21348/DS21Q348
69 of 76
Figure 11-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1)
Figure 11-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1)
Address Valid
Data Valid
A0 to A4
D0 to D7
R/
W
C
S
D
S
0ns min.
0ns min.
75ns max.
0ns min.
5ns min. / 20ns max.
t1
t2 t3 t4
t5
Address Valid
A0 to A4
D0 to D7
R/
W
C
S
D
S
0ns min.
0ns min. 75ns min.
0ns min.
10ns
min.
10ns
min.
t1
t2 t6 t4
t7 t8
DS21348/DS21Q348
70 of 76
Table 11-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0)
(VDD = 3.3V ± 5%, TA = -40°C to +85°C.) (See Figure 11-8.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Setup Time CS to SCLK tCSS 50 ns
Setup Time SDI to SCLK tSSS 50 ns
Hold Timfe SCLK to SDI tSSH 50 ns
SCLK High/Low Time tSLH 200 ns
SCLK Rise/Fall Time tSRF 50 ns
SCLK to CS Inactive tLSC 50 ns
CS Inactive Time tCM 250 ns
SCLK to SDO Valid tSSV 50 ns
SCLK to SDO Tri-State tSSH 100 ns
CS Inactive to SDO Tri-State tCSH 100 ns
Figure 11-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0)
SCLK
1
SCLK
2
SDI
C
S
HIGH Z
SDO
t
CSS
t
SSS t
SSH
tSRF tSLH t
LSC
t
CM
tSSV t
SSH
t
CSH
HIGH Z
LSB
LSB
LSB MSB
MSB
MSB
NOTE 1: OCES =1 AND ICES = 0.
NOTE 2: OCES = 0 AND ICES = 1.
DS21348/DS21Q348
71 of 76
Table 11-4. AC Characteristics—Receive Side
(VDD = 3.3V ± 5%, TA = -40°C to +85°C.) (See Figure 11-9.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
488 ns 1
RCLK Period tCP 648 ns 2
tCH 200 ns 3
RCLK Pulse Width tCL 200 ns 3
tCH 150 ns 4
RCLK Pulse Width tCL 150 ns 4
Delay RCLK to RPOS, RNEG,
PBEO, RBPV Valid tDD 50 ns
NOTES:
1) E1 mode.
2) T1 or J1 mode.
3) Jitter attenuator enabled in the receive path.
4) Jitter attenuator disabled or enabled in the transmit path.
Figure 11-9. Receive Side Timing
tDD
RPOS, RNEG
RCLK2
CL
t
tCP
CH
t
RCLK1
PBEO
tDD
bit
error
BPV/
EXZ/
CV
PRBS Detector Out of Sync
RNEG3BPV/
EXZ/
CV
NOTE 1: RCES = 1 (CCR2.0) OR CES = 1.
NOTE 2: RCES = 0 (CCR2.0) OR CES = 0.
NOTE 3: RNEG IS IN NRZ MODE (CCR1.6 = 1).
DS21348/DS21Q348
72 of 76
Table 11-5. AC Characteristics—Transmit Side
(VDD = 3.3V ± 5%, TA = -40°C to +85°C.) (Figure 11-10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
488 ns 1
TCLK Period tCP 648 ns 2
tCH 75 ns
TCLK Pulse Width tCL 75 ns
TPOS/TNEG Setup to TCLK
Falling or Rising tSU 20 ns
TPOS/TNEG Hold from TCLK
Falling or Rising tHD 20 ns
TCLK Rise and Fall Times tR, tF 25 ns
NOTES:
1) E1 mode.
2) T1 or J1 mode.
Figure 11-10. Transmit Side Timing
tF
t
R
TPOS, TNEG
t
CL
tCH
CP
tHD
tSU
TCLK1
t
TCLK2
NOTE 1: TCES = 0 (CCR2.1) or CES = 0.
NOTE 2: TCES = 1 (CCR2.1) or CES = 1.
DS21348/DS21Q348
73 of 76
12. PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for
each package is a link to the latest package outline information.)
12.1 44-Pin TQFP (56-G4012-001)
DIMENSIONS ARE IN MILLIMETERS
SEE DETAIL "A"
SUGGESTED PAD LAYOUT
44 PIN TQFP, 10*10*1.0
DS21348/DS21Q348
76 of 76
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products • Printed USA
are registered trademarks of Maxim Integrated Products, Inc., and Dallas Semiconductor Corporation.
2.60
REF
Z
0.10
0.76
REF
SEATING PLANE
2
/
/
0.17 Z
/
/
0.24 Z
0.05 LABEL THICKNESS
φ 0.76 REF
φ
0.76 L
φ
0.76 L
X
Z
Y Z
SOLDER BALL
