Data Sheet No. PD60165-C
IR1210
Block Diagram
Package
Product Summary
IO+/- 1.5A / 1.5A
VOUT 6V - 20V
ton/off (typ.) 85 & 65 ns
DUAL LOW SIDE DRIVER
Features
•Gate drive supply range from 6 to 20V
•CMOS Schmitt-triggered inputs with pull-up
•Matched propagation delay for both channels
•Outputs out of phase with inputs
Description
The IR1210 is a low voltage, high speed power
MOSFET and IGBT driver. Proprietary latch immune
CMOS technologies enable ruggedized monolithic
construction. Logic inputs are compatible with stan-
dard CMOS or LSTTL outputs. The output drivers
feature a high pulse current buffer stage designed
for minimum driver cross-conduction. Propagation
delays between two channels are matched.
8 Lead SOIC
8
7
6
5 4
3
2
1 NC
OUTA
Vs
INA
GND
INB OUTB
NC
IR1210
INB
INA TO
LOAD
The IR1210 part number has
been updated and changed to
IR4426/IR4427/IR4428
Please see new data sheet
2
IR1210 ADVANCED INFORMATION
www.irf.com
Symbol Definition Mi n. Max. Units
VSFixed supply voltage -0.3 25
VOOutput voltage -0.3 VS + 0.3
VIN Logic input voltage (INA/N & INB/N) -0.3 VS + 0.3
PDPackage power dissipation @ TA ≤ +25°C — 0.625 W
RthJA Thermal resistance, junction to ambient — 2 0 0 ° C/W
TJJunction temperature — 150
TSStorage temperature -55 150
TLLead temperature (soldering, 10 seconds) — 300
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to GND. The ther mal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
V
°C
Symbol Definition Min . Max. Units
VSFixed supply oltage 6 20
VOOutput voltage 0 VS
VIN Logic input voltage (INA/N & INB/N) 0 VS
TAAmbient temperature -40 125
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltages referenced to GND.
°C
V
Symbol Definition Min. Typ. Max. Units Test Conditions
VIH Logic “0” input voltage (OUT=LO) 2.7 — —
VIL Logic “1” input voltage (OUT=HI) — — 0.8
VOH High level output voltage, VBIAS-VO— — 1.2
VOL Low level output voltage, VO— — 0.1
IIN+ Logic “1” input bias current (OUT=HI) — 5 15 VIN = 0V
IIN- Logic “0” input bias current (OUT=LO) — -10 -30 VIN = V S
IQS Quiescent Vs supply current — 100 200 VIN = 0V or VS
IO+ Output high short circuit pulsed current 1.5 2.3 — VO = 0V, VIN = 0
PW ≤ 10 µ s
IO- Output low short circuit pulsed current 1.5 3.3 — VO = 15V, VIN = V S
PW ≤ 10 µ s
DC Electrical Characteristics
VBIAS (VS) = 15V, TA = 25°C unless otherwise specified. The VIN, and IIN parameters are referenced to GND and are
applicable to input leads: INA/N and INB/N. The VO and I O parameters are referenced to GND and are applicable to the
output leads: OUTA and OUTB.
A
µA
V
3
IR1210
ADVANCED INFORMATION
www.irf.com
Functional Block Diagram
Lead Assignment and Definitions
Symbol Description
VSSupply voltage
GND Ground
INA Logic input for gate driver output (OUTA), out of phase
INB Logic input for gate driver output (OUTB), out of phase
OUTA Gate drive output A
OUTB Gate drive output B
Symbol Definition Min. Typ. Max. Units Test Conditions
td1 Turn-on propagation delay — 85 160
td2 Turn-off propagation delay — 65 150
trTurn-on rise time — 15 35
tfTurn-off fall time — 10 25
Dynamic Electrical Characteristics
VBIAS (VS) = 15V, CL = 1000 pF, TA = 25°C unless otherwise specified.
INA
GND
INB
OUTA
VS
OUTB
ns figures 2 & 3
PREDRV
DRV
PREDRV
DRV
GND
OUTB
OUTA
Vs
INB
INA
Vs
5V
5V
4
IR1210 ADVANCED INFORMATION
www.irf.com
8 Lead SOIC 01-0021 08
5
IR1210
ADVANCED INFORMATION
www.irf.com
Figure 1. Timing Diagram Figure 2. Switching Time Waveforms
Figure 3. Switching Time Test Circuit
INA
INB
OUTA
OUTB
INA
INB
OUTA
OUTB
t
d1
t
r
50%
90%
10%
50%
90%
10%
t
d2
t
f
INA
INB
OUTA
OUTB
5
7
3
64.7UF
0.1UF
C
L
= 1000PF
C
L
= 1000PF
V
S
= 15V
2
4
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 12/20/2000