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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM25576

SNVS470H –JANUARY 2007–REVISED AUGUST 2017

LM25576 42-V, 3-A Step-Down Switching Regulator

1 Features

1• Integrated 42-V, 170-mΩN-channel MOSFET

• Ultra-Wide Input Voltage Range from 6 V to 42 V

• Adjustable Output Voltage as Low as 1.225 V

• 1.5% Feedback Reference Accuracy

• Operating Frequency Adjustable Between 50 kHz

and 1 MHz with Single Resistor

• Master or Slave Frequency Synchronization

• Adjustable Soft-Start

• Emulated Current Mode Control Architecture

• Wide Bandwidth Error Amplifier

• Built-in Protection

• HTSSOP-20EP (Exposed Pad)

• Create a Custom Design Using the LM25576 With

the WEBENCH®Power Designer

2 Applications

• Industrial

3 Description

The LM25576 is an easy to use buck regulator which

allows design engineers to design and optimize a

robust power supply using a minimum set of

components. Operating with an input voltage range of

6 V to 42 V, the LM25576 delivers 3 A of continuous

output current with an integrated 170-mΩN-Channel

MOSFET. The regulator utilizes an Emulated Current

Mode architecture which provides inherent line

regulation, tight load transient response, and ease of

loop compensation without the usual limitation of low-

duty cycles associated with current mode regulators.

The operating frequency is adjustable from 50 kHz to

1 MHz to allow optimization of size and efficiency. To

reduce EMI, a frequency synchronization pin allows

multiple IC’s from the LM(2)557x family to self-

synchronize or to synchronize to an external clock.

The LM25576 ensures robustness with cycle-by-cycle

current limit, short-circuit protection, thermal shut-

down, and remote shut-down. The device is available

in a power enhanced HTSSOP-20 package featuring

an exposed die attach pad for thermal dissipation.

The LM25576 is supported by the full suite of

WEBENCH®On-Line design tools.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM25576 HTSSOP (20) 6.50 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Application Schematic

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Electrical Characteristics........................................... 6

6.5 Typical Characteristics.............................................. 7

7 Detailed Description............................................ 10

7.1 Overview................................................................. 10

7.2 Functional Block Diagram....................................... 10

7.3 Feature Description................................................. 10

7.4 Device Functional Modes........................................ 11

8 Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Application.................................................. 24

9 Layout................................................................... 25

9.1 Layout Guidelines ................................................... 25

9.2 Layout Example ...................................................... 26

10 Device and Documentation Support................. 28

10.1 Device Support...................................................... 28

10.2 Receiving Notification of Documentation Updates 28

10.3 Community Resources.......................................... 28

10.4 Trademarks........................................................... 28

10.5 Electrostatic Discharge Caution............................ 28

10.6 Glossary................................................................ 28

11 Mechanical, Packaging, and Orderable

Information........................................................... 29

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (March 2009) to Revision G Page

• Changed layout of National Data Sheet to TI format ............................................................................................................ 1

Changes from Revision G (April 2013) to Revision H Page

• Added Application and Implementation section, Device Information table, Pin Configuration and Functions section,

ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,Device and

Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1

VIN

PRE

COMP

VCC

PGND

SS 11

RAMP

SYNC

OUT

BST

AGND

PGND

VIN

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5 Pin Configuration and Functions

PWP

20-HTSSOP

Top View

Pin Functions

NO. NAME DESCRIPTION

1 VCC Output of the bias regulator

Vcc tracks Vin up to 9 V. Beyond 9 V, Vcc is regulated to 7 Volts. A 0.1 uF to 1 uF ceramic decoupling

capacitor is required. An external voltage (7.5 V – 14 V) can be applied to this pin to reduce internal power

dissipation.

2 SD

Shutdown or UVLO input

If the SD pin voltage is below 0.7 V the regulator will be in a low power state. If the SD pin voltage is between

0.7 V and 1.225 V the regulator will be in standby mode. If the SD pin voltage is above 1.225 V the regulator

will be operational. An external voltage divider can be used to set a line undervoltage shutdown threshold. If

the SD pin is left open circuit, a 5 µA pull-up current source configures the regulator fully operational.

3, 4 VIN Input supply voltage

Nominal operating range: 6 V to 42 V

5 SYNC Oscillator synchronization input or output

The internal oscillator can be synchronized to an external clock with an external pull-down device. Multiple

LM25576 devices can be synchronized together by connection of their SYNC pins.

6 COMP Output of the internal error amplifier

The loop compensation network should be connected between this pin and the FB pin.

7 FB Feedback signal from the regulated output

This pin is connected to the inverting input of the internal error amplifier. The regulation threshold is 1.225 V.

8 RT Internal oscillator frequency set input

The internal oscillator is set with a single resistor, connected between this pin and the AGND pin.

9 RAMP Ramp control signal

An external capacitor connected between this pin and the AGND pin sets the ramp slope used for current

mode control. Recommended capacitor range 50 pF to 2000 pF.

10 AGND Analog ground

Internal reference for the regulator control functions

11 SS Soft-start

An external capacitor and an internal 10 µA current source set the time constant for the rise of the error amp

reference. The SS pin is held low during standby, Vcc UVLO and thermal shutdown.

12 OUT Output voltage connection

Connect directly to the regulated output voltage.

13, 14 PGND Power ground

Low side reference for the PRE switch and the IS sense resistor.

15, 16 IS Current sense

Current measurement connection for the re-circulating diode. An internal sense resistor and a sample/hold

circuit sense the diode current near the conclusion of the off-time. This current measurement provides the DC

level of the emulated current ramp.

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Pin Functions (continued)

NO. NAME DESCRIPTION

17, 18 SW Switching node

The source terminal of the internal buck switch. The SW pin should be connected to the external Schottky

diode and to the buck inductor.

19 PRE

Pre-charge assist for the bootstrap capacitor

This open drain output can be connected to SW pin to aid charging the bootstrap capacitor during very light

load conditions or in applications where the output may be pre-charged before the LM25576 is enabled. An

internal pre-charge MOSFET is turned on for 265 ns each cycle just prior to the on-time interval of the buck

switch.

20 BST Boost input for bootstrap capacitor

An external capacitor is required between the BST and the SW pins. A 0.022 µF ceramic capacitor is

recommended. The capacitor is charged from Vcc via an internal diode during the off-time of the buck switch.

NA EP Exposed Pad

Exposed metal pad on the underside of the device. It is recommended to connect this pad to the PWB ground

plane, in order to aid in heat dissipation.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2)

MIN MAX UNIT

VIN to GND 45 V

BST to GND 60 V

PRE to GND 45 V

SW to GND (Steady State) –1.5 V

BST to VCC 45 V

SD, VCC to GND 14 V

BST to SW 14 V

OUT to GND Limited Vin V

SYNC, SS, FB, RAMP to GND 7 V

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2 kV

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

6.3 Recommended Operating Conditions(1)

MIN MAX UNIT

VIN 6 42 V

TJOperation junction temperature –40 125 °C

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(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Texas Instruments' Average Outgoing Quality Level

(AOQL).

6.4 Electrical Characteristics

at TJ= 25°C, and VIN = 24 V, RT= 32.4 kΩ(unless otherwise noted).(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

STARTUP REGULATOR

VccReg Vcc Regulator Output TJ= –40°C to +125°C 6.85 7.15 7.45 V

Vcc LDO Mode turn-off 9 V

Vcc Current Limit Vcc = 0 V 25 mA

VCC SUPPLY

Vcc UVLO Threshold (Vcc increasing) TJ= –40°C to +125°C 5.03 5.35 5.67 V

Vcc Undervoltage Hysteresis 0.35 V

Bias Current (Iin) FB = 1.3 V TJ= –40°C to +125°C 3.7 4.5 mA

Shutdown Current (Iin) SD = 0 V TJ= –40°C to +125°C 48 70 µA

SHUTDOWN THRESHOLDS

Shutdown Threshold (SD Increasing) TJ= –40°C to +125°C 0.47 0.7 0.9 V

Shutdown Hysteresis 0.1 V

Standby Threshold (Standby Increasing) TJ= –40°C to +125°C 1.17 1.225 1.28 V

Standby Hysteresis 0.1 V

SD Pull-up Current Source 5 µA

SWITCH CHARACTERSICS

Buck Switch Rds(on) TJ= –40°C to +125°C 330 660 mΩ

BOOST UVLO 4 V

BOOST UVLO Hysteresis 0.56 V

Pre-charge Switch Rds(on) 70 Ω

Pre-charge Switch on-time 250 ns

CURRENT LIMIT

Cycle by Cycle Current Limit RAMP = 0 V TJ= –40°C to +125°C 1.8 2.1 2.5 A

Cycle by Cycle Current Limit Delay RAMP = 2.5 V 85 ns

SOFT-START

SS Current Source TJ= –40°C to +125°C 7 10 14 µA

OSCILLATOR

Frequency1 TJ= –40°C to +125°C 180 200 220 kHz

Frequency2 RT= 11 kΩTJ= –40°C to +125°C 425 485 545 kHz

SYNC Source Impedance 11 kΩ

SYNC Sink Impedance 110 Ω

SYNC Threshold (falling) 1.3 V

SYNC Frequency RT= 11 kΩTJ= –40°C to +125°C 550 kHz

SYNC Pulse Width Minimum TJ= –40°C to +125°C 15 ns

RAMP GENERATOR

Ramp Current 1 Vin = 36 V,

Vout=10 V TJ= –40°C to +125°C 272 310 368 µA

Ramp Current 2 Vin = 10 V,

Vout=10 V TJ= –40°C to +125°C 36 50 64 µA

PWM COMPARATOR

Forced Off-time TJ= –40°C to +125°C 416 500 575 ns

Min On-time 80 ns

COMP to PWM Comparator Offset 0.7 V

TEMPERATURE (oC)

NORMALIZED OSCILLATOR FREQUENCY

-50 -25 0 25 50 75 100 125

0.990

0.995

1.000

1.005

1.010

RT (k:)

OSCILLATOR FREQUENCY (kHz)

1 10 100 1000

100

1000

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Electrical Characteristics (continued)

at TJ= 25°C, and VIN = 24 V, RT= 32.4 kΩ(unless otherwise noted).(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ERROR AMPLIFIER

Feedback Voltage Vfb = COMP TJ= –40°C to +125°C 1.207 1.225 1.243 V

FB Bias Current 17 nA

DC Gain 70 dB

COMP Sink / Source Current TJ= –40°C to +125°C 3 mA

Unity Gain Bandwidth 3 MHz

DIODE SENSE RESISTANCE

DSENSE 83 mΩ

THERMAL SHUTDOWN

Tsd Thermal Shutdown Threshold 165 °C

Thermal Shutdown Hysteresis 25 °C

6.5 Typical Characteristics

Figure 1. Oscillator Frequency vs RT

FOSC = 200kHz

Figure 2. Oscillator Frequency vs Temperature

0 2 4 6 8 10

VCC (V)

VIN (V)

Ramp Up

Ramp Down

PHASE (°)

10k 100k 1M 10M 100M

FREQUENCY (Hz)

-30

-20

-10

GAIN (dB)

-135

-90

-45

135

180

225

GAIN

PHASE

TEMPERATURE (oC)

NORMALIZED SOFTSTART CURRENT

-50 -25 0 25 50 75 100 125

0.90

0.95

1.00

1.05

1.10

04 16 20 24

ICC (mA)

VCC (V)

812

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Typical Characteristics (continued)

Figure 3. Soft Start Current vs Temperature

VIN = 12V

Figure 4. VCC vs ICC

RL= 7 kΩ

Figure 5. VCC vs VIN

AVCL = 101

Figure 6. Error Amplifier Gain and Phase

0.5 1 1.5 2 2.5 3

100

EFFICIENCY (%)

IOUT (A)

VIN = 24V

VIN = 7V

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Typical Characteristics (continued)

Figure 7. Demoboard Efficiency vs IOUT and VIN

VIN

BST

AGND

CLK

PRE

3, 4

5 8 912

13, 14

LM25576

SHUTDOWN

STANDBY

REGULATOR

SYNC

OSCILLATOR

RAMP OUT

PGND

CLK

COMP

ERROR

AMP

21k C3

330p

C11

330p

C10

150

1.65k

5.11k

33 PH

0.022

0.47

CSHD6-60C

15, 16

17, 18

THERMAL

SHUTDOWN

UVLO

CLK

DIS

VCC

LEVEL

SHIFT

DRIVER

1.225V

0.7V

49.9k

0.01

open

OPEN

C12

OPEN C4

0.01

2.2

OPEN

7V ± 42V VIN VIN

2.1V

PWM

C_LIMIT

10 PA

5 PA

VIN

TRACK

SAMPLE

and

HOLD

0.5V/A

RAMP GENERATOR

Ir = (5 PA x (VIN ± VOUT))

+ 25 PA

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7 Detailed Description

7.1 Overview

The LM25576 switching regulator features all of the functions necessary to implement an efficient high voltage

buck regulator using a minimum of external components. This easy to use regulator integrates a 42 V N-Channel

buck switch with an output current capability of 3 Amps. The regulator control method is based on current mode

control utilizing an emulated current ramp. Peak current mode control provides inherent line voltage feed-forward,

cycle-by-cycle current limiting, and ease of loop compensation. The use of an emulated control ramp reduces

noise sensitivity of the pulse-width modulation circuit, allowing reliable processing of very small duty cycles

necessary in high input voltage applications. The operating frequency is user programmable from 50 kHz to 1

MHz. An oscillator synchronization pin allows multiple LM25576 regulators to self synchronize or be

synchronized to an external clock. The output voltage can be set as low as 1.225 V. Fault protection features

include, current limiting, thermal shutdown and remote shutdown capability. The device is available in the

HTSSOP-20 package featuring an exposed pad to aid thermal dissipation.

The functional block diagram and typical application of the LM25576 are shown in Functional Block Diagram. The

LM25576 can be applied in numerous applications to efficiently step-down a high, unregulated input voltage. The

device is well suited for telecom, industrial power bus voltage ranges.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 High Voltage Start-Up Regulator

The LM25576 contains a dual-mode internal high voltage startup regulator that provides the Vcc bias supply for

the PWM controller and boot-strap MOSFET gate driver. The input pin (VIN) can be connected directly to the

input voltage, as high as 42 Volts. For input voltages below 9 V, a low dropout switch connects Vcc directly to

Vin. In this supply range, Vcc is approximately equal to Vin. For Vin voltage greater than 9 V, the low dropout

switch is disabled and the Vcc regulator is enabled to maintain Vcc at approximately 7 V. The wide operating

range of 6 V to 42 V is achieved through the use of this dual mode regulator.

VIN

VCC

Internal Enable Signal

5.25V

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Feature Description (continued)

The output of the Vcc regulator is current limited to 25 mA. Upon power up, the regulator sources current into the

capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the Vcc UVLO threshold of 5.35

V and the SD pin is greater than 1.225 V, the output switch is enabled and a soft-start sequence begins. The

output switch remains enabled until Vcc falls below 5 V or the SD pin falls below 1.125 V.

An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary

voltage is greater than 7.3 V, the internal regulator will essentially shut off, reducing the IC power dissipation.

The Vcc regulator series pass transistor includes a diode between Vcc and Vin that should not be forward biased

in normal operation. Therefore the auxiliary Vcc voltage should never exceed the Vin voltage.

In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute

maximum voltage rating of 45 V. During line or load transients, voltage ringing on the Vin line that exceeds the

Absolute Maximum Ratings can damage the IC. Both careful PC board layout and the use of quality bypass

capacitors located close to the VIN and GND pins are essential.

Figure 8. Vin and Vcc Sequencing

7.4 Device Functional Modes

7.4.1 Shutdown and Stand-by Mode

The LM25575 contains a dual level Shutdown (SD) circuit. When the SD pin voltage is below 0.7 V, the regulator

is in a low current shutdown mode. When the SD pin voltage is greater than 0.7 V but less than 1.225 V, the

regulator is in standby mode. In standby mode the Vcc regulator is active but the output switch is disabled. When

the SD pin voltage exceeds 1.225 V, the output switch is enabled and normal operation begins. An internal 5 µA

pull-up current source configures the regulator to be fully operational if the SD pin is left open.

An external set-point voltage divider from VIN to GND can be used to set the operational input range of the

regulator. The divider must be designed such that the voltage at the SD pin will be greater than 1.225 V when

Vin is in the desired operating range. The internal 5 µA pull-up current source must be included in calculations of

the external set-point divider. Hysteresis of 0.1 V is included for both the shutdown and standby thresholds. The

SD pin is internally clamped with a 1 kΩresistor and an 8 V zener clamp. The voltage at the SD pin should never

exceed 14 V. If the voltage at the SD pin exceeds 8 V, the bias current will increase at a rate of 1 mA/V.

The SD pin can also be used to implement various remote enable and disable functions. Pulling the SD pin

below the 0.7 V threshold totally disables the controller. If the SD pin voltage is above 1.225 V the regulator will

be operational.

7.4.2 Oscillator and Sync Capability

The LM25576 oscillator frequency is set by a single external resistor connected between the RT pin and the

AGND pin. The RTresistor should be located very close to the device and connected directly to the pins of the IC

(RT and AGND).To set a desired oscillator frequency (F), the necessary value for the RTresistor can be

calculated from the following equation:

SYNC

LM25576

UP TO 5 TOTAL

DEVICES

LM25576

SYNC

AGND

LM25576

CLK

SYNC

500 ns

RT = - 580 x 10-9

135 x 10-12

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Device Functional Modes (continued)

(1)

The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must be

of higher frequency than the free-running frequency set by the RTresistor. A clock circuit with an open drain

output is the recommended interface from the external clock to the SYNC pin. The clock pulse duration should

be greater than 15 ns.

Figure 9. Sync from External Clock

Figure 10. Sync from Multiple Devices

Multiple LM25576 devices can be synchronized together simply by connecting the SYNC pins together. In this

configuration all of the devices will be synchronized to the highest frequency device. The diagram in Figure 11

illustrates the SYNC input and output features of the LM25576. The internal oscillator circuit drives the SYNC pin

with a strong pull-down and weak pull-up inverter. When the SYNC pin is pulled low either by the internal

oscillator or an external clock, the ramp cycle of the oscillator is terminated and a new oscillator cycle begins.

Thus, if the SYNC pins of several LM25576 IC’s are connected together, the IC with the highest internal clock

frequency will pull the connected SYNC pins low first and terminate the oscillator ramp cycles of the other IC’s.

The LM25576 with the highest programmed clock frequency will serve as the master and control the switching

frequency of the all the devices with lower oscillator frequency.

SYNC

10k

DEADTIME

ONE-SHOT

2.5V

I = f(RT)

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Device Functional Modes (continued)

Figure 11. Simplified Oscillator Block Diagram and SYNC I/O Circuit

7.4.3 Error Amplifier and PWM Comparator

The internal high gain error amplifier generates an error signal proportional to the difference between the

regulated output voltage and an internal precision reference (1.225 V). The output of the error amplifier is

connected to the COMP pin allowing the user to provide loop compensation components, generally a type II

network, as illustrated in Functional Block Diagram. This network creates a pole at DC, a zero and a noise

reducing high frequency pole. The PWM comparator compares the emulated current sense signal from the

RAMP generator to the error amplifier output voltage at the COMP pin.

7.4.4 RAMP Generator

The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the

buck switch current. This switch current corresponds to the positive slope portion of the output inductor current.

Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and

provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current

signal for PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked.

Also, the current measurement may introduce significant propagation delays. The filtering, blanking time and

propagation delay limit the minimum achievable pulsewidth. In applications where the input voltage may be

relatively large in comparison to the output voltage, controlling small pulsewidths and duty cycles is necessary for

regulation. The LM25576 utilizes a unique ramp generator, which does not actually measure the buck switch

current but rather reconstructs the signal. Reconstructing or emulating the inductor current provides a ramp

signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays. The

current reconstruction is comprised of two elements; a sample and hold DC level and an emulated current ramp.

Sample and

Hold DC Level

0.5V/A

RAMP

TON

tON

CRAMP

(5P x (VIN ± VOUT) + 25P) x

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Device Functional Modes (continued)

Figure 12. Composition of Current Sense Signal

The sample and hold DC level illustrated in Figure 12 is derived from a measurement of the re-circulating

Schottky diode anode current. The re-circulating diode anode should be connected to the IS pin. The diode

current flows through an internal current sense resistor between the IS and PGND pins. The voltage level across

the sense resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch.

The diode current sensing and sample & hold provide the DC level of the reconstructed current signal. The

positive slope inductor current ramp is emulated by an external capacitor connected from the RAMP pin to AGND

and an internal voltage controlled current source. The ramp current source that emulates the inductor current is a

function of the Vin and Vout voltages per the following equation:

IRAMP = (5µ x (Vin – Vout)) + 25µA (2)

Proper selection of the RAMP capacitor depends upon the selected value of the output inductor. The value of

CRAMP can be selected from: CRAMP =Lx10-5, where L is the value of the output inductor in Henrys. With this

value, the scale factor of the emulated current ramp will be approximately equal to the scale factor of the DC

level sample and hold ( 0.5 V / A). The CRAMP capacitor should be located very close to the device and

connected directly to the pins of the IC (RAMP and AGND).

For duty cycles greater than 50%, peak current mode control circuits are subject to sub-harmonic oscillation.

Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch

node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this

oscillation. The 25 µA of offset current provided from the emulated current source adds some fixed slope to the

ramp signal. In some high output voltage, high duty cycle applications, additional slope may be required. In these

applications, a pull-up resistor may be added between the VCC and RAMP pins to increase the ramp slope

compensation.

For VOUT > 7.5V:

Calculate optimal slope current, IOS = VOUT x 5µA/V.

For example, at VOUT = 10V, IOS = 50µA.

Install a resistor from the RAMP pin to VCC:

RRAMP = VCC / (IOS - 25µA)

VinMIN = Vout + VD

1 - Fs x 500 ns

RAMP

VCC

CRAMP

RRAMP

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Device Functional Modes (continued)

Figure 13. RRAMP to VCC for VOUT > 7.5V

7.4.5 Maximum Duty Cycle and Input Drop-Out Voltage

There is a forced off-time of 500 ns implemented each cycle to ensure sufficient time for the diode current to be

sampled. This forced off-time limits the maximum duty cycle of the buck switch. The maximum duty cycle will

vary with the operating frequency.

DMAX = 1 - Fs x 500ns (3)

Where Fs is the oscillator frequency. Limiting the maximum duty cycle will raise the input dropout voltage. The

input dropout voltage is the lowest input voltage required to maintain regulation of the output voltage. An

approximation of the input dropout voltage is:

(4)

Where VDis the voltage drop across the re-circulatory diode. Operating at high switching frequency raises the

minimum input voltage necessary to maintain regulation.

7.4.6 Current Limit

The LM25576 contains a unique current monitoring scheme for control and over-current protection. When set

correctly, the emulated current sense signal provides a signal which is proportional to the buck switch current

with a scale factor of 0.5 V / A. The emulated ramp signal is applied to the current limit comparator. If the

emulated ramp signal exceeds 2.1 V (4.2A) the present current cycle is terminated (cycle-by-cycle current

limiting). In applications with small output inductance and high input voltage the switch current may overshoot

due to the propagation delay of the current limit comparator. If an overshoot should occur, the diode current

sampling circuit will detect the excess inductor current during the off-time of the buck switch. If the sample and

hold DC level exceeds the 2.1 V current limit threshold, the buck switch will be disabled and skip pulses until the

diode current sampling circuit detects the inductor current has decayed below the current limit threshold. This

approach prevents current runaway conditions due to propagation delays or inductor saturation since the inductor

current is forced to decay following any current overshoot.

7.4.7 Soft-Start

The soft-start feature allows the regulator to gradually reach the initial steady state operating point, thus reducing

start-up stresses and surges. The internal soft-start current source, set to 10 µA, gradually increases the voltage

of an external soft-start capacitor connected to the SS pin. The soft-start capacitor voltage is connected to the

reference input of the error amplifier. Various sequencing and tracking schemes can be implemented using

external circuits that limit or clamp the voltage level of the SS pin.

In the event a fault is detected (over-temperature, Vcc UVLO, SD) the soft-start capacitor will be discharged.

When the fault condition is no longer present a new soft-start sequence will commence.

7.4.8 Boost Pin

The LM25576 integrates an N-Channel buck switch and associated floating high voltage level shift / gate driver.

This gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.022

µF ceramic capacitor, connected with short traces between the BST pin and SW pin, is recommended. During

the off-time of the buck switch, the SW pin voltage is approximately –0.5 V and the bootstrap capacitor is

charged from Vcc through the internal bootstrap diode. When operating with a high PWM duty cycle, the buck

switch will be forced off each cycle for 500 ns to ensure that the bootstrap capacitor is recharged.

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Device Functional Modes (continued)

Under very light load conditions or when the output voltage is pre-charged, the SW voltage will not remain low

during the off-time of the buck switch. If the inductor current falls to zero and the SW pin rises, the bootstrap

capacitor will not receive sufficient voltage to operate the buck switch gate driver. For these applications, the

PRE pin can be connected to the SW pin to pre-charge the bootstrap capacitor. The internal pre-charge

MOSFET and diode connected between the PRE pin and PGND turns on each cycle for 265 ns just prior to the

onset of a new switching cycle. If the SW pin is at a normal negative voltage level (continuous conduction mode),

then no current will flow through the pre-charge MOSFET/diode.

7.4.9 Thermal Protection

Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction

temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power reset state,

disabling the output driver and the bias regulator. This feature is provided to prevent catastrophic failures from

accidental device overheating.

RT = [(1 / 300 x 103) ± 580 x 10-9]

135 x 10-12

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 External Components

The procedure for calculating the external components is illustrated with the following design example. The Bill of

Materials for this design is listed in Table 1. The circuit shown in Functional Block Diagram is configured for the

following specifications:

• VOUT =5V

• VIN =7Vto42V

• Fs = 300 kHz

• Minimum load current (for CCM) = 250 mA

• Maximum load current = 3 A

8.1.2 R3 (RT)

RTsets the oscillator switching frequency. Generally, higher frequency applications are smaller but have higher

losses. Operation at 300 kHz was selected for this example as a reasonable compromise for both small size and

high efficiency. The value of RTfor 300 kHz switching frequency can be calculated as follows:

(5)

The nearest standard value of 21 kΩwas chosen for RT.

'VOUT = 'IL x 1

8 x FS x COUT

©ESR +

L1 = 5V x (42V ± 5V)

0.5A x 300 kHz x 42V = 29 PH

L1 = VOUT x (VIN(max) ± VOUT)

IRIPPLE x FS x VIN(max)

IPK+

L1 Current

0 mA

IPK-

IRIPPLE

1/Fs

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Application Information (continued)

8.1.3 L1

The inductor value is determined based on the operating frequency, load current, ripple current, and the

minimum and maximum input voltage (VIN(min), VIN(max)).

Figure 14. Inductor Current Waveform

To keep the circuit in continuous conduction mode (CCM), the maximum ripple current IRIPPLE should be less

than twice the minimum load current, or 0.5 Ap-p. Using this value of ripple current, the value of inductor (L1) is

calculated using the following:

(6)

(7)

This procedure provides a guide to select the value of L1. The nearest standard value (33 µH) will be used. L1

must be rated for the peak current (IPK+) to prevent saturation. During normal loading conditions, the peak current

occurs at maximum load current plus maximum ripple. During an overload condition the peak current is limited to

4.2 A nominal (5.1 A maximum). The selected inductor (see Table 1) has a conservative 6.2 Amp saturation

current rating. For this manufacturer, the saturation rating is defined as the current necessary for the inductance

to reduce by 30%, at 20°C.

8.1.4 C3 (CRAMP)

With the inductor value selected, the value of C3 (CRAMP) necessary for the emulation ramp circuit is:

CRAMP = L x 10-5 (8)

Where L is in Henrys

With L1 selected for 33 µH the recommended value for C3 is 330 pF.

8.1.5 C9, C10

The output capacitors, C9 and C10, smooth the inductor ripple current and provide a source of charge for

transient loading conditions. For this design a 22 µF ceramic capacitor and a 150 µF SP organic capacitor were

selected. The ceramic capacitor provides ultra low ESR to reduce the output ripple voltage and noise spikes,

while the SP capacitor provides a large bulk capacitance in a small volume for transient loading conditions. An

approximation for the output ripple voltage is:

(9)

tss = C4 x 1.225V

10 PA

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Application Information (continued)

8.1.6 D1

A Schottky type re-circulating diode is required for all LM25576 applications. Ultra-fast diodes are not

recommended and may result in damage to the IC due to reverse recovery current transients. The near ideal

reverse recovery characteristics and low forward voltage drop are particularly important diode characteristics for

high input voltage and low output voltage applications common to the LM25576. The reverse recovery

characteristic determines how long the current surge lasts each cycle when the buck switch is turned on. The

reverse recovery characteristics of Schottky diodes minimize the peak instantaneous power in the buck switch

occurring during turn-on each cycle. The resulting switching losses of the buck switch are significantly reduced

when using a Schottky diode. The reverse breakdown rating should be selected for the maximum VIN, plus some

safety margin.

The forward voltage drop has a significant impact on the conversion efficiency, especially for applications with a

low output voltage. “Rated” current for diodes vary widely from various manufacturers. The worst case is to

assume a short circuit load condition. In this case the diode will carry the output current almost continuously. For

the LM25576 this current can be as high as 4.2 A. Assuming a worst case 1 V drop across the diode, the

maximum diode power dissipation can be as high as 4.2 W. For the reference design a 60 V Schottky in a DPAK

package was selected.

8.1.7 C1, C2

The regulator supply voltage has a large source impedance at the switching frequency. Good quality input

capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current

during the on-time. When the buck switch turns on, the current into the VIN pin steps to the lower peak of the

inductor current waveform, ramps up to the peak value, then drops to zero at turn-off. The average current into

VIN during the on-time is the load current. The input capacitance should be selected for RMS current rating and

minimum ripple voltage. A good approximation for the required ripple current rating necessary is IRMS > IOUT / 2.

Quality ceramic capacitors with a low ESR should be selected for the input filter. To allow for capacitor

tolerances and voltage effects, two 2.2 µF, 100 V ceramic capacitors will be used. If step input voltage transients

are expected near the maximum rating of the LM25576, a careful evaluation of ringing and possible spikes at the

device VIN pin should be completed. An additional damping network or input voltage clamp may be required in

these cases.

8.1.8 C8

The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended value

of C8 should be no smaller than 0.1 µF, and should be a good quality, low ESR, ceramic capacitor. A value of

0.47 µF was selected for this design.

8.1.9 C7

The bootstrap capacitor between the BST and the SW pins supplies the gate current to charge the buck switch

gate at turn-on. The recommended value of C7 is 0.022 µF, and should be a good quality, low ESR, ceramic

capacitor.

8.1.10 C4

The capacitor at the SS pin determines the soft-start time, that is the time for the reference voltage and the

output voltage, to reach the final regulated value. The time is determined from:

(10)

For this application, a C4 value of 0.01 µF was chosen which corresponds to a soft-start time of 1 ms.

8.1.11 R5, R6

R5 and R6 set the output voltage level, the ratio of these resistors is calculated from:

R5/R6 = (VOUT / 1.225V) - 1 (11)

R2 = 1.225 x R1

VIN(min) + (5 x 10-6 x R1) ± 1.225

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Application Information (continued)

For a 5 V output, the R5 and R6 ratio calculates to 3.082. The resistors should be chosen from standard value

resistors, a good starting point is selection in the range of 1 kΩ- 10 kΩ. Values of 5.11 kΩfor R5, and 1.65 kΩ

for R6 were selected.

8.1.12 R1, R2, C12

A voltage divider can be connected to the SD pin to set a minimum operating voltage Vin(min) for the regulator. If

this feature is required, the easiest approach to select the divider resistor values is to select a value for R1

(between 10 kΩand 100 kΩrecommended) then calculate R2 from:

(12)

Capacitor C12 provides filtering for the divider. The voltage at the SD pin should never exceed 8 V, when using

an external set-point divider it may be necessary to clamp the SD pin at high input voltage conditions. The

reference design utilizes the full range of the LM25576 (6 V to 42 V); therefore these components can be

omitted. With the SD pin open circuit the LM25576 responds once the Vcc UVLO threshold is satisfied.

8.1.13 R7, C11

A snubber network across the power diode reduces ringing and spikes at the switching node. Excessive ringing

and spikes can cause erratic operation and couple spikes and noise to the output. Voltage spikes beyond the

rating of the LM25576 or the re-circulating diode can damage these devices. Selecting the values for the snubber

is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections

are very short. For the current levels typical for the LM25576 a resistor value between 5 and 20 Ohms is

adequate. Increasing the value of the snubber capacitor results in more damping but higher losses. Select a

minimum value of C11 that provides adequate damping of the SW pin waveform at high load.

8.1.14 R4, C5, C6

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One

advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5.

The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of

the LM25576 is as follows:

DC Gain(MOD) = Gm(MOD) x RLOAD = 2 x RLOAD (13)

The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD,) and output

capacitance (COUT). The corner frequency of this pole is:

fp(MOD) = 1 / (2πRLOAD COUT) (14)

For RLOAD = 5Ωand COUT = 177µF then fp(MOD) = 180Hz

DC Gain(MOD) =2x5=10=20dB

For the design example of Functional Block Diagram the following modulator gain vs. frequency characteristic

was measured as shown in Figure 15.

REF LEVEL

0.000 dB

0.0 deg

100 1k

START 50.000 Hz 10k

STOP 50 000.000 Hz

/DIV

10.000 dB

45.000 deg

GAIN

PHASE

REF LEVEL

0.000 dB

0.0 deg

100 1k

START 50.000 Hz 10k

STOP 50 000.000 Hz

/DIV

10.000 dB

45.000 deg

GAIN

PHASE

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Application Information (continued)

Figure 15. Gain and Phase of Modulator

RLOAD = 5 Ohms and COUT = 177µF

Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a

zero at fZ=1/(2πR4C5). The error amplifier zero cancels the modulator pole leaving a single pole response at

the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable

loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 20 kHz was selected. The

compensation network zero (fZ) should be selected at least an order of magnitude less than the target crossover

frequency. This constrains the product of R4 and C5 for a desired compensation network zero 1 / (2πR4 C5) to

be less than 2 kHz. Increasing R4, while proportionally decreasing C5, increases the error amp gain. Conversely,

decreasing R4 while proportionally increasing C5, decreases the error amp gain. For the design example C5 was

selected for 0.01 µF and R4 was selected for 49.9 kΩ. These values configure the compensation network zero at

320 Hz. The error amp gain at frequencies greater than fZis: R4 / R5, which is approximately 10 (20dB).

Figure 16. Error Amplifier Gain and Phase

The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

REF LEVEL

0.000 dB

0.0 deg

100 1k

START 50.000 Hz 10k

STOP 50 000.000 Hz

/DIV

10.000 dB

45.000 deg

GAIN

PHASE

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Application Information (continued)

Figure 17. Overall Loop Gain and Phase

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be

configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier

compensation components can be designed with the guidelines given. Step load transient tests can be

performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response.

C6 can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value

of C6 must be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer

function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of

the pole added by C6 is: fp2 = fz x C5 / C6.

8.1.15 Bias Power Dissipation Reduction

Buck regulators operating with high input voltage can dissipate an appreciable amount of power for the bias of

the IC. The VCC regulator must step-down the input voltage VIN to a nominal VCC level of 7 V. The large voltage

drop across the VCC regulator translates into a large power dissipation within the Vcc regulator. There are several

techniques that can significantly reduce this bias regulator power dissipation. Figure 18 and Figure 19 depict two

methods to bias the IC from the output voltage. In each case the internal Vcc regulator is used to initially bias the

VCC pin. After the output voltage is established, the VCC pin potential is raised above the nominal 7 V regulation

level, which effectively disables the internal VCC regulator. The voltage applied to the VCC pin should never

exceed 14 V. The VCC voltage should never be larger than the VIN voltage.

BST

VCC

GND

LM25576

COUT

VOUT

BST

VCC

GND

LM25576

VOUT

COUT

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Application Information (continued)

Figure 18. VCC Bias from VOUT for 8 V < VOUT < 14 V

Figure 19. VCC Bias with Additional Winding on the Output Inductor

33P

LM25576

VIN SW

BST

COMP

GND

SS VCC

RAMP

10V - 30V

0.022

0.47330p

OUT

0.01

0.1

0.022

49.9k

10k

1.4k

CSHD6-60

4.4

21k

7.15k

170

-10V

5.11k

3.01k

BST

COMP

RAMP RT VCC

VIN

OUT

GND

9V - 32V

3.3V, 3A

SYNC

0.01P

47p 0.01P

CSHD6-40

3.57k

LM25576

0.1P

49.9k

3.3P

140P

4.7P

0.022P

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8.2 Typical Application

8.2.1 Typical Schematic for High Frequency (1 MHz) Application

Figure 20. Schematic 3.3 V, 3 A, 1 MHz

8.2.2 Typical Schematic for Buck and Boost (Inverting) Application

8.2.3 Detailed Design Procedure

8.2.3.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM25576 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage ( VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

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9 Layout

9.1 Layout Guidelines

9.1.1 PCB Layout and Thermal Considerations

The circuit in Figure 19 serves as both a block diagram of the LM25576 and a typical application board

schematic for the LM25576. In a buck regulator there are two loops where currents are switched very fast. The

first loop starts from the input capacitors, to the regulator VIN pin, to the regulator SW pin, to the inductor then

out to the load. The second loop starts from the output capacitor ground, to the regulator PGND pins, to the

regulator IS pins, to the diode anode, to the inductor and then out to the load. Minimizing the loop area of these

two loops reduces the stray inductance and minimizes noise and possible erratic operation. A ground plane in

the PC board is recommended as a means to connect the input filter capacitors to the output filter capacitors and

the PGND pins of the regulator. Connect all of the low power ground connections (CSS, RT, CRAMP) directly to the

regulator AGND pin. Connect the AGND and PGND pins together through the topside copper area covering the

entire underside of the device. Place several vias in this underside copper area to the ground plane.

The two highest power dissipating components are the re-circulating diode and the LM25576 regulator IC. The

easiest method to determine the power dissipated within the LM25576 is to measure the total conversion losses

(Pin – Pout) then subtract the power losses in the Schottky diode, output inductor and snubber resistor. An

approximation for the Schottky diode loss is P = (1-D) x Iout x Vfwd. An approximation for the output inductor

power is P = IOUT2x R x 1.1, where R is the DC resistance of the inductor and the 1.1 factor is an approximation

for the AC losses. If a snubber is used, an approximation for the damping resistor power dissipation is P = Vin2x

Fsw x Csnub, where Fsw is the switching frequency and Csnub is the snubber capacitor. The regulator has an

exposed thermal pad to aid power dissipation. Adding several vias under the device to the ground plane will

greatly reduce the regulator junction temperature. Selecting a diode with an exposed pad will aid the power

dissipation of the diode.

The most significant variables that affect the power dissipated by the LM25576 are the output current, input

voltage and operating frequency. The power dissipated while operating near the maximum output current and

maximum input volatge can be appreciable. The operating frequency of the LM25576 evaluation board has been

designed for 300 kHz. When operating at 3 A output current with a 42 V input the power dissipation of the

LM25576 regulator is approximately 1.9 W.

The junction-to-ambient thermal resistance of the LM25576 will vary with the application. The most significant

variables are the area of copper in the PC board, the number of vias under the IC exposed pad and the amount

of forced air cooling provided. Referring to the evaluation board artwork, the area under the LM25576

(component side) is covered with copper and there are 5 connection vias to the solder side ground plane.

Additional vias under the IC will have diminishing value as more vias are added. The integrity of the solder

connection from the IC exposed pad to the PC board is critical. Excessive voids will greatly diminish the thermal

dissipation capacity. The junction-to-ambient thermal resistance of the LM25576 mounted in the evaluation board

varies from 45°C/W with no airflow to 25°C/W with 900 LFM (Linear Feet per Minute). With a 25°C ambient

temperature and no airflow, the predicted junction temperature for the LM25576 will be 25 + (45 x 1.9) = 110°C.

If the evaluation board is operated at 3 A output current and 42 V input voltage for a prolonged period of time the

thermal shutdown protection within the IC may activate. The IC will turn off allowing the junction to cool, followed

by restart with the soft-start capacitor reset to zero.

Table 1. 5 V, 3 A Demo Board Bill of Materials

ITEM PART NUMBER DESCRIPTION VALUE

C 1 C4532X7R2A225M CAPACITOR, CER, TDK 2.2µ, 100V

C 2 C4532X7R2A225M CAPACITOR, CER, TDK 2.2µ, 100V

C 3 C0805C331G1GAC CAPACITOR, CER, KEMET 330p, 100V

C 4 C2012X7R2A103K CAPACITOR, CER, TDK 0.01µ, 100V

C 5 C2012X7R2A103K CAPACITOR, CER, TDK 0.01µ, 100V

C 6 OPEN NOT USED

C 7 C2012X7R2A223K CAPACITOR, CER, TDK 0.022µ, 100V

C 8 C2012X7R1C474M CAPACITOR, CER, TDK 0.47µ, 16V

C 9 C3225X7R1C226M CAPACITOR, CER, TDK 22µ, 16V

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Layout Guidelines (continued)

Table 1. 5 V, 3 A Demo Board Bill of Materials (continued)

ITEM PART NUMBER DESCRIPTION VALUE

C 10 EEFHE0J151R CAPACITOR, SP, PANASONIC 150µ, 6.3V

C 11 C0805C331G1GAC CAPACITOR, CER, KEMET 330p, 100V

C 12 OPEN NOT USED

D 1 CSHD6-60C DIODE, 60V, CENTRAL

6CWQ10FN DIODE, 100V, IR (D1-ALT)

L 1 DR127-330 INDUCTOR, COOPER 33µH

R 1 OPEN NOT USED

R 2 OPEN NOT USED

R 3 CRCW08052102F RESISTOR 21kΩ

R 4 CRCW08054992F RESISTOR 49.9kΩ

R 5 CRCW08055111F RESISTOR 5.11kΩ

R 6 CRCW08051651F RESISTOR 1.65kΩ

R 7 CRCW2512100J RESISTOR 10, 1W

U 1 LM25576 REGULATOR, TEXAS INSTRUMENTS

9.2 Layout Example

Figure 21. Component Side

Figure 22. Solder Side

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Layout Example (continued)

Figure 23. Silkscreen

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10 Device and Documentation Support

10.1 Device Support

10.1.1 Developmental Support

10.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM25575 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

10.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

10.4 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Aug-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM25576MH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM25576

LM25576MHX NRND HTSSOP PWP 20 2500 TBD Call TI Call TI -40 to 125 LM25576

LM25576MHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM25576

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

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flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

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PACKAGE OPTION ADDENDUM

www.ti.com 18-Aug-2017

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM25576 :

•Automotive: LM25576-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM25576MHX HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

LM25576MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM25576MHX HTSSOP PWP 20 2500 367.0 367.0 35.0

LM25576MHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

Pack Materials-Page 2

MECHANICAL DATA

PWP0020A

www.ti.com

MXA20A (Rev C)

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