SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DWide Operating Voltage Range of 2 V to 6 V
DHigh-Current Outputs Can Drive Up To
15 LSTTL Loads
DLow Power Consumption, 80-µA Max ICC
DTypical tpd = 15 ns
D±6-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
D8-Bit Serial-In, Parallel-Out Shift Registers
With Storage
DIndependent Direct Overriding Clears on
Shift and Storage Registers
DIndependent Clocks for Both Shift and
Storage Registers
SN54HC594 ...J OR W PACKAGE
SN74HC594 . . . D, DW, OR N PACKAGE
(TOP VIEW)
SN54HC594 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QB
QC
QD
QE
QF
QG
QH
GND
VCC
QA
SER
RCLR
RCLK
SRCLK
SRCLR
QH′
3212019
910111213
4
5
6
7
8
18
17
16
15
14
SER
RCLR
NC
RCLK
SRCLK
QD
QE
NC
QF
QG
Q
NC
SRCLR
H
GND
NC
C
QB
VCC
QA
Q
H
Q′
description/ordering information
The ’HC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. Separate clocks and direct overriding clear (RCLR, SRCLR) inputs are provided on both the shift and
storage registers. A serial (QH′) output is provided for cascading purposes.
Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks
are connected together, the shift register always is one count pulse ahead of the storage register.
The parallel (QA−QH) outputs have high-current capability. QH′ is a standard output.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74HC594N SN74HC594N
Tube of 40 SN74HC594D
−40°C to 85°C
SOIC − D Reel of 2500 SN74HC594DR HC594
−40°C to 85°C
SOIC − D
Reel of 250 SN74HC594DT
HC594
SOIC − DW
Tube of 40 SN74HC594DW
HC594
SOIC − DW Reel of 2000 SN74HC594DWR HC594
CDIP − J Tube of 25 SNJ54HC594J SNJ54HC594J
−55°C to 125°CCFP − W Tube of 150 SNJ54HC594W SNJ54HC594W
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54HC594FK SNJ54HC594FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
!"#$ $%$
&& $'("%$ !((#$ % ' )!*+%$ %#, (! $'("
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(!$ )(#$0 # $ $##%(+/ $+!# #$0 ' %++
)%(%"##(,
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
FUNCTION
SER SRCLK SRCLR RCLK RCLR
FUNCTION
X X L X X Shift register is cleared.
L↑H X X First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
H↑H X X First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
L↓H X X Shift register state is not changed.
XX X X L Storage register is cleared.
XXX↑H Shift register data is stored in the storage register.
X X X ↓HStorage register state is not changed.
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
R
3R
C3
3S
1D
C1
R
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
R
3R
C3
3S
2R
C2
R
2S
13
12
10
11
14 15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QH′
RCLR
SRCLR
RCLK
SRCLK
SER
Pin numbers shown are for the D, DW, J, N, and W packages.
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
QA
QB
QC
QD
QE
QF
QG
QH
QH′
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 57°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HC594 SN74HC594
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage VCC = 4.5 V 3.15 3.15 V
VIH
High-level input voltage
VCC = 6 V 4.2 4.2
V
VCC = 2 V 0.5 0.5
V
IL
Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VIL
Low-level input voltage
VCC = 6 V 1.8 1.8
V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
t
t
Input transition (rise and fall) time VCC = 4.5 V 500 500 ns
tt
Input transition (rise and fall) time
VCC = 6 V 400 400
ns
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC594 SN74HC594
UNIT
PARAMETER
TEST CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
I
OH
= −20 µA4.5 V 4.4 4.499 4.4 4.4
IOH = −20 µA
6 V 5.9 5.999 5.9 5.9
V
OH
V
I
= V
IH
or V
IL
QH′, IOH = −4 mA
4.5 V
3.98 4.3 3.7 3.84 V
VOH
VI = VIH or VIL
QA−QH, IOH = −6 mA 4.5 V 3.98 4.3 3.7 3.84
V
QH′, IOH = −5.2 mA
6 V
5.48 5.8 5.2 5.34
QA−QH, IOH = −7.8 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
I
OL
= 20 µA4.5 V 0.001 0.1 0.1 0.1
IOL = 20 µA
6 V 0.001 0.1 0.1 0.1
V
OL
V
I
= V
IH
or V
IL
QH′, IOL = 4 mA
4.5 V
0.17 0.26 0.4 0.33 V
VOL
VI = VIH or VIL
QA−QH, IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33
V
QH′, IOL = 5.2 mA
6 V
0.15 0.26 0.4 0.33
QA−QH, IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
IOZ VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5µA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
Ci2 V
to 6 V 3 10 10 10 pF
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SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C SN54HC594 SN74HC594
UNIT
V
CC MIN MAX MIN MAX MIN MAX
UNIT
2 V 5 3.3 4
f
clock
Clock frequency 4.5 V 25 17 20 MHz
fclock
Clock frequency
6 V 29 20 24
MHz
2 V 100 150 125
SRCLK or RCLK high or low 4.5 V 20 30 25
tw
Pulse duration
SRCLK or RCLK high or low
6 V 17 25 21
ns
twPulse duration 2 V 100 150 125 ns
SRCLR or RCLR low 4.5 V 20 30 25
SRCLR or RCLR low
6 V 17 25 21
2 V 90 135 110
SER before SRCLK↑4.5 V 18 27 22
SER before SRCLK↑
6 V 15 23 19
2 V 90 135 110
SRCLK↑ before RCLK↑†4.5 V 18 27 22
SRCLK↑ before RCLK↑†
6 V 15 23 19
2 V 50 75 63
t
su
Setup time SRCLR low before RCLK↑4.5 V 10 15 13 ns
tsu
Setup time
SRCLR low before RCLK↑
6 V 9 13 11
ns
2 V 20 20 20
SRCLR high (inactive) before SRCLK↑4.5 V 10 10 10
SRCLR high (inactive) before SRCLK↑
6 V 10 10 10
2 V 5 5 5
RCLR high (inactive) before SRCLK↑4.5 V 5 5 5
RCLR high (inactive) before SRCLK↑
6 V 5 5 5
2 V 5 5 5
t
h
Hold time, SER after SRCLK↑4.5 V 5 5 5 ns
th
Hold time, SER after SRCLK
6 V 5 5 5
ns
†This setup time ensures that the output register receives stable data from the shift-register outputs. The clocks may be tied together, in which
case the output register is one clock pulse behind the shift register.
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SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C SN54HC594 SN74HC594
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 5 8 3.3 4
f
max
4.5 V 25 35 17 20 MHz
fmax
6 V 29 40 20 24
MHz
2 V 50 150 225 185
SRCLK Q
H
′4.5 V 20 30 45 37
tpd
SRCLK
QH
6 V 15 25 38 31
ns
tpd 2 V 50 150 225 185 ns
RCLK Q
A
−Q
H
4.5 V 20 30 45 37
RCLK
QA−QH
6 V 15 25 38 31
2 V 50 150 225 185
SRCLR Q
H
′4.5 V 20 30 45 37
tPHL
SRCLR
QH
6 V 15 25 38 31
ns
tPHL 2 V 50 125 185 155 ns
RCLR Q
A
−Q
H
4.5 V 20 25 37 31
RCLR
QA−QH
6 V 15 21 31 26
2 V 38 75 110 95
Q
H
′4.5 V 8 15 22 19
tt
QH
6 V 6 13 19 16
ns
t
t2 V 38 60 90 75
ns
Q
A
−Q
H
4.5 V 8 12 18 15
QA−QH
6 V 6 10 15 13
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C SN54HC594 SN74HC594
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 90 200 300 250
t
pd
RCLK Q
A
−Q
H
4.5 V 23 40 60 50 ns
tpd
RCLK
QA−QH
6 V 19 34 51 43
ns
2 V 90 200 300 250
t
PHL
RCLR Q
A
−Q
H
4.5 V 23 40 60 50 ns
tPHL
RCLR
QA−QH
6 V 19 34 51 43
ns
2 V 45 210 315 265
t
t
Q
A
−Q
H
4.5 V 17 42 63 53 ns
tt
QA−QH
6 V 13 36 53 45
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 395 pF
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SCLS040F − DECEMBER 1982 − REVISED OCTOBER 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
50%
High-Level
Pulse 50%
V
CC
0 V
50% 50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VC
C
VO
H
VO
L
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VO
H
VO
L
tr
tf
tPHL tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
F. tf and tr are the same as tt.
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74HC594D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DWE4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DWR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC594N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74HC594NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC594DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC594DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Jan-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC594DR SOIC D 16 2500 333.2 345.9 28.6
SN74HC594DWR SOIC DW 16 2000 366.0 364.0 50.0
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Jan-2012
Pack Materials-Page 2
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