SCLS040F - DECEMBER 1982 - REVISED OCTOBER 2003 D Wide Operating Voltage Range of 2 V to 6 V D High-Current Outputs Can Drive Up To D Low Input Current of 1 A Max D 8-Bit Serial-In, Parallel-Out Shift Registers 15 LSTTL Loads With Storage D Low Power Consumption, 80-A Max ICC D Typical tpd = 15 ns D 6-mA Output Drive at 5 V SN54HC594 . . . J OR W PACKAGE SN74HC594 . . . D, DW, OR N PACKAGE (TOP VIEW) 14 4 13 5 6 12 11 7 10 8 9 QD QE NC QF QG 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 SER RCLR NC RCLK SRCLK SRCLR 3 VCC QA SER RCLR RCLK SRCLK SRCLR QH NC VCC QA 15 GND NC Q H 16 2 SN54HC594 . . . FK PACKAGE (TOP VIEW) QC QB 1 D Shift and Storage Registers Independent Clocks for Both Shift and Storage Registers QH QB QC QD QE QF QG QH GND D Independent Direct Overriding Clears on NC - No internal connection description/ordering information The 'HC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clear (RCLR, SRCLR) inputs are provided on both the shift and storage registers. A serial (QH) output is provided for cascading purposes. Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register always is one count pulse ahead of the storage register. The parallel (QA-QH) outputs have high-current capability. QH is a standard output. ORDERING INFORMATION PACKAGE TA PDIP - N -40C to 85C TOP-SIDE MARKING Tube of 25 SN74HC594N Tube of 40 SN74HC594D Reel of 2500 SN74HC594DR Reel of 250 SN74HC594DT Tube of 40 SN74HC594DW Reel of 2000 SN74HC594DWR CDIP - J Tube of 25 SNJ54HC594J SNJ54HC594J CFP - W Tube of 150 SNJ54HC594W SNJ54HC594W LCCC - FK Tube of 55 SNJ54HC594FK SOIC - D SOIC - DW -55C -55 C to 125 125C C ORDERABLE PART NUMBER SN74HC594N HC594 HC594 SNJ54HC594FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated !"#$ $%$ && $'("%$ !((#$ % ' )!*+%$ %#, (! $'(" )#'%$ )#( # #(" ' #-% $(!"#$ %$%( .%((%$/, (!$ )(#$0 # $ $##%(+/ $+!# #$0 ' %++ )%(%"##(, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCLS040F - DECEMBER 1982 - REVISED OCTOBER 2003 FUNCTION TABLE INPUTS 2 FUNCTION SER SRCLK SRCLR RCLK RCLR X X L X X Shift register is cleared. L H X X First stage of shift register goes low. Other stages store the data of previous stage, respectively. H H X X First stage of shift register goes high. Other stages store the data of previous stage, respectively. L H X X Shift register state is not changed. X X X X L Storage register is cleared. X X X H Shift register data is stored in the storage register. X X X H Storage register state is not changed. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS040F - DECEMBER 1982 - REVISED OCTOBER 2003 logic diagram (positive logic) RCLR RCLK SRCLR SRCLK SER 13 12 10 11 14 1D C1 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 2S 2R C2 R R 3R C3 3S 15 1 2 3 4 5 6 7 9 Pin numbers shown are for the D, DW, J, N, and W packages. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 QA QB QC QD QE QF QG QH QH 3 SCLS040F - DECEMBER 1982 - REVISED OCTOBER 2003 timing diagram SRCLK SER RCLK SRCLR RCLR QA QB QC QD QE QF QG QH QH absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS040F - DECEMBER 1982 - REVISED OCTOBER 2003 recommended operating conditions (see Note 3) SN54HC594 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO Input voltage NOM MAX 2 5 6 NOM MAX 2 5 6 1.5 3.15 3.15 4.2 4.2 0 VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 VCC VCC VCC = 2 V VCC = 4.5 V Input transition (rise and fall) time MIN 1.5 0 Output voltage tt MIN VCC = 4.5 V VCC = 6 V Low-level input voltage SN74HC594 0 VCC VCC 0 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN74HC594 2V 1.9 1.998 1.9 1.9 IOH = -20 A 4.5 V 4.4 4.499 4.4 4.4 VI = VIH or VIL QH, IOH = -4 mA QA-QH, IOH = -6 mA QH, IOH = -5.2 mA QA-QH, IOH = -7.8 mA IOL = 20 A VOL SN54HC594 VCC 6V VOH TA = 25C MIN TYP MAX TEST CONDITIONS VI = VIH or VIL QH, IOL = 4 mA QA-QH, IOL = 6 mA QH, IOL = 5.2 mA QA-QH, IOL = 7.8 mA II IOZ VI = VCC or 0 VO = VCC or 0 ICC VI = VCC or 0, IO = 0 Ci 4.5 V 6V MIN MAX MIN 5.9 5.999 5.9 5.9 3.98 4.3 3.7 3.84 3.98 4.3 3.7 3.84 5.48 5.8 5.2 5.34 5.48 5.8 5.2 MAX V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 0.17 0.26 0.4 0.33 0.15 0.26 0.4 0.33 4.5 V 6V UNIT V 0.15 0.26 0.4 0.33 6V 0.1 100 1000 1000 nA 6V 0.01 0.5 10 5 A 8 160 80 A 10 10 10 pF 6V 2V to 6 V 3 1 $'("%$ $#($ )(! $ # '("%2# ( #0$ )%# ' #2#+)"#$, %(%#( %% %$ #( )#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(2# # (0 %$0# ( $$!# ## )(! .! $#, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SCLS040F - DECEMBER 1982 - REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency SRCLK or RCLK high or low tw Pulse duration SRCLR or RCLR low SER before SRCLK SRCLK before RCLK tsu Setup time SRCLR low before RCLK SRCLR high (inactive) before SRCLK RCLR high (inactive) before SRCLK th Hold time, SER after SRCLK SRCLK TA = 25C MIN MAX SN54HC594 MIN MAX SN74HC594 MIN MAX 2V 5 3.3 4 4.5 V 25 17 20 6V 29 20 24 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 90 135 110 4.5 V 18 27 22 6V 15 23 19 2V 90 135 110 4.5 V 18 27 22 6V 15 23 19 2V 50 75 63 4.5 V 10 15 13 6V 9 13 11 2V 20 20 20 4.5 V 10 10 10 6V 10 10 10 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 UNIT MHz ns ns ns This setup time ensures that the output register receives stable data from the shift-register outputs. The clocks may be tied together, in which case the output register is one clock pulse behind the shift register. 1 $'("%$ $#($ )(! $ # '("%2# ( #0$ )%# ' #2#+)"#$, %(%#( %% %$ #( )#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(2# # (0 %$0# ( $$!# ## )(! .! $#, 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCLS040F - DECEMBER 1982 - REVISED OCTOBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax SRCLK QH H tpd RCLK QA-QH SRCLR QH H tPHL RCLR QA-QH QH H tt QA-QH VCC MIN TA = 25C TYP MAX SN54HC594 MIN MAX SN74HC594 MIN 2V 5 8 3.3 4 4.5 V 25 35 17 20 6V 29 40 20 24 MAX UNIT MHz 2V 50 150 225 185 4.5 V 20 30 45 37 6V 15 25 38 31 2V 50 150 225 185 4.5 V 20 30 45 37 6V 15 25 38 31 2V 50 150 225 185 4.5 V 20 30 45 37 6V 15 25 38 31 2V 50 125 185 155 4.5 V 20 25 37 31 6V 15 21 31 26 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 2V 38 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) RCLK tPHL QA-QH RCLR QA-QH tt QA-QH VCC MIN TA = 25C TYP MAX SN54HC594 MIN MAX SN74HC594 MIN MAX 2V 90 200 300 250 4.5 V 23 40 60 50 6V 19 34 51 43 2V 90 200 300 250 4.5 V 23 40 60 50 6V 19 34 51 43 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 UNIT ns ns ns operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS TYP UNIT No load 395 pF 1 $'("%$ $#($ )(! $ # '("%2# ( #0$ )%# ' #2#+)"#$, %(%#( %% %$ #( )#'%$ %(# #0$ 0%+, #-% $(!"#$ (##(2# # (0 %$0# ( $$!# ## )(! .! $#, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SCLS040F - DECEMBER 1982 - REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. F. tf and tr are the same as tt. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74HC594D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DWE4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC594N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74HC594NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Jan-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC594DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC594DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Jan-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC594DR SN74HC594DWR SOIC D 16 2500 333.2 345.9 28.6 SOIC DW 16 2000 366.0 364.0 50.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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