R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX Electrical Specifications Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. All specifications subject to change without notice. XC4000EX DC Characteristics Absolute Maximum Ratings Symbol Description VCC Supply voltage relative to GND Value Units -0.5 to +7.0 V VIN Input voltage relative to GND (Note 1) -0.5 to VCC +0.5 V VTS Voltage applied to 3-state output (Note 1) -0.5 to VCC +0.5 V VCCt Longest Supply Voltage Rise Time from 1 V to 4 V 50 ms TSTG Storage temperature (ambient) -65 to +150 C TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 C Ceramic packages +150 C Plastic packages +125 C TJ Junction Temperature Note 1: Maximum DC excursion above Vcc or below Ground must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. Maximum total combined current on all dedicated inputs and Tri-state outputs must not exceed 200 mA. During transitions, the device pins may undershoot to -2.0 V or overshoot toVCC +2.0 V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. May 14, 1999 (Version 1.6) 6-87 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays Recommended Operating Conditions Symbol VCC Description Min Max Units Supply voltage relative to GND, TJ = 0 C to +85C Commercial 4.75 5.25 V Supply voltage relative to GND, TJ = -40C to +100C Industrial 4.5 5.5 V TTL inputs 2.0 VCC V 70% 100% VCC TTL inputs 0 0.8 V CMOS inputs 0 20% VCC 250 ns VIH High-level input voltage (Note1) VIL Low-level input voltage (Note1) TIN Input signal transition time CMOS inputs Note 1: Maximum DC excursion above Vcc or below Ground must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. Maximum total combined current on all dedicated inputs and Tri-state outputs must not exceed 200 mA. During transitions, the device pins may undershoot to -2.0 V or overshoot toVCC +2.0 V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Notes: At junction temperatures above those listed , all delay parameters increase by 0.35% per C. Input and output measurement thresholds for TTL are 1.5 V and for CMOS are 2.5 V. DC Characteristics Over Recommended Operating Conditions Symbol Description Min Max Units High-level output voltage @ IOH = -4.0 mA, VCC min TTL outputs High-level output voltage @ IOH = -1.0 mA CMOS outputs VOL Low-level output voltage @ IOL = 12.0 mA, VCC min (Note 1) TTL outputs 0.4 V CMOS outputs 0.4 V VDR Data Retention Supply Voltage (below which configuration data may be lost) ICCO Quiescent FPGA supply current (Note 2) VOH IL CIN V VCC-0.5 V 3.0 V 25 mA +10 A BGA, SBGA, PQ, HQ, MQ packages 10 pF PGA packages 16 pF Input or output leakage current Input capacitance (sample tested) 2.4 -10 IRPU Pad pull-up (when selected) @ Vin = 0 V (sample tested) 0.02 0.25 mA IRPD Pad pull-down (when selected) @ Vin = 5.5 V (sample tested) 0.02 0.25 mA IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.3 2.0 mA Note 1: With up to 64 pins simultaneously sinking 12 mA. Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND. 6-88 May 14, 1999 (Version 1.6) R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX Switching Characteristics Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Global Buffer Switching Characteristic Guidelines Speed Grade -4 -3 -2 Units Description Symbol Device Max Max Max From pad through Global Low Skew buffer, to any clock K TGLS XC4028EX XC4036EX 9.2 9.8 7.5 7.9 6.4 7.1 ns ns From pad through Global Early buffer, to any clock K in same quadrant TGE XC4028EX XC4036EX 5.7 5.9 4.4 4.6 4.2 4.4 ns ns Horizontal Longline Switching Characteristic Guidelines Speed Grade Description -4 -3 -2 Units Symbol Device Max Max Max I going High or Low to Horizontal Longline going High or Low, while T is Low. Buffer is constantly active. TIO1 XC4028EX XC4036EX 13.7 16.5 11.3 13.6 10.9 13.2 ns ns T going Low to Horizontal Longline going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. TON XC4028EX XC4036EX 14.7 17.4 12.1 14.4 11.7 14.0 ns ns I going High or Low to half of a Horizontal Longline going High or Low, while T is Low. Buffer is constantly active. THIO1 XC4028EX XC4036EX 6.3 7.3 5.6 6.0 4.6 5.7 ns ns T going Low to half of a Horizontal Longline going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. THON XC4028EX XC4036EX 7.2 8.2 6.4 6.8 5.4 6.5 ns ns TBUF driving a Horizontal Longline TBUF driving Half a Horizontal Longline Note: These values include a minimum load of one output, spaced as far as possible from the activated pullup(s). Use the static timing analyzer to determine the delay for each destination. May 14, 1999 (Version 1.6) 6-89 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX CLB Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devicees unless otherwise noted. CLB Switching Characteristic Guidelines Description Speed Grade Symbol Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H' to X/Y outputs F/G inputs via transparent latch to Q outputs C inputs via SR/H0 via H' to X/Y outputs C inputs via H1 via H' to X/Y outputs C inputs via DIN/H2 via H' to X/Y outputs C inputs via EC, DIN/H2 to YQ, XQ output (bypass) TILO TIHO TITO THH0O THH1O THH2O TCBYP CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Carry Net Delay, COUT to CIN TOPCY TASCY TINCY TSUM TBYP TNET -4 Min -3 Max Min 2.2 3.8 3.2 3.6 3.0 3.6 2.0 -2 Max Min 1.8 3.2 2.7 3.0 2.5 3.0 1.6 2.5 4.1 1.9 3.0 0.60 0.18 Max 1.5 2.7 2.5 2.5 2.3 2.5 1.4 2.2 3.6 1.6 2.6 0.50 0.15 1.9 3.1 1.4 2.2 0.40 0.15 Units ns ns ns ns ns ns ns ns ns ns ns ns ns Sequential Delays Clock K to Flip-Flop outputs Q Clock K to Latch outputs Q Setup Time before Clock K F/G inputs F/G inputs via H' C inputs via H0 through H' C inputs via H1 through H' C inputs via H2 through H' C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F'/G' CIN input via F'/G' and H' TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK 1.3 3.0 2.8 2.2 2.8 1.2 1.2 0.8 2.2 3.9 1.1 2.5 2.3 1.8 2.3 0.9 1.0 0.7 1.8 3.2 1.1 2.2 2.0 1.8 2.0 0.9 0.9 0.6 2.1 3.2 ns ns ns ns ns ns ns ns ns ns Hold Time after Clock K F/G inputs F/G inputs via H' C inputs via SR/H0 through H' C inputs via H1 through H' C inputs via DIN/H2 through H' C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) TCKI TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns ns ns ns ns ns ns ns TCH TCL 3.5 3.5 3.0 3.0 3.0 3.0 ns ns TRPW TRIO 3.5 TCKO TCKLO Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q (XC4028EX) Delay from GSR input to any Q (XC4036EX) TMRW TMRQ TMRQ Toggle Frequency ) (for export control purposes) FTOG 6-90 2.2 2.2 1.9 1.9 3.0 1.7 1.7 3.0 ns ns 4.5 3.8 3.6 ns ns 13.0 22.8 24.0 143 11.5 19.0 21.0 166 11.5 19.0 21.0 166 ns ns ns MHz May 14, 1999 (Version 1.6) R XC4000E and XC4000X Series Field Programmable Gate Arrays CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Single Port RAM Speed Grade -4 -3 -2 Units Size Symbol Min Max Min Max Min Max Address write cycle time (clock K period) 16x2 32x1 TWCS TWCTS 11.0 11.0 9.0 9.0 9.0 9.0 ns ns Clock K pulse width (active edge) 16x2 32x1 TWPS TWPTS 5.5 5.5 4.5 4.5 4.5 4.5 ns ns Address setup time before clock K 16x2 32x1 TASS TASTS 2.7 2.6 2.3 2.2 2.2 2.2 ns ns Address hold time after clock K 16x2 32x1 TAHS TAHTS 0 0 0 0 0 0 ns ns DIN setup time before clock K 16x2 32x1 TDSS TDSTS 2.4 2.9 2.0 2.5 2.0 2.5 ns ns DIN hold time after clock K 16x2 32x1 TDHS TDHTS 0 0 0 0 0 0 ns ns WE setup time before clock K 16x2 32x1 TWSS TWSTS 2.3 2.1 2.0 1.8 2.0 1.8 ns ns WE hold time after clock K 16x2 32x1 TWHS TWHTS 0 0 0 0 0 0 ns ns Data valid after clock K 16x2 32x1 TWOS TWOTS Write Operation Notes:: 8.2 10.1 6.8 8.4 6.8 8.2 ns ns Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Applicable Read timing specifications are identical to Level-Sensitive Read timing. Dual-Port RAM Speed Grade -4 -3 -2 Units Size Symbol Min 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS 11.0 5.5 3.1 0 2.9 0 2.1 0 Max Min Max Min Max Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K Note:: 9.0 4.5 2.6 0 2.5 0 1.8 0 9.4 9.0 4.5 2.5 0 2.5 0 1.8 0 7.8 7.8 ns ns ns ns ns ns ns ns ns Applicable Read timing specifications are identical to Level-Sensitive Read timing. May 14, 1999 (Version 1.6) 6-91 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays CLB Single-Port RAM Synchronous (Edge-Triggered) Write Timing Waveforms TWPS WCLK (K) TWHS TWSS WE TDSS TDHS TASS TAHS DATA IN ADDRESS TILO TILO TWOS DATA OUT OLD NEW X6461 CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing Waveforms TWPDS WCLK (K) TWSDS TWHDS TDSDS TDHDS TASDS TAHDS WE DATA IN ADDRESS TILO TILO TWODS DATA OUT OLD NEW X6474 6-92 May 14, 1999 (Version 1.6) R XC4000E and XC4000X Series Field Programmable Gate Arrays CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Speed Grades -4 -3 -2 Units Description Size Symbol Min Max Min Max Min Max Address write cycle time 16x2 32x1 TWC TWCT 10.6 10.6 9.2 9.2 8.0 8.0 ns ns Write Enable pulse width (High) 16x2 32x1 TWP TWPT 5.3 5.3 4.6 4.6 4.0 4.0 ns ns Address setup time before WE 16x2 32x1 TAS TAST 2.8 2.9 2.4 2.5 2.0 2.0 ns ns Address hold time after end of WE 16x2 32x1 TAH TAHT 1.7 1.7 1.4 1.4 1.4 1.4 ns ns DIN setup time before end of WE 16x2 32x1 TDS TDST 1.1 1.1 0.9 0.9 0.8 0.8 ns ns DIN hold time after end of WE 16x2 32x1 TDH TDHT 6.6 6.6 5.7 5.7 5.0 5.0 ns ns Address read cycle time 16x2 32x1 TRC TRCT 4.5 6.5 3.1 5.5 3.1 5.5 ns ns Data valid after address change (no Write Enable) 16x2 32x1 TILO TIHO Write Operation Read Operation 2.2 3.8 1.8 3.2 1.5 2.7 ns ns Read Operation, Clocking Data into Flip-Flop Address setup time before clock K 16x2 32x1 TICK TIHCK 1.5 3.2 1.2 2.6 1.2 2.6 ns ns Data valid after WE goes active (DIN stable before WE) 16x2 32x1 TWO TWOT 6.5 7.4 5.7 6.5 4.9 5.6 ns ns Data valid after DIN (DIN changes during WE) 16x2 32x1 TDO TDOT 7.7 8.2 6.7 7.2 5.8 6.2 ns ns Read During Write Read During Write, Clocking Data into Flip-Flop WE setup time before clock K 16x2 32x1 TWCK TWCKT 7.1 9.2 6.2 8.1 5.5 7.0 ns ns Data setup time before clock K 16x2 32x1 TDCK TDCKT 5.9 8.4 5.2 7.4 4.6 6.4 ns ns Note: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. May 14, 1999 (Version 1.6) 6-93 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays CLB RAM Asynchronous (Level-Sensitive) Timing Waveforms T WC ADDRESS WRITE TAS T WP T AH WRITE ENABLE T DS DATA IN REQUIRED READ WITHOUT WRITE X,Y OUTPUTS T DH T ILO VALID VALID READ, CLOCKING DATA INTO FLIP-FLOP T ICK T CH CLOCK T CKO VALID (OLD) XQ, YQ OUTPUTS VALID (NEW) READ DURING WRITE T WP WRITE ENABLE T DH DATA IN (stable during WE) T WO X, Y OUTPUTS VALID DATA IN (changing during WE) OLD VALID NEW T DO T WO X, Y OUTPUTS VALID (PREVIOUS) VALID (OLD) VALID (NEW) READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP T WP WRITE ENABLE T WCK T DCK DATA IN CLOCK T CKO XQ, YQ OUTPUTS X2640 6-94 May 14, 1999 (Version 1.6) R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX Pin-to-Pin Output Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000EX devices unless otherwise noted. Output Flip-Flop, Clock to Out Guidelines Speed Grade -4 -3 -2 Description Symbol Device Max Max Max Global Low Skew Clock to TTL Output (fast) using OFF TICKOF XC4028EX XC4036EX 16.6 17.2 13.7 14.1 12.4 13.1 ns ns Global Early Clock to TTL Output (fast) using OFF TICKEOF XC4028EX XC4036EX 13.1 13.3 10.6 10.8 10.2 10.4 ns ns Speed Grade -4 -3 -2 Units OFF = Output Flip Flop Output MUX, Clock to Out Guidelines Units Description Symbol Device Max Max Max Global Low Skew Clock to TTL Output (fast) using OMUX TPFPF XC4028EX XC4036EX 15.9 16.5 13.1 13.5 11.8 12.5 ns ns Global Early Clock to TTL Output (fast) using OMUX TPEFPF XC4028EX XC4036EX 12.4 12.6 10.0 10.2 9.6 9.8 ns ns OMUX = Output MUX Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Output timing is measured at TTL threshold with 50 pF external capacitive load. Set-up time is measured with the fastest route and the lightest load. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions. Output Level and Slew Rate Adjustments The following table must be used to adjust output parameters and output switching characteristics. Description For TTL output FAST add For TTL output SLOW add Speed Grade Symbol Device All Devices TTTLOF -4 Max 0 -3 Max 0 -2 Max 0 Units ns TTTLO All Devices 2.9 2.4 2.4 ns For CMOS FAST output add TCMOSOF All Devices 1.0 0.8 0.8 ns For CMOS SLOW output add TCMOSO All Devices 3.6 3.0 3.0 ns May 14, 1999 (Version 1.6) 6-95 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX Pin-to-Pin Input Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000EX devices unless otherwise noted Global Low Skew Clock, Set-Up and Hold Guidelines Description Input Setup Time, using Global Low Skew clock and IFF (full delay) Input Hold Time, using Global Low Skew clock and IFF (full delay) Speed Grade Symbol Device TPSD XC4028EX XC4036EX TPHD XC4028EX XC4036EX -4 Min 8.0 8.0 0 0 -3 Min 6.8 6.8 0 0 -2 Min 6.8 6.8 0 0 -4 Min 6.5 6.5 0 0 -3 Min 5.4 5.4 0 0 -2 Min 5.4 5.4 0 0 Units ns ns ns ns IFF = Input Flip-Flop or Latch Global Early Clock, Set-Up and Hold for IF Guidelines Description Symbol Input Setup Time, using Global Early clock and IFF TPSEP (partial delay) Input Hold Time, using Global Early clock and IFF (par- TPHEP tial delay) Speed Grade Device XC4028EX XC4036EX XC4028EX XC4036EX Units ns ns ns ns IFF = Input Flip-Flop or Latch Note: Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.6 ns for BUFGE #s 1, 2, 5 and 6. Global Early Clock, Set-Up and Hold for FCL Guidelines Description Input Setup Time, using Global Early clock and FCL (partial delay) Input Hold Time, using Global Early clock and FCL (partial delay) Symbol TPFSEP TPFHEP Speed Grade Device XC4028EX XC4036EX XC4028EX XC4036EX -4 Min 3.4 4.4 0 0 -3 Min 3.4 4.2 0 0 -2 Min 3.4 4.2 0 0 Units ns ns ns ns FCL = Fast Capture Latch Notes: For CMOS input levels, see the "Input Threshold Adjustments" on page 96. Setup time is measured with the fastest route and the lightest load. Use the static timing analyzer to determine the setup time under given design conditions. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions. Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.2 ns for BUFGE #s 1, 2, 5 and 6. Input Threshold Adjustments The following table must be used to adjust input parameters and input switching characteristics. Description For TTL input add Speed Grade Symbol Device All Devices TTTLI -4 Max 0 -3 Max 0 -2 Max 0 Units For CMOS input add TCMOSI 0.3 0.2 0.2 ns 6-96 All Devices ns May 14, 1999 (Version 1.6) R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Description Clocks Delay from FCL enable (OK) active edge to IFF clock (IK) active edge Propagation Delays Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent input latch, partial delay Pad to I1, I2 via transparent input latch, full delay Pad to I1, I2 via transparent FCL and input latch, no delay Pad to I1, I2 via transparent FCL and input latch, partial delay Propagation Delays Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) FCL Enable (OK) active edge to I1, I2 (via transparent standard input latch) Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q Delay from GSR input to any Q Symbol Speed Grade Device -4 Min -3 Min -2 Min Units TOKIK All devices 3.2 2.6 2.6 ns TPID TPLI TPPLI All devices All devices XC4028EX XC4036EX XC4028EX XC4036EX All devices Max 2.2 3.8 13.3 14.5 18.2 19.4 5.3 Max 1.9 3.2 11.1 12.1 15.2 16.2 4.4 Max 1.8 3.0 10.9 11.9 14.9 15.9 4.2 ns ns ns ns ns ns ns TPPFLI XC4028EX XC4036EX 13.6 14.8 11.3 12.3 11.1 12.1 ns ns TIKRI TIKLI TOKLI All devices All devices All devices 3.0 3.2 6.2 2.5 2.7 5.2 2.4 2.6 5.0 ns ns ns TMRW TRRI TRRI All devices XC4028EXX C4036EX 13.0 22.8 24.0 11.5 19.0 21.0 11.5 19.0 21.0 ns ns ns TPDLI TPFLI 6 FCL = Fast Captur Latch, IFF = Input Flip-Flop or Latch Notes: For CMOS input levels, see the "Input Threshold Adjustments" on page 96. For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Set-up and Hold tables on page 96. May 14, 1999 (Version 1.6) 6-97 R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX IOB Input Switching Characteristic Guidelines (Continued) Description Speed Grade Device -4 Min -3 Min -2 Min Units All devices XC4028EX XC4036EX XC4028EX XC4036EX All devices 2.5 10.8 12.0 15.7 16.9 3.9 2.0 9.0 10.0 13.1 14.1 3.3 2.0 9.0 10.0 13.1 14.1 3.3 ns ns ns ns ns ns XC4028EX XC4036EX All devices XC4028EX XC4036EX 12.3 13.5 0.8 9.1 10.3 10.2 11.2 0.7 7.6 8.6 10.2 11.2 0.7 7.6 8.6 ns ns ns ns ns TECIK All devices 0.3 0.2 0.2 ns TIKPI TIKPIP TIKPID All devices All devices All devices 0 0 0 0 0 0 0 0 0 ns ns ns TIKFPI TIKFPIP TIKFPID All devices All devices All devices 0 0 0 0 0 0 0 0 0 ns ns ns TIKEC TIKECP TIKECD All devices All devices All devices 0 0 0 0 0 0 0 0 0 ns ns ns TOKPI TOKPIP All devices All devices 0 0 0 0 0 0 ns ns Symbol Setup Times Pad to Clock (IK), no delay Pad to Clock (IK), partial delay TPICK TPICKP Pad to Clock (IK), full delay TPICKD Pad to Clock (IK), via transparent Fast Capture Latch, no delay Pad to Clock (IK), via transparent Fast Capture Latch, partial delay Pad to Fast Capture Latch Enable (OK), no delay Pad to Fast Capture Latch Enable (OK), partial delay TPICKF Setup Times (TTL or CMOS Inputs) Clock Enable (EC) to Clock (IK) Hold Times Pad to Clock (IK), no delay partial delay full delay Pad to Clock (IK) via transparent Fast Capture Latch, no delay partial delay full delay Clock Enable (EC) to Clock (IK), no delay partial delay full delay Pad to Fast Capture Latch Enable (OK), no delay partial delay Notes: 6-98 TPICKFP TPOCK TPOCKP For CMOS input levels, see the "Input Threshold Adjustments" on page 96. For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Set-up and Hold tables on page 96. May 14, 1999 (Version 1.6) R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000EX IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values apply to all XC4000EX devices unless otherwise noted. Speed Grade Description Symbol -4 Min -3 Max Min -2 Max Min Max Units Propagation Delays Clock (OK) to Pad Output (O) to Pad 3-state to Pad hi-Z (slew-rate independent) 3-state to Pad active and valid Output MUX Select (OK) to Pad Fast Path Output MUX Input (EC) to Pad Slowest Path Output MUX Input (O) to Pad TOKPOF TOPF TTSHZ TTSONF TOKFPF TCEFPF TOFPF 7.4 6.2 4.9 6.2 6.7 6.2 7.3 6.2 5.2 4.1 5.2 5.6 5.1 6.0 6.0 5.0 4.1 5.0 5.4 5.0 5.9 ns ns ns ns ns ns ns Setup and Hold Times Output (O) to clock (OK) setup time Output (O) to clock (OK) hold time Clock Enable (EC) to clock (OK) setup Clock Enable (EC) to clock (OK) hold TOOK TOKO TECOK TOKEC 0.6 0 0 0 0.5 0 0 0 0.5 0 0 0 ns ns ns ns TCH TCL 3.5 3.5 3.0 3.0 3.0 3.0 ns ns TMRW TRPO TRPO 13.0 30.2 31.4 11.5 25.2 27.2 11.5 25.0 27.0 ns ns ns Clock Clock High Clock Low Global Set/Reset Minimum GSR pulse width Delay from GSR input to any Pad (XC4028EX) Delay from GSR input to any Pad (XC4036EX) Notes: Output timing is measured at TTL threshold, with 35pF external capacitive loads. For CMOS output levels, see the "Output Level and Slew Rate Adjustments" on page 95 May 14, 1999 (Version 1.6) 6-99 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays Revision Control Version Description 2/1/99 (1.5) Release included in 1999 data book, section 6 5/14/99 (1.6) Replaced Electrical Specification pages for XLA and XV families with separate updates and added URL link on placeholder page for electrical specifications/pinouts for WebLINX users. 6-100 May 14, 1999 (Version 1.6)