DEMO MANUAL DC1717A LTC4417 Prioritized PowerPathTM Controller Description Demonstration circuit DC1717A uses the LTC(R)4417 to arbitrate between three input supply rails, selecting the highest priority, valid supply to power the load. The rail's priority is defined by the input connection (V1-V3). Each rail has overvoltage and undervoltage thresholds set by external resistors. If the highest priority rail voltage falls out of the defined window (overvoltage or undervoltage), the rail with the next highest priority, which is valid, is Performance Summary enabled and powers the load. Two or more LTC4417s can be cascaded to provide switchover between more than three rails. Design files for this circuit board are available at http://www.linear.com/demo/DC1717A L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Specifications are at TA = 25C SYMBOL PARAMETER V1-V3, VOUT V1 to V3, VOUT Operating Supply Range CONDITIONS MIN VG Open (VS-VG) Clamp Voltage VOUT = 11V, G1 to G3 = Open 5.4 TYP 2.5 MAX UNITS 36 V 6.2 6.7 V VG(SOURCE) Sourcing (VS-VG) Clamp Voltage VOUT = 11V, I = -10A 5.8 6.6 7 V VG(SINK) Sinking (VS-VG) Clamp Voltage VOUT = 11V, I = 10A 4.5 5.2 6 V VG(OFF) G1 to G3 Off (VS-VG) Threshold V1 = V2 = V3 = 2.8V, VOUT = 2.6V, G1 to G3 Rising Edge 0.12 0.35 0.6 V VG(SLEW,ON) G1 to G3 Pull-Down Slew Rate VOUT = 11V, CGATE = 10nF 4 9 20 V/s VG(SLEW,OFF) G1 to G3 Pull-Up Slew Rate VOUT = 11V, CGATE = 10nF 7.5 13 22 V/s IGATE(LOW) G1 to G3 Low Pull-Down Current VOUT = 2.6V, V1 to V3 = 2.8V, (G1 to G3) = VG + 300mV 0.8 2 7 A VREV Reverse Voltage Threshold Measure (V1 to V3) - VOUT, VOUT Falling 30 120 200 mV VOUT = 11V, CGATE = 10nF 0.7 tG(SWITCHOVER) Break-Before-Make Time 2 3 s 0.2 0.55 V 5 8 13 s SHDN Rising 0.4 0.8 1.2 V SHDN, EN Pull-Up Current SHDN = EN = 0V -0.5 -2 -5 A VOV_UV(THR) OV1 to O3, UV1 to UV3 Comparator Threshold VOUT = 11V, OV1 to OV3 Rising, UV1 to UV3 Falling 0.985 1 1.015 V VOV_UV(HYS) OV1 to O3, UV1 to UV3 Comparator Hysteresis VOUT = 11V 15 30 45 mV tVALID V1 to V3 Validation Time 100 256 412 ms V1 Operating Voltage of Channel V1 9.6 12 14.4 V VVALID(OL) VALID1 to VALID3 Output Low Voltage tPVALID(OFF) VALID1 to VALID3 Delay OFF from OV/UV Fault VSHDN(THR) SHDN Threshold Voltage VSHDN_EN(HYS) SHDN, EN Threshold Hysteresis ISHDN_EN I = 1mA, (V1 to V3) = 2.5V, VOUT = 0V 100 mV V2 Operating Voltage of Channel V2 4 5 6 V V3 Operating voltage of Channel V3 6.4 8 9.6 V ILOAD Load Current AVI Auxiliary Voltage Input 24 V 2 6 A dc1717afa 1 DEMO MANUAL DC1717A Overview The LTC4417 controls three sets of external back-to-back P-channel MOSFETs to connect the proper rail to the load. Precision comparators are used to monitor each of the three input rails for both UV and OV conditions. The highest priority input supply whose voltage is within its respective OV/UV window for at least 256ms is considered valid and connected to the load. Low signals on the VALID1, VALID2, and VALID3 pins indicate validation of the V1, V2, and V3 voltages. DC1717A is designed to operate from inputs of 12V, 5V, and 8V, applied to V1, V2 and V3 respectively. The valid range of each supply is 20%, as set by OV and UV comparators and their associated resistive dividers. V1 has the highest priority, V3 has the lowest. The highest priority input that is also within its valid range is selected to power the output. V1, V2 and V3 inputs are protected against input glitches of up to 42V. Maximum load current is 2A, limited by MOSFET capability. Logic and LEDs are included to provide visual information about the operating status. These circuits are powered from a 6V to 24V auxiliary voltage input (AVI) which is regulated by an LT3060 (U4) to 5V. This auxiliary 5V rail also powers 100k pull-ups for VALID pins. AVI must be present in order for the board to operate. See the Modification section for a means of eliminating AVI. Operating Principles To eliminate back-and-forth switching during rail switchover, the LTC4417 provides a 30mV hysteresis in the OV and UV comparators, and an externally adjustable current mode hysteresis using the OV/UV resistive dividers. DC1717A's input reference hysteresis is 6%, and can be changed to 3% by moving the JP1 jumper to the 30mV position. The controller's "break-before-make" switching method prevents cross conduction between input channels and reverse current from the output capacitor into the selected input supply. Each channel's control circuit of the LTC4417 has a REV comparator, which monitors the connecting input supply and output load voltage. The REV comparator delays the connection until the output voltage droops 120mV below the input voltage. This prevents reverse current. The LTC4417 has two common control pins: EN and SHDN. Pulling the EN pin below 1V turns off all external back-toback P-channel MOSFETs. When this pin is driven above 1V, the highest priority valid channel is connected to the load. All these actions are provided without resetting the 256ms OV/UV timers. Pulling the SHDN pin below 0.8V turns off all external back-to-back P-channel MOSFETs, placing the controller 2 in a low current state and resetting the 256ms timers used to validate input rail voltages. It requires at least 256ms to validate each rail voltage after the SHDN pin signal goes high. The LTC4417 features two different driving modes for the P-channel MOSFET gates. One mode is provided by the internal soft-start circuitry, which limits output voltage slew rate to no more than 5V/ms. As the highest output voltage slew rate, usually, can impose the highest requirements for circuit components, 5V/ms should be taken into account as a worst case for component selection. The soft-start circuitry is enabled each time under the following conditions: * If the LTC4417 is first powered on, or * If SHDN is forced low, or * If VOUT falls below ~0.7V Soft-start is disabled when: * any channel turns off, including the channel that is soft starting. * 32ms validation delay time has elapsed during the softstart interval. dc1717afa DEMO MANUAL DC1717A Operating Principles The other driving mode of the P-channel MOSFETs is used in the voltage switching operation, when the higher priority rail replaces the rail losing validity. The gate driver operates with a fixed current, which is defined by the external component parameters RS and CS shown in Figure 1. 12V WALL ADAPTER V1 + M1 IRF7324 M2 CIN1 68F CS DS BAT54 CVS1 The LTC4417 circuit designer should select the value of RS and CS based on the MOSFET parameters, power rail source characteristics, acceptable output voltage droop during transient, and the value of load capacitance. VS1 G1 VOUT LTC4417 RS + VOUT CL 47F Figure 1 Design Procedure for Modification of DC1717A The valid input range for any supply is controlled by the OV and UV comparators with resistive dividers (R4-R13). See the LTC4417 data sheet for design equations to select resistors to match a particular requirement. Dual MOSFETs, Q1-Q3, may be replaced with single devices Q4-Q9 by simply removing Q1-Q3. Pads for Q4-Q9 are located on the bottom side of the board. The requirement for AVI may be eliminated by removing jumpers JP2 and JP3, and removing resistor R19. This modification leaves the LEDs unpowered and the inputs of U2 and U3 clamp the VALID pins at 0.7V, but otherwise leaves the LTC4417 operating autonomously. The following design considerations and equations demonstrate the interrelation of the main component values and transient parameters in the rail transitions, when the output voltage exceeds 0.7V. The variables CS and RS used in the design equations correspond to the following board components: The slew rate of the output voltage can be expressed as a function of CS: dVOUT dVCS VSINK - | VTHRES | = = dt dt RS * CS (1) where: * VSINK is the LTC4417 parameter rated in the data sheet as VG(SINK) = 4.5V-6V. * VTHRES is the P-channel gate threshold voltage, which is between -1.5V and -3.5V for the Si7905DN installed on the board. * RS = 249 and CS = 47nF. Given that dVOUT/dt is based on the transient time requirement, it is possible to define RS from equation 1. The output voltage slew rate, dVOUT/dt, range for the circuit with the listed parameters is between 85V/ms and 385V/ms. * C20, R23 for V1 (+12V channel) During the transition of rails, the load can be disconnected from any rail for a time: * C21, R26 for V2 (+5.0V channel) TDISCON = tG(SWITCHOVER) + tpVALID(OFF) + tGATE_THRES * C22, R28 for V3 (+8.0V channel) To have dominant influence on the transient time CS should be at least ten times larger than the P-channel MOSFET's reverse transfer capacitance (Miller). In this design, for all rails, CS (C20, C21,and C22) equals 47nF. Two first summands of the TDISCON are rated in the LTC4417 data sheet as: tG(SWITCHOVER) = (0.3 to 3)s tpVALID(OFF) = (5 to 13)s dc1717afa 3 DEMO MANUAL DC1717A Design Procedure for Modification of DC1717A The second summand, tpVALID(OFF), should be taken into account if the associated LTC4417 input does not have any bypass capacitor and the rail can be disconnected from the input instantly. The third one must be calculated as: V tGATE _ THRES = RS * CS -In 1- THRES VSINK (2) It is possible to determine the minimum capacitive load required to hold the output up during switchover as a: CLOAD(MIN) ILOAD(MAX) * TDISCON VOUT(DROOPMAX) (3) where: As shown in the equation (3), the use of external slew rate control will add additional delay to the total switchover time. Unfortunately, the actual components cannot be chosen until the load capacitance is known. This circular issue can only be resolved through an iterative process. The process starts by calculating the CLOAD(MIN), assuming that tGATE_THRES =10s. For clarity this value will be labeled CLOAD(INIT). Using the calculated CLOAD(INIT), calculate RS from the expression of the TDISCON. To ensure the newly calculated RS based on CLOAD(INIT) is sufficient, calculate CLOAD with the calculated RS. If CLOAD(INIT) (the initial calculated CLOAD) is higher than the newly calculated CLOAD then the process is completed. If the CLOAD(INIT) is lower than the newly calculated CLOAD, calculate RS using the higher value and repeat this process. * ILOAD(MAX) is the maximum load current, A * VOUT(DROOPMAX) is the maximum acceptable voltage droop, V V RS * CS -In 1- THRES = 10s V SINK Calculate RS with CL(INIT) Recalculate CL with RS Is recalculated CL lower than initial CL(INIT)? No Done. Use CL(INIT) and RS Figure 2 4 dc1717afa DEMO MANUAL DC1717A Turrets V1: 12V supply input; do not exceed 42V. V2: 5V supply input; do not exceed 42V. V3: 8V supply input; do not exceed 42V. GND: Adjacent ground connection for input supplies. VOUT: Output for up to 2A load. GND: Adjacent ground connection for load. AVI: Auxiliary Voltage Input. 6V to 24V input regulated by U4 to 5V for LEDs, logic and pull ups on various pins. GND: Adjacent ground connection for auxiliary supply. 5V: 5V regulated output provided by U4, for powering logic, LEDs and pull ups. Use this turret to verify that 5V is present. Each of the following turrets is a direct connection to the like-name LTC4417 pin: VALID1: pulled up with 100kOhm to auxiliary 5V supply. VALID2: pulled up with 100kOhm to auxiliary 5V supply. VALID3: pulled up with 100kOhm to auxiliary 5V supply. EN: pulled up by 2A internal to the LTC4417. Optional R33 may be added as a pull-up to the auxiliary 5V power supply. SHDN: pulled up by 2A internal to the LTC4417. Optional R36 may be added as a pull-up to the auxiliary 5V power supply. CAS: used to cascade a second DC1717A. Connect the CAS turret of the high priority DC1717A to the EN turret of the lower priority DC1717A. Grounds must be connected in common. Jumpers JP1, HYS: Add 30mV fixed hysteresis to the OV and UV comparators, or 3% referred to actual supply input. In the RHYS position input-referred hysteresis is set to 6.4%, as controlled by R11. Default stuffing position is for 30mV. JP2, EN: Directly controls EN pin. Default stuffing position is ON, pulled up by internal 2A current source. LEDs No more than one of D8, D9 and D10 will be illuminated at any given moment: D11, D16 and D17 indicate the presence of a valid input on any of the three supplies: D8: indicates power is being taken from V1. D17: V1 is 12V20%. D9: indicates power is being taken from V2. D11: V2 is 5V20%. D10: indicates power is being taken from V3. D16: V3 is 8V20%. dc1717afa 5 DEMO MANUAL DC1717A Quick Start Procedure Refer to the Figure 3 for proper measurement equipment setup and follow the procedure below: Initially, the LTC4417 should be disabled by: * placing the jumper JP2 (EN) header in the OFF position, and Connect 6 load resistor (30W) to the DC1717A output turret or banana jack (VOUT). Do not use an electronic load in constant current mode. Turn on three power supplies. No additional LEDs should light. * placing the jumper JP3 (SHDN) header in the OFF position Change the jumper JP3 (SHDN) header position from OFF to ON. Three LEDs (VALID1, VALID2, and VALID3) validating the input rail voltages should light. Connecting the auxiliary power source (6V to 24V) to the DC1717A (AVI and GND turrets) lights the green LED (LDO-D12) indicating the presence of auxiliary +5V supply for powering logic. Placing the jumper JP2 (EN) in the ON position turns on the LTC4417 powering the load with 12V (2.0A). In an initial power up the LTC4417 uses a fixed slew rate for the output voltage, which should be not larger than 5V/ms. With power off, connect three power supplies with output voltages of 12V, 5V, and 8V to corresponding DC1717A turrets or banana jacks V1(+12V), V2(+5V), V3(+8V), and GND. The prioritizing function is demonstrated by simply turning off one or two of the V1, V2 and V3 supplies. The output will be powered from the remaining supply of the highest priority. V1, V2 and V3 may be adjusted up and down beyond 20% to invalidate a given input. 12V POWER SUPPLY 5V POWER SUPPLY 6 RESISTIVE LOAD 8V POWER SUPPLY Figure 3 6 dc1717afa DEMO MANUAL DC1717A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER 1 0 C1, C3, C5, C8 CAP., 1206 OPT 2 0 C2, C4, C6, C9 CAP., 2220 OPT 3 1 C7 CAP., ALUM., 47F 50V 20% SMT SUN ELECT., 50CE47BS 4 5 C10, C11, C12, C13, C15 CAP., X5R, 1F 50V, 10%, 0603 MURATA, GRM188R61H105KAALD 5 1 C14 CAP., X5R 10F 10V 20% 0805 TAIYO YUDEN LMK212ABJ106MG -T 6 1 C16 CAP., NPO 10nF 50V 5% 0805 NIC, NMC0805NPO103J50TRPF 7 3 C17, C18, C19 CAP., X5R 0.1F 50V 10% 0805 TAIYO YUDEN UMK212BJ104KG-T 8 3 C20, C21, C22 CAP., X7R 0.047F 50V, 10%, 0805 MURATA, GRM21BR71H473KA01L 9 3 D1, D2, D3 DIODE, TVS BI-DIRECTIONAL, 26V, 600W DIODES/ZETEX SMBJ26CA-13-F 10 0 D7 ZENER DIODE, 5.1V SOD-123 OPT 11 8 D8-D12, D16, D17, D18 LED, GREEN, LED-ROHM-SML-01 ROHM, SML-012P8TT86 12 3 D13, D14, D15 DIODE, SCHOTTKY, SOD323 VISHAY SEMI., BAT42WS-E3-08 13 9 E1-E4, E6, E13-E16 TURRET, 0.094" MILL-MAX 2501-2-00-80-00-00-07-0 14 6 E7, E8, E9, E10, E11, E12 TURRET, 0.063" MILL-MAX 2308-2-00-80-00-00-07-0 15 3 JP1, JP2, JP3 HEADERS, SGL. ROW 3 PINS 2mm CTRS. SAMTEC TMM-103-02-L-S 16 3 SHUNTS ON JP1-JP3 (1&2) SHUNT, 2mm CTRS. SAMTEC 2SN-BK-G 17 6 J1, J2, J3, J4, J5, J6 JACK, BANANA KEYSTONE 575-4 18 3 Q1, Q2, Q3 DUAL P-CHAN., 40V POWERPAK1212-8-DUAL VISHAY Si7905DN-T1-GE3 19 0 Q4, Q5, Q6, Q7, Q8, Q9 MOSFET P-CHAN., 40V, FDD4685, DPAK OPT 20 1 Q10 XTOR N-CHAN., SOT23 DIODE INC., MMBTA42-7-F 21 1 Q11 XTOR N-CHAN., SOT23 DIODE INC., MMBT3904-7-F 22 1 R4 RES., CHIP 1.69M 0.125W 1% 0805 VISHAY, CRCW08051M69FKEA 23 3 R5, R8, R12 RES., CHIP 69.8k 0.125W 1% 0805 VISHAY, CRCW080569K8FKEA 24 3 R6, R9, R13 RES., CHIP 130k 0.125W 1% 0805 NIC, NRC10F1303TRF 25 1 R7 RES., CHIP 590k 0.125W 1% 0805 VISHAY, CRCW0805590KFKEA 26 1 R10 RES., CHIP 1.05M 0.125W 1% 0805 VISHAY, CRCW08051M05FKEA 27 1 R11 RES., CHIP 127k 0.1W 1% 0603 VISHAY, CRCW0603127KFKED 28 7 R14-R16, R20-R22, R29 RES., CHIP 1k 0.1W 5% 0603 VISHAY, CRCW06031K00JNEA 29 0 R17 RES., CHIP 845k 0.1W 1% 0603 OPT 30 0 R18 RES., CHIP 115k 0.06W 1% 0603 OPT 31 1 R19 RES., CHIP 30.9k 0.1W 1% 0603 VISHAY, CRCW060330K9FKEA 32 3 R23, R26, R28 RES., CHIP 249 0.1W 1% 0603 VISHAY, CRCW060249RFKEA 33 5 R30, R31, R32, R33, R36 RES., CHIP 100k 0.1W 5% 0603 NIC, NRC06J104TRF 34 1 R34 RES., CHIP 68k 0.25W 5% 1206 NIC, NRC12J683TRF 35 1 R35 RES., CHIP 240 0.25W 1% 1206 VISHAY, CRCW1206240RFKEA 36 1 U1 I.C., POWERPATH CONTROLLER, QFN24UF-4x4 LINEAR TECH CORP. LTC4417CUF 37 3 U2,U3,U5 I.C., TRIPPLE 3-INPUT NOR GATE TSSOP14 NXP/PHILIPS SEMI. 74HC27PW 38 1 U4 I.C., LOW DROPOUT REG. TSOT23-8 LINEAR TECH CORP. LT3060ETS8-5 39 4 MH1-MH4 STANDOFF, NYLON, 0.50, 1/2" KEYSTONE, 8833 (SNAP ON) dc1717afa 7 A B C D GND V3 (+8V) V2 (+5V) V1 (+12V) E4 J6 E3 J5 E2 J2 E1 J1 V3 V2 V1 5 C17 0.1uF 50V 0805 C19 0.1uF 50V 0805 C18 0.1uF 50V 0805 OV1 R8 69.8K 0805 OV2 R12 69.8K 0805 OV3 R13 130K 0805 R10 1.05M 0805 UV3 R9 130K 0805 R7 590K 0805 UV2 V3 R5 69.8K 0805 R6 130K 0805 R4 1.69M 0805 V2 V1 C8 OPT 1206 C3 OPT 1206 C1 OPT 1206 UV1 D3 SMBJ26CA D2 SMBJ26CA D1 SMBJ26CA C9 OPT 2220 C4 OPT 2220 C2 OPT 2220 OV3 UV3 V3 OV2 UV2 V2 OV1 UV1 V1 VS1 G1 18 17 C11 1uF 50V VS2 14 VS3 GND 10 EP 25 U1 LTC4417 VS2 G2 16 15 C12 1uF 50V VS3 G3 13 R26 249 VOUT CAS HYS SHDN EN VALID3 VALID2 VALID1 4 2 2 1 2 1 3 1 11 24 23 22 9 8 7 R28 249 12 FG3 8 7 FG2 Q3 Si7905DN Q2 Si7905DN 8 7 R23 249 8 7 FG1 Q1 Si7905DN 4 3 4 3 4 1. ALL RESISTORS ARE IN OHMS, 0603. ALL CAPACITORS ARE IN MICROFARADS, 0603. 2. INSTALL SHUNTS ON JUMPERS AS SHOWN. NOTES: UNLESS OTHERWISE SPECIFIED 6 5 19 4 3 20 2 1 21 C10 1uF 50V VS1 4 1 2 1 2 1 G1 C21 0.047uF 50V 0805 5V 5V JP1 HYS 30mV RHYS R32 100k 5V CUSTOMER NOTICE 1 2 3 5V FG3 VS3 FG2 VS2 FG1 VS1 R33 100k R34 68k 1206 2 1 2 3 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 1 R35 240 1206 OFF ON 5V 2 SCALE = NONE VLAD O. KIM T. JP3 C5 OPT 1206 C6 + OPT 2220 VOUT 1 E12 E11 E10 E9 E8 E7 J4 E6 E16 J3 DATE GND VOUT 2A MAX 07-23-15 CAS SHDN EN VALID3 VALID2 VALID1 EN /VALID3 /VALID2 /VALID1 VLAD O. APPROVED DATE: N/A SIZE IC NO. Thursday, July 23, 2015 1 SHEET 1 OF 2 3 REV. PRIORITIZED POWERPATH CONTROLLER LTC4417CUF DEMO CIRCUIT 1717A 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only C7 47uF 50V SANYO 50CE47BS PRODUCTION DESCRIPTION REVISION HISTORY TECHNOLOGY OFF SHDN ON 3 __ 1 2 3 REV ECO TITLE: SCHEMATIC R36 100k VOUT D18 GRN Q10 MMBTA42 LED DRIVER 1 APPROVALS JP2 EN Q11 MMBT3904 LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED APP ENG. CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. R11 127k R30 100k G3 R31 100k C22 0.047uF 50V 0805 D15 BAT42WS-V 6 5 G2 D14 BAT42WS-V 6 5 3 C20 0.047uF 50V 0805 D13 BAT42WS-V 6 5 3 3 2 3 12 2 8 2 5 A B C D DEMO MANUAL DC1717A Schematic Diagram dc1717afa A B C R19 30.9K GND E15 5 C13 1uF 50V 1 5 7 9 10 11 3 4 5 1 2 13 7 9 10 11 3 4 5 SHDN IN U4 LT3060ETS8-5 D7 MMSZ5231BT1G 5.1V OPT AUXILIARY VOLTAGE INPUT 6V - 24V E14 /VALID2 /VALID1 EN /VALID3 1 1 2 13 VDD GND ADJ OUT 7 6 VDD U3 74HC27PW GND REF/BYP 2 U2 74HC27PW 14 8 6 12 14 8 6 12 R18 115k OPT R17 845k OPT 5V 5V 4 4 C16 10nF 50V 0805 V3 GRN D10 V2 GRN D9 V1 GRN C14 10uF 10V 0805 1 1 1 D8 C15 1uF 50V 2 2 2 LDO D12 GRN R29 1k R16 1k R15 1k R14 1k 5V VOUT POWER SOURCE 1 D 2 3 GND 4 GND GND 8 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 2 3 2 5V 2 SCALE = NONE VLAD O. KIM T. APPROVALS 14 7 VDD 8 9 10 11 GND 6 12 Q8 FDD4685 Q6 FDD4685 Q4 FDD4685 3 4 5 1 2 13 U5 74HC27PW V3 1 V2 1 V1 1 1 1 1 OPTIONAL CIRCUIT THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. CUSTOMER NOTICE 5V /VALID3 /VALID2 /VALID1 FG3 VS3 FG2 VS2 FG1 VS1 3 2 LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED APP ENG. CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. E13 3 3 2 Q9 FDD4685 VOUT Q5 FDD4685 VOUT Q7 FDD4685 VOUT 3 2 2 VALID3 GRN D16 VALID2 GRN D11 VALID1 GRN D17 R21 1k R20 1k R22 1k DATE: N/A IC NO. Thursday, July 23, 2015 1 SHEET 2 OF 2 REV. PRIORITIZED POWERPATH CONTROLLER SIZE 3 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only 1 LTC4417CUF DEMO CIRCUIT 1717A TECHNOLOGY 2 2 2 TITLE: SCHEMATIC 1 1 1 VALID STATUS 3 3 2 3 2 5 A B C D DEMO MANUAL DC1717A Schematic Diagram dc1717afa 9 DEMO MANUAL DC1717A DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright (c) 2004, Linear Technology Corporation 10 Linear Technology Corporation dc1717afa LT 0915 REV A * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2013