IRF9630, RF1S9630SM Data Sheet 6.5A, 200V, 0.800 Ohm, P-Channel Power MOSFETs These are P-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers and drivers for other high-power switching devices. The high input impedance allows these types to be operated directly from integrated circuits. Formerly developmental type TA17512. Ordering Information PART NUMBER PACKAGE January 2002 Features * 6.5A, 200V * rDS(ON) = 0.800 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol BRAND IRF9630 TO-220AB IRF9630 RF1S9630SM TO-263AB RF1S9630 D G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in the tape and reel, i.e., RF1S9630SM9A. S Packaging JEDEC TO-220AB JEDEC TO-263AB SOURCE DRAIN GATE DRAIN (FLANGE) (c)2002 Fairchild Semiconductor Corporation DRAIN (FLANGE) GATE SOURCE IRF9630, RF1S9630SM Rev. B IRF9630, RF1S9630SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF9630, RF1S9630SM -200 -200 -6.5 -4 -26 20 75 0.6 500 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS -200 - - V VGS = VDS, ID = -250A -2 - -4 V VDS = Rated BVDSS, VGS = 0V - - -25 A A Drain to Source Breakdown Voltage BVDSS ID = -250A, VGS = 0V(Figure 10) Gate Threshold Voltage VGS(TH) Zero Gate Voltage Drain Current IDSS VDS = 0.8 x Rated BVDSS, VGS = 0V, TC= 125oC On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge rDS(ON) gfs td(ON) tr td(off) VGS = 20V ID = -3.5A, VGS = -10V (Figures 8, 9) VDS ID(ON) x rDS(ON)MAX, ID = -3.5A (Figure 12) VDD = -100V, ID -6.5A, RG = 50 RL = 15.4 (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature tf Qg(TOT) Qgs Gate to Drain ("Miller") Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Internal Drain Inductance VDS > ID(ON) x rDS(ON)MAX, VGS = -10V LD VGS = -10V, ID = -6.5A, VDS = 0.8 x Rated BVDSS Ig(REF) = -1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature LS Thermal Resistance Junction to Case RJC Thermal Resistance Junction to Ambient RJA (c)2002 Fairchild Semiconductor Corporation - -250 - - A - - 100 nA - 0.500 0.800 2.2 3.5 - S - 30 50 ns - 50 100 ns - 50 100 ns - 40 80 ns - 31 45 nC - 18 - nC - 13 - nC VDS = -25V, VGS = 0V, f = 1MHz (Figure 11) - 550 - pF - 170 - pF - 50 - pF Measured From the Contact Screw On Tab To the Center of Die - 3.5 - nH - 4.5 - nH - 7.5 - nH - - 1.67 oC/W - - 80 oC/W Measured From the Drain Lead, 6mm (0.25in) From Package to the Center of Die Internal Source Inductance -6.5 Measured From the Source Lead, 6mm (0.25in) From Package to Source Bonding Pad Typical Socket Mount Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S IRF9630, RF1S9630SM Rev. B IRF9630, RF1S9630SM Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode ISDM MIN TYP MAX - - -6.5 UNITS A - - -26 A - - -1.5 V - 400 - ns - 2.6 - C D G S Source to Drain Diode Voltage (Note 2) VSD TJ trr TJ QRR TJ Reverse Recovery Time Reverse Recovery Charge = 25oC, ISD = -6.5A, VGS = 0V (Figure 13) = 150oC, ISD = -6.5A, dISD/dt = 100A/s = 150oC, ISD = -6.5A, dISD/dt = 100A/s NOTES: 2. Pulse Test: Pulse width 300s, duty cycle 2%. 3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 17.75mH, RG = 25, peak IAS = 6.5A. (Figures 15, 16). Typical Performance Curves Unless Otherwise Specified -10 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 0 -8 -6 -4 -2 0 0 50 100 150 0 50 TC, CASE TEMPERATURE (oC) 75 125 100 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE THERMAL IMPEDENCE ZqJC, NORMALIZED 1 0.5 0.2 0.1 0.1 PDM 0.05 0.02 0.01 t1 t2 t2 SINGLE PULSE 0.01 10-5 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-4 10-3 10-2 10-1 t 1, RECTANGULAR PULSE DURATION (s) 1 10 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE (c)2002 Fairchild Semiconductor Corporation IRF9630, RF1S9630SM Rev. B IRF9630, RF1S9630SM Typical Performance Curves -100 Unless Otherwise Specified (Continued) -15 ID, DRAIN CURRENT (A) TJ = MAX RATED SINGLE PULSE -10 10s 100s 1ms -1 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -0.1 -1 100ms DC -10 -100 VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) TC = 25oC VGS = -10V VGS = -8V -12 -9 VGS = -6V -6 VGS = -5V -3 VGS = -4V 0 -1000 -10 VGS = -9V VGS = -8V VGS = -7V VGS = -6V -4 VGS = -5V VGS = -4V 0 -2 -4 -6 -8 ID(ON), ON-STATE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) -15 -8 0 -55oC -9 25oC -125oC -6 -3 0 -10 -2 -4 -6 -8 VGS, GATE TO SOURCE VOLTAGE (V) 0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE () 2.5 1.6 1.2 VGS = -10V 0.8 VGS = - 20V 0 -15 -10 ID, DRAIN CURRENT (A) -20 -10 FIGURE 7. TRANSFER CHARACTERISTICS 2.0 -5 -50 -12 FIGURE 6. SATURATION CHARACTERISTICS 0 -40 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS, DRAIN TO SOURCE VOLTAGE (V) 0.4 -30 FIGURE 5. OUTPUT CHARACTERISTICS VGS = -10V -12 -20 VDS, DRAIN TO SOURCE VOLTAGE (V) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX -16 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -7V FIGURE 4. FORWARD BIAS SAFE OPERATING AREA -20 -9V -25 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 0.5 0 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT (c)2002 Fairchild Semiconductor Corporation FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF9630, RF1S9630SM Rev. B IRF9630, RF1S9630SM Typical Performance Curves Unless Otherwise Specified (Continued) 2000 1.15 VGS = 0V, f = 1MHz CISS = CGS + CGD C = CGD 1600 RSS COSS CDS + CGD C, CAPACITANCE (pF) NORMALIZED DRAIN-TO-SOURCE BREAKDOWN VOLTAGE 1.25 1.05 0.95 1200 CISS 800 COSS 400 0.85 CRSS 0.75 -40 0 40 80 120 0 160 10 0 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 30 40 50 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE -100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 5.6 ISD, DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) 7.0 20 VDS, DRAIN TO SOURCE VOLTAGE (V) TJ = -55oC TJ = 25oC 4.2 TJ = 125oC 2.8 1.4 TJ = 150oC -10 TJ = 25oC -1.0 -0.1 0 0 -3 -6 -9 -15 -12 -0.4 -0.6 ID , DRAIN CURRENT (A) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT -1.8 FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 0 VGS, GATE TO SOURCE (V) -1.0 -1.2 -1.6 -0.8 -1.4 VSD, SOURCE TO DRAIN VOLTAGE (V) I D = -8A -5 VDS = -160V - 10 VDS = -100V VDS = -40V - 15 0 8 16 24 42 40 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE (c)2002 Fairchild Semiconductor Corporation IRF9630, RF1S9630SM Rev. B IRF9630, RF1S9630SM Test Circuits and Waveforms VDS tAV L 0 VARY tP TO OBTAIN REQUIRED PEAK IAS - RG VDD + 0V VDD DUT tP IAS IAS VDS tP 0.01 -VGS BVDSS FIGURE 15. UNCLAMPED INDUCTIVE ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(OFF) td(ON) tr 0 - DUT VGS VDS VDD VGS 0 + 10% 10% RL RG tf 90% 90% 10% 50% 50% PULSE WIDTH 90% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS FIGURE 17. SWITCHING TIME TEST CIRCUIT -VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 0 VDS DUT 0.2F 50k 0.3F + Qgs Qg(TOT) DUT G VGS Qgd D VDD 0 S IG(REF) IG CURRENT SAMPLING RESISTOR +VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation 0 IG(REF) FIGURE 20. GATE CHARGE WAVEFORMS IRF9630, RF1S9630SM Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET VCXTM STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4