©2002 Fairchild Semiconductor Corporation IRF9630, RF1S9630SM Rev. B
IRF9630, RF1S9630SM
6.5A, 200V, 0.800 Ohm, P-Channel Power
MOSFETs
These are P-Channel enhancement mode silicon gate power
field effect transistors. They are advanced power MOSFETs
designed, tested, and guaranteed to withstand a specified
level of energy in the breakdown avalanche mode of
operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
converters, motor drivers, relay drivers and drivers for other
high-power switching devices. The high input impedance
allows these types to be operated directly from integrated
circuits.
Formerly developmental type TA17512.
Features
• 6.5A, 200V
•r
DS(ON)
= 0.800
Ω
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-220AB JEDEC TO-263AB
Ordering Information
PART NUMBER PACKAGE BRAND
IRF9630 TO-220AB IRF9630
RF1S9630SM TO-263AB RF1S9630
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in the tape and reel, i.e., RF1S9630SM9A.
G
D
S
GATE
DRAIN (FLANGE)
SOURCE
DRAIN
DRAIN
(FLANGE)
GATE
SOURCE
Data Sheet January 2002
©2002 Fairchild Semiconductor Corporation IRF9630, RF1S9630SM Rev. B
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
IRF9630,
RF1S9630SM UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
-200 V
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
-200 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
-6.5
-4
A
A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
-26 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
75 W
Dissipation Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W/
o
C
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
500 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
J
, T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= -250
µ
A, V
GS
= 0V(Figure 10) -200 - - V
Gate Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= -250
µ
A -2 - -4 V
Zero Gate Voltage Drain Current I
DSS
V
DS
= Rated BV
DSS
, V
GS
= 0V - - -25
µ
A
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
C
= 125
o
C - - -250
µ
A
On-State Drain Current (Note 2) I
D(ON)
V
DS
> I
D(ON)
x r
DS(ON)MAX
, V
GS
= -10V -6.5 - - A
Gate to Source Leakage Current I
GSS
V
GS
=
±
20V - - °±
±
100 nA
On Resistance (Note 2) r
DS(ON)
I
D
= -3.5A, V
GS
= -10V (Figures 8, 9) - 0.500 0.800
Ω
Forward Transconductance (Note 2) gfs V
DS
≥
I
D(ON)
x r
DS(ON)MAX
, I
D
= -3.5A
(Figure 12)
2.2 3.5 - S
Turn-On Delay Time t
d(ON)
V
DD
= -100V, I
D
≈
-6.5A, R
G
= 50
Ω
R
L
= 15.4
Ω
(Figures 17, 18)
MOSFET Switching Times are Essentially
Independent of Operating Temperature
-3050 ns
Rise Time t
r
- 50 100 ns
Turn-Off Delay Time t
d(off)
- 50 100 ns
Fall Time t
f
-4080 ns
Total Gate Charge
(Gate to Source + Gate to Drain)
Q
g(TOT)
V
GS
= -10V, I
D
= -6.5A, V
DS
= 0.8 x Rated BV
DSS
I
g(REF)
= -1.5mA (Figures 14, 19, 20)
Gate Charge is Essentially Independent of
Operating Temperature
-3145nC
Gate to Source Charge Q
gs
-18 - nC
Gate to Drain (“Miller”) Charge Q
gd
-13 - nC
Input Capacitance C
ISS
V
DS
= -25V, V
GS
= 0V, f = 1MHz
(Figure 11)
- 550 - pF
Output Capacitance C
OSS
- 170 - pF
Reverse Transfer Capacitance C
RSS
-50 - pF
Internal Drain Inductance L
D
Measured From the
Contact Screw On Tab To
the Center of Die
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
- 3.5 - nH
Measured From the Drain
Lead, 6mm (0.25in) From
Package to the Center of
Die
- 4.5 - nH
Internal Source Inductance L
S
Measured From the Source
Lead, 6mm (0.25in) From
Package to Source Bond-
ing Pad
- 7.5 - nH
Thermal Resistance Junction to Case R
θ
JC
- - 1.67
o
C/W
Thermal Resistance Junction to Ambient R
θ
JA
Typical Socket Mount - - 80
o
C/W
LS
LD
G
D
S
IRF9630, RF1S9630SM
©2002 Fairchild Semiconductor Corporation IRF9630, RF1S9630SM Rev. B
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current I
SD
Modified MOSFET Symbol
Showing the Integral Re-
verse P-N Junction Diode
- - -6.5 A
Pulse Source to Drain Current
(Note 3)
I
SDM
- - -26 A
Source to Drain Diode Voltage (Note 2) V
SD
T
J
= 25
o
C, I
SD
= -6.5A, V
GS
= 0V (Figure 13) - - -1.5 V
Reverse Recovery Time t
rr
T
J
= 150
o
C, I
SD
= -6.5A, dI
SD
/dt = 100A/
µ
s - 400 - ns
Reverse Recovery Charge Q
RR
T
J
= 150
o
C, I
SD
= -6.5A, dI
SD
/dt = 100A/
µ
s - 2.6 -
µ
C
NOTES:
2. Pulse Test: Pulse width
≤
300
µ
s, duty cycle
≤
2%.
3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. V
DD
= 50V, starting T
J
= 25
o
C, L = 17.75mH, R
G
= 25Ω, peak IAS = 6.5A. (Figures 15, 16).
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
G
D
S
0 50 100 150
0
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0.2
0.4
0.6
0.8
1.0
1.2
-2
0
050 100
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
-10
150
-8
75 125
-4
-6
t1, RECTANGULAR PULSE DURATION (s)
ZqJC, NORMALIZED
THERMAL IMPEDENCE
10-3 10-2
1
10-5 10-4
0.01
0.1
10
10-1 1
SINGLE PULSE t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1
0.1
0.02
0.2
0.5
0.01
0.05
t2
IRF9630, RF1S9630SM
©2002 Fairchild Semiconductor Corporation IRF9630, RF1S9630SM Rev. B
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
-100
-1
100µs
10µs
DC
1ms
10ms
100ms
-10-1
-0.1 -1000
-10
-100
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
TC = 25oC
SINGLE PULSE
TJ = MAX RATED
ID, DRAIN CURRENT (A)
0 -10 -20 -30 -40
-3
-6
-9
-12
-15
-50
-9V
VGS = -7V
VGS = -6V
VGS = -5V
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = -4V
VGS = -10V
VGS = -8V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
-4
0-2 -4 -6 -10
-8
-12
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
-16
-8
-20
VGS = -6V
VGS = -5V
VGS = -4V
VGS = -7V
VGS = -9V
VGS = -8V
VGS = -10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0-4 -6 -8 -10-2
0
-9
-12
ID(ON), ON-STATE DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
-15
-6
-3
-125oC
25oC
-55oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
1.6
-5 -10 -15 -20
ID, DRAIN CURRENT (A)
-25
2.0
0
0.4
0.8
1.2
VGS = -10V
VGS = - 20V
rDS(ON), DRAIN TO SOURCE ON
RESISTANCE (Ω)
2.5
1.5
1.0
0.5
0
-40 0 40
TJ, JUNCTION TEMPERATURE (oC)
120 160
2.0
80
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
IRF9630, RF1S9630SM
©2002 Fairchild Semiconductor Corporation IRF9630, RF1S9630SM Rev. B
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves Unless Otherwise Specified (Continued)
1.25
0.95
0.85
0.75
-40 0 40 80
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN-TO-SOURCE
BREAKDOWN VOLTAGE
120 160
1.05
1.15
2000
400
0020 50
C, CAPACITANCE (pF)
1200
VDS, DRAIN TO SOURCE VOLTAGE (V)
1600
800
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
CISS
10 30 40
COSS
CRSS
VGS = 0V, f = 1MHz
ID, DRAIN CURRENT (A)
gfs, TRANSCONDUCTANCE (S)
0 -3 -6 -9 -12
1.4
2.8
4.2
5.6
7.0
-15
TJ = 125oC
TJ = 25oC
TJ = -55oC
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
-0.4 -1.0 -1.2 -1.6 -1.8-0.6
-0.1
-1.0
-10
ISD, DRAIN CURRENT (A)
VSD, SOURCE TO DRAIN VOLTAGE (V)
-100
-0.8 -1.4
TJ = 25oC
TJ = 150oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
Qg(TOT), TOTAL GATE CHARGE (nC)
VGS, GATE TO SOURCE (V)
0 8 16 24 40
- 5
0
VDS = -160V
- 10
- 15
42
VDS = -100V VDS = -40V
ID = -8A
IRF9630, RF1S9630SM
©2002 Fairchild Semiconductor Corporation IRF9630, RF1S9630SM Rev. B
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED INDUCTIVE ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
tP
-VGS 0.01Ω
L
IAS
+
-
VDS
VDD
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
RG
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-
VDD
td(ON)
tr
90%
10%
VDS 90%
tf
td(OFF)
tOFF
90%
50%
50%
10%
PULSE WIDTH
VGS
tON
10%
0
0
0.3µF
12V
BATTERY 50kΩ
+VDS
S
DUT
D
G
IG(REF)
0
(ISOLATED
-VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
DUT
+
-
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
0
IG(REF)
IRF9630, RF1S9630SM
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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SILENT SWITCHER
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FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
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MicroPak™
MICROWIRE™
Rev. H4
ACEx™
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STAR*POWER is used under license
VCX™