SEMICONDUCTOR
3-115
November 1996
CA3240, CA3240A
Dual, 4.5MHz, BiMOS Operational Amplifier
with MOSFET Input/Bipolar Output
Features
Dual Version of CA3140
Internally Compensated
MOSFET Input Stage
- Very High Input Impedance (ZIN) 1.5T (Typ)
- Very Low Input Current (II) 10pA Typ. at ±15V
- Wide Common-Mode Input Voltage Range (VICR):
Can Be Swung 0.5V Below Negative Supply Voltage
Rail
Directly Replaces Industry Type 741 in Most
Applications
Applications
Ground Referenced Single Amplifiers in Automobile
and P ortable Instrumentation
Sample and Hold Amplifiers
Long Duration Timers/Multivibrators (Microseconds-
Minutes-Hours)
Photocurrent Instrumentation
Description
The CA3240A and CA3240 are dual versions of the popular
CA3140 series integrated circuit operational amplifiers. They
combine the advantages of MOS and bipolar transistors on the
same monolithic chip. The gate-protected MOSFET (PMOS)
input transistors provide high input impedance and a wide
common-mode input voltage range (typically to 0.5V below the
negative supply rail). The bipolar output transistors allow a wide
output voltage swing and provide a high output current capability.
The CA3240A and CA3240 are compatible with the industry
standard 1458 operational amplifiers in similar pac kages.The off-
set null f eature is a v ailab le only when these types are supplied in
the 14 lead PDIP package (E1 suffix).
Pinouts
CA3240, CA3240A, (PDIP)
TOP VIEW
CA3240, CA3240A, (PDIP)
TOP VIEW
Functional Diagram
Intrusion Alarm System Active Filters
Comparators Function Generators
Instrumentation Amplifiers Power Supplies
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
CA3240AE -40 to 85 8 Ld PDIP E8.3
CA3240AE1 -40 to 85 14 Ld PDIP E14.3
CA3240E -40 to 85 8 Ld PDIP E8.3
CA3240E1 -40 to 85 14 Ld PDIP E14.3
OUTPUT (A)
INV.
INPUT (A)
NON-INV.
1
2
3
4
8
7
6
5
V+
OUTPUT
INV.
NON-INV.
INPUT (A)
V-
INPUT (B)
INPUT (B)
INV.
NON-INV.
OFFSET
V-
OFFSET
NON - INV.
INV.
OFFSET
V+
OUTPUT (A)
NC
OUTPUT (B)
V+
OFFSET
1
2
3
4
5
6
7
14
13
12
11
10
9
8
INPUT (A)
INPUT (A)
NULL (A)
NULL (B)
INPUT (B)
INPUT (B)
NULL (A)
NULL (B)
Pins 9 and 13 internally connected through approximately 3.
A 10,000
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
A 1
2mA 4mA
2mA1.6mA 2µA200µA200µA
IN- OUT-
OFFSET NULL
C1
12pF
V+
V-
+
-
NOTE: Only available with 14 lead DIP (E1 Suffix).
A 10 PUT
PUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996 File Number 1050.3
3-116
Absolute Maximum Ratings Thermal Information
Supply Voltage (Between V+ and V-) . . . . . . . . . . . . . . . . . . . . . 36V
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mA
Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Voltage Range . . . . . . . . . . . . . . . . . . . . . 4V to 36V or ±2V to ±18V
Thermal Resistance (Typical, Note 2) θJA (oC/W)
8 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . . 100
14 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . 100
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Short circuit may be applied to ground or to either supply. Temperatures and/or supply voltages must be limited to keep dissipation within
maximum rating.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications For Equipment Design, VSUPPLY =±15V, TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL
CA3240 CA3240A
UNITSMIN TYP MAX MIN TYP MAX
Input Offset Voltage VIO - 5 15 - 2 5 mV
Input Offset Current IIO - 0.5 30 - 0.5 20 pA
Input Current II- 10 50 - 10 40 pA
Large-Signal Voltage Gain
(See Figures 13, 28) (Note 3) AOL 20 100 - 20 100 - kV/V
86 100 - 86 100 - dB
Common Mode Rejection
Ratio (See Figure 18) CMRR - 32 320 - 32 320 µV/V
70 90 - 70 90 - dB
Common Mode Input Voltage
Range (See Figure 25) VICR -15 -15.5 to
+12.5 11 -15 -15.5 to
+12.5 12 V
Power Supply Rejection Ratio
(See Figure 20) PSRR - 100 150 - 100 150 µV/V
(VIO/V±) 76 80 - 76 80 - dB
Maximum Output Voltage (Note 4)
(See Figures 24, 25) VOM+ 12 13 - 12 13 - V
VOM- -14 -14.4 - -14 -14.4 - V
Maximum Output Voltage (Note 5) VOM- 0.4 0.13 - 0.4 0.13 - V
Total Supply Current
(See Figure 16) For Both Amps I+ - 8 12 - 8 12 mA
Total Device Dissipation PD- 240 360 - 240 360 mW
NOTES:
3. At VO = 26VP-P, +12V, -14V and RL = 2k.
4. At RL = 2k.
5. At V+ = 5V, V- = GND, ISINK = 200µA.
Electrical Specifications For Equipment Design, VSUPPLY =±15V, TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
TYPICAL VALUES
UNITSCA3240A CA3240
Input Offset Voltage Adjustment Resistor
(E1 Package Only) Typical Value of Resistor Between Terminals 4 and
3(5) or Between 4 and 14(8) to Adjust Maximum VIO 18 4.7 k
Input Resistance RI1.5 1.5 T
Input Capacitance CI44pF
Output Resistance RO60 60
Equivalent Wideband Input Noise Voltage
(See Figure 2) eNBW = 140kHz, RS = 1M48 48 µV
CA3240, CA3240A
3-117
Equivalent Input Noise Voltage
(See Figure 19) eNf = 1kHz, RS = 10040 40 nV/Hz
f = 10kHz, RS = 10012 12 nV/Hz
Short-Circuit Current to Opposite Supply IOM+ Source 40 40 mA
IOM- Sink 11 11 mA
Gain Bandwidth Product (See Figures 14, 28) fT4.5 4.5 MHz
Slew Rate (See Figure 15) SR 9 9 V/µs
Transient Response (See Figure 1) trRL = 2k, CL = 100pF Rise Time 0.08 0.08 µs
OS RL = 2k, CL = 100pF Overshoot 10 10 %
Settling Time at 10 V P-P (See Figure 26) tSAV = +1, RL = 2k, CL = 100pF,
Voltage Follower To 1mV 4.5 4.5 µs
To 10mV 1.4 1.4 µs
Crosstalk (See Figure 23) f = 1kHz 120 120 dB
Electrical Specifications For Equipment Design, VSUPPLY =±15V, TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS
TYPICAL VALUES
UNITSCA3240A CA3240
Electrical Specifications For Equipment Design, at VSUPPLY =±15V, TA = -40 to 85 oC, Unless Otherwise Specified
PARAMETER SYMBOL
TYPICAL VALUES
UNITSCA3240A CA3240
Input Offset Voltage |VIO| 3 10 mV
Input Offset Current (Note 8) |IIO|32 32pA
Input Current (Note 8) II640 640 pA
Large Signal Voltage Gain (See Figures 13, 28), (Note 6) AOL 63 63 kV/V
96 96 dB
Common Mode Rejection Ratio (See Figure 18) CMRR 32 32 µV/V
90 90 dB
Common Mode Input Voltage Range (See Figure 25) VICR -15 to +12.3 -15 to +12.3 V
Power Supply Rejection Ratio (See Figure 20) PSRR 150 150 µV/V
(VIO/V±)76 76 dB
Maximum Output Voltage (Note 7) (See Figures 24, 25) VOM+ 12.4 12.4 V
VOM- -14.2 -14.2 V
Supply Current (See Figure 16) Total For Both Amps I+ 8.4 8.4 mA
Total Device Dissipation PD252 252 mW
Temperature Coefficient of Input Offset Voltage VIO/T15 15µV/oC
NOTES:
6. At VO = 26VP-P, +12V, -14V and RL = 2k.
7. At RL = 2k.
8. At TA = 85oC.
Electrical Specifications For Equipment Design, at V+ = 5V, V- = 0V, TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL
TYPICAL VALUES
UNITSCA3240A CA3240
Input Offset Voltage |VIO|2 5mV
Input Offset Current |IIO| 0.1 0.1 pA
Input Current II22pA
Input Resistance RIN 11T
Large Signal Voltage Gain (See Figures 13, 28) AOL 100 100 kV/V
100 100 dB
CA3240, CA3240A
3-118
Common-Mode Rejection Ratio CMRR 32 32 µV/V
90 90 dB
Common-Mode Input Voltage Range (See Figure 25) VICR -0.5 -0.5 V
2.6 2.6 V
Power Supply Rejection Ratio PSRR 31.6 31.6 µV/V
90 90 dB
Maximum Output Voltage (See Figures 24, 25) VOM+3 3 V
V
OM- 0.3 0.3 V
Maximum Output Current Source IOM+20 20mA
Sink IOM-1 1mA
Slew Rate (See Figure 15) SR 7 7 V/µs
Gain Bandwidth Product (See Figure 14) fT4.5 4.5 MHz
Supply Current (See Figure 16) I+ 4 4 mA
Device Dissipation PD20 20 mW
Electrical Specifications For Equipment Design, at V+ = 5V, V- = 0V, TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL
TYPICAL VALUES
UNITSCA3240A CA3240
Test Circuits and Waveforms
FIGURE 1A. SMALL SIGNAL RESPONSE FIGURE 1B. LARGE SIGNAL RESPONSE
FIGURE 1C. TEST CIRCUIT
FIGURE 1. SPLIT-SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS
50mV/Div., 200ns/Div.
Top Trace: Input, Bottom Trace: Output 5V/Div., 1µs/Div.
Top Trace: Input, Bottom Trace: Output
2k
10k
CA3240
+15V
-15V
0.1µF
0.1µF
100pF
SIMULATED
LOAD
2k
0.05µF
+
-
BW (-3dB) = 4.5MHz
SR = 9V/µs
CA3240, CA3240A
3-119
Schematic Diagram
(One Amplifier of Two)
FIGURE 2. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEB AND NOISE MEASUREMENT
Test Circuits and Waveforms
(Continued)
RS
CA3240
+15V
-15V
0.01µF
0.01µF
+
-
BW (-3dB) = 140kHz
TOTAL NOISE VOLTAGE
30.1k
1k
1M
(REFERRED TO INPUT) = 48µV (TYP)
NOISE
VOLTAGE
OUTPUT
BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK V+
OUTPUT
V-
OFFSET NULL (NOTE 9)
INVERTING
INPUT
NON-INVERTING
INPUT +
-
R1
8K
Q1
D1
Q6
Q7
Q8
Q2
Q5Q4
Q3
D2D3D4
D5
Q9Q10
R2
500
R5
500
R4
500
R3
500
Q11 Q12
Q13
C1
12pF
Q14
R6
50R7
30
Q15 Q16
R8
1K
R11
20
Q17
R10
1K
R9
50
D7
D8
Q20
Q21
R12
12K
R14
20K
R13
15K
D6
Q18
Q19
NOTES:
9. Only available with 14 Lead DIP (E1 Suffix).
10. All resistance values are in ohms.
CA3240, CA3240A
3-120
Application Information
Circuit Description
The schematic diagram details one amplifier section of the
CA3240. It consists of a diff erential amplifier stage using PMOS
transistors (Q9 and Q10) with gate-to-source protection against
static discharge damage provided by zener diodes D3, D4, and
D5. Constant current bias is applied to the differential amplifier
from transistors Q2 and Q5 connected as a constant current
source. This assures a high common-mode rejection ratio. The
output of the differential amplifier is coupled to the base of gain
stage transistor Q13 by means of an NPN current mirror that
supplies the required differential-to-single-ended conversion.
Provision for offset null for types in the 14 lead plastic package
(E1 suffix) is provided through the use of this current mirror.
The gain stage transistor Q 13 has a high impedance activ e load
(Q3 and Q4) to pro vide maximum open-loop gain. The collector
of Q13 directly drives the base of the compound emitter-f ollow er
output stage. Pulldown for the output stage is provided by two
independent circuits: (1) constant-current-connected transistors
Q14 and Q15 and (2) dynamic current-sink transistor Q16 and
its associated circuitry.
The le v el of pulldo wn current is constant
at about 1mA for Q
15
and varies from 0 to 18mA for Q
16
depending on the magnitude of the voltage between the output
terminal and V+.
The dynamic current sink becomes active
whenever the output terminal is more negative than V+ by
about 15V. When this condition exists, transistors Q21 and Q16
are turned on causing Q16 to sink current from the output termi-
nal to V-. This current always flows when the output is in the lin-
ear region, either from the load resistor or from the emitter of
Q18 if no load resistor is present. The purpose of this dynamic
sink is to permit the output to go within 0.2V (VCE (sat)) of V-
with a 2k load to ground.
When the load is returned to V+, it
may be necessar y to supplement the 1mA of current from Q
15
in order to turn on the dynamic current sink (Q
16
).
This may be
accomplished by placing a resistor (Approx. 2k) between the
output and V-.
Output Circuit Considerations
Figure 24 shows output current-sinking capabilities of the
CA3240 at various supply voltages. Output voltage swing to
the negative supply rail permits this device to operate both
power transistors and thyristors directly without the need for
level-shifting circuitry usually associated with the 741 ser ies
of operational amplifiers.
Figure 3 shows some typical configurations. Note that a series
resistor, RL, is used in both cases to limit the dr ive available to
the driven device. Moreover, it is recommended that a series
diode and shunt diode be used at the thyristor input to prevent
large negative transient surges that can appear at the gate of
th yristors, from damaging the integr ated circuit.
Input Circuit Considerations
As indicated by the typical VICR, this device will accept
inputs as low as 0.5V below V-. However, a series current-
limiting resistor is recommended to limit the maximum input
terminal current to less than 1mA to prevent damage to the
input protection circuitry.
Moreover, some current-limiting resistance should be pro-
vided between the inverting input and the output when the
CA3240 is used as a unity-gain voltage follower. This resis-
tance prevents the possibility of extremely large input-signal
transients from forcing a signal through the input-protection
network and directly driving the internal constant-current
source which could result in positive feedback via the output
terminal. A 3.9kW resistor is sufficient.
The typical input current is on the order of 10pA when the
inputs are centered at nominal device dissipation. As the
output supplies load current, de vice dissipation will increase,
rasing the chip temperature and resulting in increased input
current. Figure 4 shows typical input-terminal current versus
ambient temperature for the CA3240.
It is well known that MOSFET devices can exhibit slight
changes in characteristics (for example, small changes in
input offset voltage) due to the application of large differen-
tial input voltages that are sustained over long periods at
elevated temperatures.
CA3240
RS
RLMT1
MT2
120VAC
LOAD
30V NO LOAD
CA3240
LOAD
RL
V+ +HV
FIGURE 3. METHODS OF UTILIZING THE VCE (SAT) SINKING
CURRENT CAPABILITY OF THE CA3240 SERIES
VS = ±15V
TEMPERATURE (oC)
-60 -40 -20 0 20 40 60 80 100 120 140
100
10
INPUT CURRENT (pA)
1K
10K
FIGURE 4. INPUT CURRENT vs TEMPERATURE
CA3240, CA3240A
3-121
Both applied voltage and temperature accelerate these
changes. The process is reversible and offset voltage shifts
of the opposite polarity reverse the offset. In typical linear
applications, where the differential voltage is small and sym-
metrical, these incremental changes are of about the same
magnitude as those encountered in an operational amplifier
employing a bipolar transistor input stage.
Offset-Voltage Nulling
The input offset voltage of the CA3240AE1 and CA3240E1
can be nulled by connecting a 10k potentiometer between
Terminals 3 and 14 or 5 and 8 and retur ning its wiper arm to
Terminal 4, see Figure 5A. This technique, however, gives
more adjustment range than required and therefore, a consid-
erable portion of the potentiometer rotation is not fully utilized.
Typical values of series resistors that may be placed at either
end of the potentiometer, see Figure 5B, to optimize its utiliza-
tion range are given in the table “Electrical Specifications for
Equipment Design” shown on third page of this data sheetAn
alternate system is shown in Figure 5C. This circuit uses only
one additional resistor of approximately the value shown in
the table . F or potentiometers, in which the resistance does not
drop to 0 at either end of rotation, a value of resistance 10%
low er than the values shown in the table should be used.
Typical Applications
On/Off Touch Switch
The on/off touch switch shown in Figure 6 uses the
CA3240E to sense small currents flowing between two con-
tact points on a touch plate consisting of a PC board metalli-
zation “grid”. When the “on” plate is touched, current flows
between the two halves of the grid causing a positive shift in
the output voltage (Terminal 7) of the CA3240E. These posi-
tive transitions are fed into the CA3059, which is used as a
latching circuit and zero-crossing TRIAC driver. When a pos-
itive pulse occurs at Terminal 7 of the CA3240E, the TRIAC
is turned on and held on by the CA3059 and its associated
positive feedback circuitry (51k resistor and 36k/42k
voltage divider). When the positive pulse occurs at Ter minal
1 (CA3240E), the TRIAC is tur ned off and held off in a simi-
lar manner. Note that power for the CA3240E is supplied by
the CA3059 internal power supply.
The advantage of using the CA3240E in this circuit is that it
can sense the small currents associated with skin conduc-
tion while allowing sufficiently high circuit impedance to pro-
vide protection against electrical shock.
Dual Level Detector (Window Comparator)
Figure 7 illustrates a simple dual liquid level detector using
the CA3240E as the sensing amplifier. This circuit operates
on the principle that most liquids contain enough ions in
solution to sustain a small amount of current flow between
two electrodes submersed in the liquid. The current, induced
by an 0.5V potential applied between two halves of a PC
board grid, is converted to a voltage level by the CA3240E in
a circuit similar to that of the on/off touch switch shown in
Figure 6. The changes in voltage for both the upper and
lower level sensors are processed by the CA3140 to activate
an LED whenever the liquid level is above the upper sensor
or below the lower sensor..
FIGURE 5A. BASIC FIGURE 5B. IMPROVED RESOLUTION
FIGURE 5C. SIMPLER IMPROVED RESOLUTION
NOTE:
11. See Electrical Specification Table on Third page of this data sheet for value of R.
FIGURE 5. THREE OFFSET-VOLTAGE NULLING METHODS, (CA3240AE1, CA3240E1 ONLY)
CA3240
V+
4
13(9)
12(10)
3
(5)
14(8)
V-
1(7)
2(6)
10k
CA3240
V+
V-
10k
R (NOTE 11) R (NOTE 11)
CA3240
V+
V-
10k
R
(NOTE 11)
CA3240, CA3240A
3-122
Constant-Voltage/Constant-Current Power Supply
The constant-voltage/constant-current power supply shown
in Figure 8 uses the CA3240E1 as a voltage-error and cur-
rent-sensing amplifier. The CA3240E1 is ideal for this appli-
cation because its input common-mode voltage range
includes ground, allowing the supply to adjust from 20mV to
25V without requiring a negative supply voltage. Also, the
ground reference capability of the CA3240E1 allows it to
sense the voltage across the 1 current-sensing resistor in
the negative output lead of the power supply. The CA3086
transistor array functions as a reference for both constant-
voltage and constant-current limiting. The 2N6385 power
Darlington is used as the pass element and may be required
to dissipate as much as 40W. Figure 9 shows the transient
response of the supply during a 100mA to 1A load transition.
Precision Differential Amplifier
Figure 10 shows the CA3240E in the classical precision dif-
ferential amplifier circuit. The CA3240E is ideally suited for
biomedical applications because of its extremely high input
impedance. To insure patient safety, an extremely high elec-
trode series resistance is required to limit any current that
might result in patient discomfort in the ev ent of a fault condi-
tion. In this case, 10M resistors have been used to limit the
current to less than 2µA without affecting the perf ormance of
the circuit. Figure 11 shows a typical electrocardiogram
waveform obtained with this circuit.
NOTE:
12. At 220V operation, TRIAC should be T2300D, RS = 18K, 5W.
FIGURE 6. ON/OFF TOUCH SWITCH
FIGURE 7. DUAL LEVEL DETECTER
7
1
2
3
5
65
13
9
10
2
4
8
7
11
8
4
120V/220V
AC
60Hz/50Hz
10K (2W)
RS(NOTE 10)
12K MT2
MT1
G
40W
120V LIGHT
T2300B (NOTE 10)
51K
COMMON
+
-100µF (16V)
+6V SOURCE
1N914
1N914
42K
36K
+6V
+6V
44M
44M
CA3059
CA3240
CA3240
+
-
+
-
+6V
1M
5.1M
1M
0.01µF
0.01µF1M
“ON”
“OFF” 1/2
1/2
6
5
3
2
8
4
+15V
12M
12M
+15V
8.2K
240K
100K
100K
1
7
7
+15V
CA3140
+
-6
3
24
33K
100K
100K
160K
0.1µF
(0.5V)
HIGH
LEVEL
LOW
LEVEL
0.1µF
680
LED
LED ON WHEN
LIQUID OUTSIDE
OF LIMITS
CA3240
+
-1/2
CA3240
+
-
1/2
CA3240, CA3240A
3-123
FIGURE 8. CONSTANT-VOLTAGE/CONSTANT-CURRENT POWER SUPPLY
FIGURE 9. TRANSIENT RESPONSE
32
1
10
11
9
8
7
64
5
3
1
2
12
14
12 1
2
13
4
10
7
6
9
13
-
+
1/2
CA3240E1
2N6385
DARLINGTON
75
3K
2.7K
VI = 30V +
-2000µF
50V
CA3086E
TRANSISTOR
ARRAY
CHASSIS GROUND
2.2K
6.2K
1K
+
-5µF
16V
100K
100K
50K
100K
100
V+
V+
10K
+
-
1/2
CA3240E1
1N914
0.056µF
820680K
100K 1
1W
180K
82K
+
-500
µF
IO
VO
VO RANGE = 20mV TO 25V
LOAD REGULATION:
VOLTAGE <0.08%
CURRENT <0.05%
OUTPUT HUM AND NOISE 150µVRMS
(10MHz BANDWIDTH)
SINE REGULATION 0.1%/VO
IO RANGE = 10mA - 1.3A
Top Trace: Output Voltage;
500mV/Div., 5µs/Div.
Bottom Trace: Collector Of Load Switching Transistor
Load = 100mA to 1A; 5V/Div., 5µs/Div.
CA3240, CA3240A
3-124
Differential Light Detector
In the circuit shown in Figure 12, the CA3240E converts the
current from two photo diodes to voltage, and applies 1V of
reverse bias to the diodes. The voltages from the CA3240E
outputs are subtracted in the second stage (CA3140) so that
only the difference is amplified. In this manner, the circuit
can be used over a wide range of ambient light conditions
without circuit component adjustment. Also, when used with
a light source, the circuit will not be sensitive to changes in
light level as the source ages.
FIGURE 10. PRECISION DIFFERENTIAL AMPLIFIER
FIGURE 11. TYPICAL ELECTROCARIOGRAM WAVEFORM
1/2
CA3240
+
-
1/2
CA3240
+
-
1
2
3
6
57
3
2
6
4
CA3140
7
8
4
100K 1%
2000pF
+15V
0.1µF
OUTPUT
2K
5.1K
1%
1%
5.1K
-15V
100K 1%
100K 1%
2000pF
2000pF
0.1µF
+15V
0.1µF
0.1µF
-15V
100K
3.9K
10M
10M
GAIN
CONTROL
TWO COND.
SHIELDED
CABLE
FREQUENCY RESPONSE (-3dB) DC TO 1MHz
SLEW RATE = 1.5V/µs
COMMON MODE REJ: 86dB
GAIN RANGE: 35dB TO 60dB
Vertical: 1.0mV/Div.
Amplifier Gain = 100X
Scope Sensitivity = 0.1V/Div.
Horizontal: >0.2s/Div. (Uncal)
CA3240, CA3240A
3-125
FIGURE 12. DIFFERENTIAL LIGHT DETECTOR
Typical Performance Curves
FIGURE 13. OPEN LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE FIGURE 14. GAIN BANDWIDTH PRODUCT vs SUPPLY V OLTA GE
FIGURE 15. SLEW RA TE vs SUPPL Y VOLTAGE FIGURE 16. QUIESCENT SUPPLY CURRENT vs SUPPL Y V OL T AGE
3
2
+15V
6
2
37
+15V
CA3140
+
6
5
4
8
4
1
7
-15V
-15V
1/2
CA3240E
+
-
1/2
CA3240E
+
0.015µF
100K
0.015µF
100K
+15V
5.1K
1.3
13K
K
C30809
PHOTO
DIODE
C30809
PHOTO
DIODE
-
2K
200K
2K
OUTPUT
-
200k
RL = 2k
TA = -40oC
25oC
85oC
125
100
75
50
25
2520151050
OPEN LOOP VOLTAGE GAIN (dB)
SUPPLY VOLTAGE (V)
RL = 2k
CL = 100pF
TA = -40oC
0 5 10 15 20 25
SUPPLY VOLTAGE (V)
1
10
20
GAIN BANDWIDTH PRODUCT (MHz)
25oC
85oC
25oC
TA = -40oC
RL = 2k
5101520
SUPPLY VOLTAGE (V) 25
CL = 100pF
20
15
10
5
0
SLEW RATE (V/µs)
0
85oC
RL =
TA = -40oC25oC
85oC
10
9
8
7
6
5
4
3
20 5 10 15 20
SUPPLY VOLTAGE (V)
TOTAL SUPPLY CURRENT (mA)
FOR BOTH AMPS
25
CA3240, CA3240A
3-126
FIGURE 17. MAXIMUM OUTPUT VOLTA GE SWING vs
FREQUENCY FIGURE 18. COMMON MODE REJECTION RATIO vs
FREQUENCY
FIGURE 19. EQUIVALENT INPUT NOISE V OLTA GE vs
FREQUENCY FIGURE 20. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
FIGURE 21. OUTPUT SINK CURRENT vs OUTPUT VOLTA GE FIGURE 22. SUPPLY CURRENT vs OUTPUT V OLTA GE
Typical Performance Curves
(Continued)
25
20
15
10
5
0
OUTPUT VOLTAGE (VP-P)
10K 100K
FREQUENCY (Hz)
1M 4M
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC
120
100
80
60
40
20
0
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC
101102103104105106107
COMMON MODE REJECTION RATIO (dB)
FREQUENCY (Hz)
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC
FREQUENCY (Hz)
1101102103104105
EQUIVALENT INPUT NOISE V OLTAGE (nV/Hz)
100
10
1
1000
RS = 100
SUPPLY VOLTAGE: VS = ±15V
TA = 25oCPOWER SUPPLY
REJECTION RATIO = VIO/∆VS
-PSRR
+PSRR
100
80
60
40
20
101102103104105106107
FREQUENCY (Hz)
POWER SUPPLY REJECTION RATIO (dB)
TA = 25oC
VS = ±15V
12
10
8
6
4
2
0-15 -10 -5 0 5 10 15
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT (mA)
PER AMP
ONE AMPLIFIER OPERATING
TA = 25oC
17.5
-15 -10 -5 0 5 10 15
OUTPUT VOLTAGE (V)
VS = ±15V
15
12.5
10
7.5
5
2.5
SUPPLY CURRENT (mA)
PER AMP (DOUBLE FOR BOTH)
RL =
CA3240, CA3240A
3-127
FIGURE 23. CROSSTALK vs FREQUENCY FIGURE 24. VOLTAGE ACROSS OUTPUT TRANSISTORS Q15
AND Q16 vs LOAD CURRENT
FIGURE 25A. FIGURE 25B.
FIGURE 25. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
Typical Performance Curves
(Continued)
TA = 25oC
AMP A AMP B
AMP B AMP A
VS = ±15V
VO = 5VRMS
140
130
120
110
100
90
80
0.1 1 101102103
CROSSTALK (dB)
FREQUENCY (Hz)
1.0
0.01 0.1
LOAD (SINKING) CURRENT (mA)
1.0 10
10
100
1000
OUTPUT STAGE TRANSISTOR (Q15, Q16)
SATURATION VOLTAGE (mV)
V- = 0V
TA = 25oC
V+ = +5V +15V
+30V
TA = -40oC
TA = 25oCTA = -40oC
TA = 25oC
TA = 85oC
TA = 85oC
RL =
0
-0.5
-1
-1.5
-2
-2.5
-3
0 5 10 15 20 25
SUPPLY VOLTAGE (V)
INPUT AND OUTPUT VOLTAGE
REFERENCED TO TERMINAL 7 (V)
OUTPUT VOLTAGE (+VO)
COMMON MODE VOLTAGE (+VICR)
TA = -40oC TO 85oC
TA = 85oC
TA = -40oCTA = 25oC
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
INPUT AND OUTPUT VOLTAGE
REFERENCED TO TERMINAL 4 (V)
0510152025
SUPPLY VOLTAGE (V)
RL =
OUTPUT VOLTAGE (+VO)
COMMON MODE VOLTAGE (+VICR)
CA3240, CA3240A
3-128
FIGURE 26A. SETTLING TIME vs INPUT VOLTAGE FIGURE 26B. TEST CIRCUIT (FOLLOWER)
FIGURE 26C. TEST CIRCUIT (INVERTING)
FIGURE 26. INPUT VOLTAGE vs SETTLING TIME
FIGURE 27. INPUT CURRENT vs TEMPERATURE FIGURE 28. OPEN LOOP VOLTAGE GAIN AND PHASE vs
FREQUENCY
Typical Performance Curves
(Continued)
0.1
INPUT VOLTAGE (V)
1.0 10
2468
SUPPLY VOLTAGE: VS = ±15V
TA = 25oC, RL = 2k, CL = 100pF
1mV
10mV
2468
10mV
1mV
1mV
1mV
10mV 10mV
FOLLOWER
INVERTING
10
8
6
4
2
0
-2
-4
-6
-8
-10
TIME (µs)
2k
10kCA3240
+15V
-15V
0.1µF
0.1µF
100pF
SIMULATED
LOAD
2k
0.05µF
+
-
5k
2k
5.11k
4.99k
5k
200
CA3240
+15V
-15V
0.1µF
0.1µF
100pF
SIMULATED
LOAD
D2
D1
1N914 1N914
SETTLING POINT
-
+
VS = ±15V
TEMPERATURE (oC)
-60 -40 -20 0 20 40 60 80 100 120 140
INPUT CURRENT (pA)
1K
100
1
10K
10
101103104105106107108
FREQUENCY (Hz)
OPEN LOOP VOLTAGE GAIN (dB)
100
80
60
40
20
0
VS = ±15V
TA = 25oC
102
OPEN LOOP PHASE (DEGREES)
-75
-90
-105
-120
-135
-150
RL = 2k ,
CL = 0pF
PHASE
RL = 2k ,
CL = 100pF
GAIN
CA3240, CA3240A