


SDFS063AD2932, MARCH 1987 − REVISED OCTOBER 1993
Copyright 1993, Texas Instruments Incorporated
2−1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
Package Options Include Plastic
Small-Outline (SOIC) and Shrink
Small-Outline (SSOP) Packages, Ceramic
Chip Carriers, and Plastic and Ceramic
DIPs
description
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. Taken together with the F240 and
F241, these devices provide the choice of
selected combinations of inverting and
noninverting outputs, symmetrical OE (active-low
output-enable) inputs, and complementary OE
and OE inputs.
The F244 is organized as two 4-bit buffers/line
drivers with separate output enable (OE) inputs.
When OE is low, the device passes data from the
A inputs to the Y outputs. When OE is high, the
outputs are in the high-impedance state.
The SN74F244 is available in TI’s shrink
small-outline package (DB), which provides the
same I/O pin count and functionality of standard
small-outline packages in less than half the
printed-circuit-board area.
The SN54F244 is characterized for operation over
the full military temperature range of −55°C to
125°C. The SN74F244 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE A
OUTPUT
Y
L H H
LLL
H X Z
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
SN54F244 ...J PACKAGE
SN74F244 . . . DB, DW, OR N PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
SN54F244 . . . FK PACKAGE
(TOP VIEW)
2Y4
1A1
1OE
1Y4
2A2 2OE
2Y1
G
ND
2A1 VCC
  !"#$ % &'!!($ #%  )'*+&#$ ,#$(-
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2  #++ )#!#"($(!%-



SDFS063AD2932, MARCH 1987 − REVISED OCTOBER 1993
2−2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
logic symbollogic diagram (positive logic)
1
2
4
6
8
19
11
13
15
17 3
5
7
9
12
14
16
18
1A1
1A2
1A3
1A4
1Y1
2A1
2A2
2A3
2A4
2Y1
1Y2
1Y3
1Y4
2Y2
2Y3
2Y4
2OE
1OE
2
1A1 4
1A2 6
1A3 8
1A4
EN
1
1Y1
18
1Y2
16
1Y3
14
1Y4
12
11
2A1 13
2A2 15
2A3 17
2A4
EN
19
2Y1
9
2Y2
7
2Y3
5
2Y4
3
1OE
2OE
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) 1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range 30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state 0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state 0.5 V to VCC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state: SN54F244 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74F244 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54F244 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74F244 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.



SDFS063A − D2932, MARCH 1987 − REVISED OCTOBER 1993
2−3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
recommended operating conditions
SN54F244 SN74F244
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IIK Input clamp current −18 −18 mA
IOH High-level output current −12 −15 mA
IOL Low-level output current 48 64 mA
TAOperating free-air temperature −55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54F244 SN74F244
UNIT
PARAMETER
TEST CONDITIONS
MIN TYPMAX MIN TYPMAX
UNIT
VIK VCC = 4.5 V, II = −18 mA 1.2 1.2 V
IOH = − 3 mA 2.4 3.3 2.4 3.3
VOH
V
CC
= 4.5 V IOH = − 12 mA 2 3.2
V
VOH
VCC = 4.5 V
IOH = − 15 mA 2 3.1 V
VCC = 4.75 V, IOH = − 3 mA 2.7
VOL
VCC = 4.5 V
IOL = 48 mA 0.38 0.55
V
VOL VCC = 4.5 V IOL = 64 mA 0.42 0.55 V
IOZH VCC = 5.5 V, VO = 2.7 V 50 50 µA
IOZL VCC = 5.5 V, VO = 0.5 V −50 −50 µA
IIVCC = 5.5 V, VI = 7 V 0.1 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL
OE
VCC = 5.5 V,
VI = 0.5 V
−1 −1
mA
IIL Any A VCC = 5.5 V, VI = 0.5 V 1.6 1.6 mA
IOSVCC = 5.5 V, VO = 0 100 225 100 225 mA
VCC = 5.5 V,
Outputs high 40 60 40 60
I
CC
VCC = 5.5 V,
Outputs open
Outputs low 60 90 60 90 mA
ICC
Outputs open
Outputs disabled 60 90 60 90
mA
All typical values are at VCC = 5 V, TA = 25°C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.



SDFS063AD2932, MARCH 1987 − REVISED OCTOBER 1993
2−4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
switching characteristics (see Note 2)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500 ,
TA = 25°C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500,
TA = MIN to MAXUNIT
(INPUT)
(OUTPUT)
F244 SN54F244 SN74F244
MIN TYP MAX MIN MAX MIN MAX
tPLH
A
Y
1.7 3.6 5.2 2 6.5 1.7 6.2
ns
tPHL A
Y
1.7 3.6 5.2 2 7 1.7 6.5 ns
tPZH
OE
Y
1.2 3.9 5.7 2 7 1.2 6.7
ns
tPZL
OE
Y
1.2 5 7 2 8.5 1.2 8 ns
tPHZ
OE
Y
1.2 4.1 6 2 7 1.2 7
ns
tPLZ
OE
Y
1.2 4.1 6 2 7.5 1.2 7
ns
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 2: Load circuits and waveforms are shown in Section 1.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74F244DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74F244DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
SN74F244NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74F244DBR SSOP DB 20 2000 853.0 449.0 35.0
SN74F244DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74F244NSR SO NS 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Dec-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
18X 0.65
2X
5.85
20X 0.38
0.22
8.2
7.4 TYP
SEATING
PLANE
0.05 MIN
0.25
GAGE PLANE
0 -8
2 MAX
B5.6
5.0
NOTE 4
A
7.5
6.9
NOTE 3
0.95
0.55
(0.15) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
1
10 11
20
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
A 15
DETAIL A
TYPICAL
SCALE 2.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ALL AROUND 0.07 MIN
ALL AROUND
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
10 11
20
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
20X (1.85)
20X (0.45)
18X (0.65)
(7)
(R0.05) TYP
SSOP - 2 mm max heightDB0020A
SMALL OUTLINE PACKAGE
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
10 11
20
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
18X 1.27
20X 0.51
0.31
2X
11.43
TYP
0.33
0.10
0 - 8
0.3
0.1
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
13.0
12.6
B7.6
7.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
120
0.25 C A B
11
10
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
www.ti.com
EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )
TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
10 11
20
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
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