CY7C1034DV33
6-Mbit (256K X 24) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-08351 Rev. *E Revised September 29, 2011
Features
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 175 mA at f = 100 MHz
■Low CMOS standby power
❐ISB2 = 25 mA
■Operating voltages of 3.3 ± 0.3 V
■2.0 V data retention
■Automatic power-down when deselected
■T ransistor-transistor logic (TTL) compatible inputs and outputs
■Easy memory expansion with CE1, CE2, and CE3 features
■Available in Pb-free standard 119-Ball PBGA
Functional Description
The CY7C1034DV33 is a high performance CMOS static RAM
organized as 256K words by 24 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.
To write to the device, enable the chip (CE1 LOW, CE2 HIGH,
and CE3 LOW) while forcing the Write Enable (WE) input LOW .
T o read from the device, enable the chip by taking CE1 LOW, CE2
HIGH, and CE3 LOW , while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. See the Truth Table on page
7 for a complete description of Read and Write modes.
The 24 IO pins (IO0 to IO23) are placed in a high impedance state
when the device is deselected (CE1 HIGH, CE2 LOW, or CE3
HIGH) or when the output enable (OE) is HIGH during a write
operation. (CE1 LOW, CE2 HIGH, CE3 LOW, and WE LOW).
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
256K x 24
ARRAY
IO
0
– IO
23
OE
CE
1
, CE
2
, CE
3
WE
CONTROL LOGIC
Logic Block Diagram
A(9:0)
A(17:10)
CY7C1034DV33
Document Number: 001-08351 Rev. *E Page 2 of 12
Selection Guide
Description –10 Unit
Maximum access time 10 ns
Maximum operating current 175 mA
Maximum CMOS standby current 25 mA
Pin Configuration
Figure 1. 119-Ball PBGA Top View [1]
1 2 3 4 5 6 7
ANCAAAAANC
BNC A A CE1AANC
CIO12 NC CE2ACE
3NC IO0
DIO13 VDD VSS VSS VSS VDD IO1
EIO14 VSS VDD VSS VDD VSS IO2
FIO15 VDD VSS VSS VSS VDD IO3
GIO16 VSS VDD VSS VDD VSS IO4
HIO17 VDD VSS VSS VSS VDD IO5
JNC VSS VDD VSS VDD VSS NC
KIO18 VDD VSS VSS VSS VDD IO6
LIO19 VSS VDD VSS VDD VSS IO7
MIO20 VDD VSS VSS VSS VDD IO8
NIO21 VSS VDD VSS VDD VSS IO9
PIO22 VDD VSS VSS VSS VDD IO10
RIO23 NC NC NC NC NC IO11
TNC A A WE AANC
UNC A A OE AANC
Note
1. NC pins are not connected on the die.
CY7C1034DV33
Document Number: 001-08351 Rev. *E Page 3 of 12
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied .......................................... –55 C to +125 C
Supply Voltage on VCC Relative to GND [2]..–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State [2].................................–0.5 V to VCC + 0.5 V
DC Input Voltage [2] .............................–0.5 V to VCC + 0.5 V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................... ... ..............>2001 V
(MIL-STD-883, Method 3015)
Latch up Current......................................................>200 mA
Operating Range
Range Ambient
Temperature VCC
Industrial –40 C to +85 C 3.3 V 0.3 V
DC Electrical Characteristics
Over the operating range
Parameter Description Test Conditions [3] –10 Unit
Min Max
VOH Output HIGH voltage Min VCC, I OH = –4.0 mA 2.4 V
VOL Output LOW voltage Min VCC, IOL = 8.0 mA 0.4 V
VIH Input HIGH voltage 2.0 VCC + 0.3 V
VIL [2] Input LOW voltage –0.3 0.8 V
IIX Input leakage current GND < VIN < VCC –1 +1 A
IOZ Output leakage current GND < VOUT < VCC, output disabled –1 +1 A
ICC VCC operating supply current Max VCC, f = fMAX = 1/tRC,
IOUT = 0 mA CMOS levels 175 mA
ISB1 Automatic CE power-down
current — TTL inputs Max VCC, CE1, CE3 > VIH, CE2 < VIL,
VIN > VIH or VIN < VIL, f = fMAX 30 mA
ISB2 Automatic CE power-down
current — CMOS inputs Max VCC, CE1, CE3 > VCC – 0.3 V, CE2 < 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 25 mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 8 pF
COUT IO capacit ance 10 pF
Thermal Resist ance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions 119-Ball
PBGA Unit
JA Thermal resistance
(junction to ambient) Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board 20.31 C/W
JC Thermal resistance
(junction to case) 8.35 C/W
Notes
2. VIL (min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
3. CE refers to a combination of CE1, CE2, and CE3. CE is active LOW when CE1 is LOW, CE2 is HIGH, and CE3 is LOW. CE is HIGH when CE1 is HIGH or CE2 is LOW
or CE3 is HIGH.
CY7C1034DV33
Document Number: 001-08351 Rev. *E Page 4 of 12
AC Test Loads and Waveform [4]
AC Switching Characteristics
Over the operating range [5]
Parameter Description –10 Unit
Min Max
Read Cycle
tpower [6] VCC(Typical) to the first access 100 – s
tRC Read cycle time 10 – ns
tAA Address to data valid – 10 ns
tOHA Data hold from address change 3 – ns
tACE CE active LOW to data valid [3] –10ns
tDOE OE LOW to data valid – 5 ns
tLZOE OE LOW to low Z [7] 1–ns
tHZOE OE HIGH to high Z [7] –5ns
tLZCE CE active LOW to low Z [3, 7] 3–ns
tHZCE CE deselect HIGH to high Z [3, 7] –5ns
tPU CE active LOW to power-up [3, 8] 0–ns
tPD CE deselect HIGH to power-down [3, 8] –10ns
90%
10%
3.0V
GND
90%
10%
All input pulses
3.3V
OUTPUT 5 pF*
(a) (b)
R1 317
R2
351
Fall T ime:> 1V/ns
(c)
OUTPUT 50
Z0= 50
VTH = 1.5 V
30 pF*
*Capacitive Load consists of all
components of the test environment
Rise T ime > 1V/ns
*Including jig
and scope
Notes
4. Valid SRAM operation does not occur until the power supplies reach th e mi nimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD,
normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage.
5. Test conditions assume signal t ransi tio n ti me of 3 ns or less, t iming reference levels of 1. 5 V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of the AC Test Loads and Waveform [4], unless specified otherwise.
6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
7. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveform [4]. Transition is measured
200 mV from steady state voltage.
8. These parameters are guaranteed by design and are not tested.
CY7C1034DV33
Document Number: 001-08351 Rev. *E Page 5 of 12
Write Cycle [9, 10]
tWC Write cycle time 10 – ns
tSCE CE active LOW to write end [3] 7–ns
tAW Address setup to write end 7 – ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 7 – ns
tSD Data setup to write end 5.5 – ns
tHD Data hold from write end 0 – ns
tLZWE WE HIGH to low Z [7] 3–ns
tHZWE WE LOW to high Z [7] –5ns
Data Retention Characteristics
Over the operating range
Parameter Description Conditions [3] Min Typ Max Unit
VDR VCC for data retention 2 – – V
ICCDR Data retention current[9] VCC = 2 V, CE1, CE3 > VCC – 0.2 V,
CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V ––25 mA
tCDR [11] C hip deselect to data retention time 0 – – ns
tR [12] Operation recovery time tRC ––ns
Figure 2. Data Retention Waveform
AC Switching Characteristics (continued)
Over the operating range [5]
Parameter Description –10 Unit
Min Max
3.0V3.0V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
Notes
9. The internal write time of th e memory is defined by the overlap o f CE1 LOW , CE2 HIGH, CE3 LOW , and WE LOW. Chip enables must be active and WE must be L OW
to initiate a write and the transition of any of these signals terminates the write. The input data setup and hold timing are referenced to the leading edge of the signal
that terminates the write.
10.The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
11. Tested initially and after any design or process changes that may affect these parameters.
12.Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s.
CY7C1034DV33
Document Number: 001-08351 Rev. *E Page 6 of 12
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [13, 14]
Figure 4. Read Cycle No. 2 (OE Controlled) [3, 14, 15]
Figure 5. Write Cycle No. 1 (CE Controlled) [3, 16, 17]
PREVIOUS DATA VALID DATA OUT VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA I/O
50%
50%
DATA OUT VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
ICC
ISB
IMPEDANCE
OE
CE
ADDRESS
DATA I/O
VCC
SUPPLY
CURRENT
tWC
DATA IN VA LID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
WE
DATA I/O
ADDRESS
Notes
13.Device is continuously selected. OE, CE = VIL.
14.WE is HIGH for read cycle.
15.Address valid before or similar to CE transition LOW.
16.Data IO is high impedance if OE = VIH.
17.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
CY7C1034DV33
Document Number: 001-08351 Rev. *E Page 7 of 12
Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [3, 16, 17]
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [3, 17]
Truth Table
CE1CE2CE3OE WE IO0 – IO23 Mode Power
H XXXXHigh Z Power-down Standby (I
SB)
X L X X X High Z Power-down Standby (ISB)
X X H X X High Z Power-down Standby (ISB)
L H L L H Full Data Out Read Active (ICC)
L H L X L Full Data In Write Active (ICC)
L H L H H High Z Selected, outputs disabled Active (ICC)
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATA IN VALID
NOTE 18
CE
ADDRESS
WE
DATA I/O
OE
DATA IN VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
NOTE 18
CE
ADDRESS
WE
DATA I/O
Note
18.During this period, the IOs are in the output sta te and input signals are not applied.
CY7C1034DV33
Document Number: 001-08351 Rev. *E Page 8 of 12
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
10 CY7C1034DV33-10BGXI 51-85115 119-ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-free) Industrial
Ordering Code Definitions
Temperature Range:
I = Industrial
Package Type :
BGX = 119-ball PBGA (Pb-free)
Speed: 10 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technolo gy
4 = Data width × 24-bits
03 = 6-Mbit density
1 = Fast Asynchronous SRAM family
Tech nology Code: C = CMOS
7 = SRAM
CY = Cypress
CCY 1 - 10 BGX703 V33 ID4
CY7C1034DV33
Document Number: 001-08351 Rev. *E Page 9 of 12
Package Diagram
Figure 8. 119-ball PBGA (14 x 22 x 2. 4 m m)
51-85115 *C
CY7C1034DV33
Document Number: 001-08351 Rev. *E Page 10 of 12
Acronyms
Document Conventions
Units of Measure
Acronym Description
CMOS complementary metal oxide semiconductor
I/O input/output
SRAM static random access memory
TSOP thin small outline package
TTL transistor-transistor logic
Symbol Unit of Measure
°C degrees Celsius
Amicroamperes
mA milliamperes
MHz megahertz
ns nanoseconds
pF picofarads
Vvolts
ohms
Wwatts
CY7C1034DV33
Document Number: 001-08351 Rev. *E Page 11 of 12
Document History Page
Document Title: CY7C1034DV33 6-Mbit (256K X 24) Static RAM
Document Number: 001-08351
REV. ECN NO. Orig. of
Change Submission
Date Description of Change
** 469517 NXR See ECN New data sheet
*A 499604 NXR See ECN Added note 1 for NC pins
Changed ICC specification from 150 mA to 185 mA
Updated Test Condition for ICC in DC Electrical Characteristics table
Added note for tACE, t LZCE, tHZCE, t PU, tPD, tSCE in AC Switching Ch aracteristics
Table on page 4
*B 1462586 VKN/SFV See ECN Converted from preliminary to final
Updated block diagram
Changed ICC specification from 185 mA to 225 mA
Updated thermal specs
*C 2644842 VKN/PYRS 01/23/09 Replaced Comm ercial range with the Industrial
Replaced 8 ns speed with 10 ns
*D 3109199 PRAS 12/13/2010 Added Ordering Code Definitions.
Updated Package Diagram.
*E 3388455 TAVA 09/29/2011 Minor text edits. Added Acronyms and Document Conventions.
Updated temp late.
Document Number: 001-08351 Rev. *E Revised September 29, 201 1 Page 12 of 12
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1034DV33
© Cypress Semico nducto r Co rpor ation , 20 05-2 011. The information cont ai ned he rein is subj ect to chang e with out no tice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypres s pro d ucts ar e not war ran t ed no r int e nded to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n exp re ss wri tte n ag reement with Cypress. Furthermore, Cyp ress doe s not author i ze its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product t o be used only in conju nction with a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permis sion of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOS E. Cypress reserves the right to make changes without further notice to th e materials described herei n. Cypress d oes not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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